Abstract: There are provided a base member 14, a position restriction mechanism 15, a height restriction mechanism 17, an evenness holding mechanism, and an alignment mechanism 20, 22. A plurality of semiconductor modules is serially layered on the base member. Each semiconductor module comprises a semiconductor chip 7 mounted on a printed-wiring board 6 and a bump 13 formed on an interlayer connection land 8. The position restriction mechanism 15 restricts respective positions of the semiconductor modules 2 to be layered on the base member 14. The height restriction mechanism 17 restricts the height of the entire layered semiconductor module unit 4 layered on the base member 14. The evenness holding mechanism maintains evenness of the semiconductor module 2. The alignment mechanism 20, 22 aligns a mother substrate 5 on which a multilayer semiconductor module unit 4 is mounted.

Abstract: A semiconductor device (1) comprises a semiconductor substrate (2) on which an integrated circuit (3, 4) is formed, a first ground terminal (7) and a second ground terminal (8) for electrically connecting the integrated circuit (3, 4) to an external ground electrode, and an electrostatic breakdown protection element (5) for electrically connecting the first ground terminal (7) with the second ground terminal (8). The first ground terminal (7) is electrically connected with the semiconductor substrate (2), while the second ground terminal (8) is not electrically connected with the semiconductor substrate (2). A semiconductor device comprises a semiconductor substrate on which an integrated circuit is formed, a first ground terminal and a second ground terminal for electrically connecting the integrated circuit to an external ground electrode, and an electrostatic breakdown protection element for electrically connecting the first ground terminal with the second ground terminal.

Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.

Abstract: An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.

Abstract: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.

Abstract: There is disclosed a semiconductor device comprising at least two substrates, at least one wiring being provided in each of the substrates, the substrates being stacked such that major surfaces on one side of each thereof oppose each other and the wirings being connected between the major surfaces, and a plurality of connecting portions being provided adjacent to each other while connected to each wiring on the major surfaces opposing each other, at least one of the connecting portions provided on the same major surface being formed smaller than the adjacent other connecting portion, the connecting portions being provided at positions opposing each other one to one on the major surface, the connecting portions being connected so that the wirings are connected between the major surfaces, one connecting portion of a pair of the connecting portions connected one to one being formed smaller than the other connecting portion.

Abstract: A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.

Abstract: An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top surface of the substrate. A heat sink device is in thermal communication with the bottom surface of the substrate. Thermal conductive vias are in thermal communication to pass thermal energy from the at least one electronics package to the heat sink. At least some of the thermal conductive vias are formed extending from the top surface to the bottom surface of the substrate at an angle.

Abstract: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface of the first resin layer, and an external terminal which is formed to be electrically connected with the redistribution layer in a manner to avoid the pad.

Abstract: An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making an electrode structure by providing a substrate; forming a plurality of electrodes on the substrate; growing at least one nano-wire from the edge of a first electrode; and connecting the at least one nano-wire to the edge of a second electrode is also disclosed.

Abstract: A core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a core substrate using paste bumps comprising: (a) aligning a pair of paste bump boards, each of which has a plurality of paste bumps joined to its surface, such that the paste bumps face each other, and (b) pressing the pair of paste bump boards together, where an insulation element is placed between the pair of paste bump boards, it is easier to implement interlayer electrical interconnection between circuit patterns, the thickness of the core substrate can readily be adjusted by adjusting the thickness of the insulation layer, the stiffness is improved as a pair of paste bump boards are pressed from the top and bottom, and high-density wiring can be formed more easily as the paste bumps are connected in pairs so that the diameters of the paste bumps formed on the paste bump boards can be reduced.

Abstract: An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).

Abstract: The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

Abstract: Reinforced interconnection structures are provided. A reinforced interconnection structure comprises a first conductive layer formed in a first dielectric layer. A second conductive layer is formed in a second dielectric layer which overlies the first dielectric layer.

Abstract: Cells are formed on a substrate. First and second cell power wiring lines extend in a first direction on the substrate. First and second intermediate layer power wiring lines are formed on the first and second cell power lines. First upper layer power wiring lines are formed on the first and second intermediate layer power lines. The first upper layer power wiring lines extend in a second direction crossing the first direction at right angles. First contact members are formed between the first cell power lines and the first upper layer power lines. Second contact members are formed between the second cell power lines and the first upper layer power lines. The second contact members are arranged at positions shifted from a straight line which passes through the first contact members in the first direction and a straight line which passes through the first contact members in the second direction.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

Abstract: The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.

Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic polymer layer, forming a via hole by sequentially etching the upper porous oxide layer, the pyrolytic polymer layer, and the lower porous oxide layer, forming a trench having a width larger than a width of the via hole by sequentially etching the upper porous oxide layer and the pyrolytic polymer layer in such a manner that the trench is connected with the via hole, forming metal interconnections by filling the via hole and the trench with a metal thin film, and forming a vacuum between the upper and lower porous oxide layers by removing the pyrolytic polymer layer.

Abstract: A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.

Abstract: By replacing, in an otherwise copper-based metallization stack, copper with aluminum in the very last metal line layer, the respective terminal metal layer of conventional semiconductor devices may be omitted. Consequently, an enormous gain in production cost savings may be achieved, since a plurality of process steps may be omitted, while, on the other hand, substantially no performance degradation may result.

Abstract: A semiconductor device comprises at least one first electrode 11b provided on the front surface of a semiconductor chip and electrically connected to at least one of electrodes that constitute a transistor, a second electrode 9 provided on the back surface of the semiconductor chip and electrically connected to one of the other electrodes, a via hole penetrating the semiconductor chip from the front surface to the back surface, and a through electrode 11a a part of which is exposed on the front surface of the semiconductor chip electrically connected to the second electrode 9 through the via hole.

Abstract: Format data is subjected to the last memory function for each of one or more external inputs, and when the same input is re-selected in the next time or the power is turned on again, the data already subjected to the last memory function is output as an image with priority rather than the detection result of the present input. The image output control and the format detection of the present inputs are processed in parallel. Chip resistor includes the rectangular first substrate made of ceramics and having surfaces, the rectangular second substrate made of ceramics and having surfaces, and a joint layer interposed between the surfaces, and electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes. Further, electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes.

Abstract: The present invention provides a multi chip module which realizes high functions or high performances thereof. A multi chip module is constituted by stacking a first semiconductor chip on which a digital signal processing circuit is mounted, a second semiconductor chip which constitutes a dynamic random access memory, a third semiconductor chip which constitutes a non-volatile memory, and a mounting substrate thus forming the stacked structure. The first semiconductor chip is arranged on an uppermost layer with a spacer interposed on a back surface side thereof. The second semiconductor chip is arranged on the mounting substrate.

Abstract: An electronic component includes a substrate having contacts and a chip having contacts and a passivation layer disposed on an active side of the chip. The active side of the chip is mounted on a first surface of the substrate by flip chip technology such that the contacts of the chip are electrically connected to the contacts of the substrate by means of connecting elements. Elastic elevations are disposed between the contacts of the chip and the contacts of the substrate and an underfiller is disposed in an intermediate space between the chip and the substrate and between the elastic elevations. The underfiller and the elastic elevations have substantially the same modulus of elasticity.

Abstract: A flip chip package including a chip structure, a substrate and an under-fill is provided. The chip structure includes a base, a number of pads, a first passivation layer, a second passivation layer and a number of bumps. The pads are formed on the base. The first passivation layer is formed on the base and exposes the pads. The second passivation layer formed on the first passivation layer has a number of first openings and at least a second openings. The first openings are positioned on the pads. The second openings are positioned on the area other than the pads. The width at the bottom of the second opening is larger than the width of the second opening at the top. The bumps are formed on the pads. The substrate has a number of connecting points corresponding to the bumps.

Abstract: A flip chip architecture providing a hermetic seal. A flip chip die is assembled so as to be in contact with a package substrate. A pre-form of seal material is placed such that it surrounds the flip chip die and is in contact with the package substrate. The pre-form material is then processed so that it becomes a hermetic seal between the flip chip die and the substrate.

Abstract: A dicing and die bonding tape, comprising a substrate 1, a pressure sensitive adhesive layer (A) 2 superimposed on the substrate 1, a substrate 3 superimposed on the pressure sensitive adhesive layer (A) 2, a pressure sensitive adhesive layer (B) 4 superimposed on the substrate 3, and an adhesive layer 5 super imposed on the pressure sensitive adhesive layer (B) 4, said dicing and die bonding tape having an adhesion strength between the pressure sensitive adhesive layer (A) 2 and a dicing flame of 0.6 N/25 mm or larger, and an adhesion strength between the pressure sensitive adhesive layer (B) 4 and the adhesive layer 5 of from 0.05 to 0.5 N/25 mm.

Abstract: In an electronic component in which a semiconductor device such as a light emitting diode is encapsulated by an encapsulation resin and a manufacturing method of the same, formation of flash on occasion of filling a resin is prevented. The semiconductor device (SIC) is mounted in a reception concavity of a base member, and the encapsulation resin is filled into the reception concavity. After mounting the semiconductor device in the reception concavity and before filling the encapsulation resin into the reception concavity, a stopper resin layer is formed on a top face of the base member along a circumference of an aperture of the reception concavity by applying a resin.

Abstract: A separable connection is created between at least one transfer support and the conductor structure. The transfer support including the conductor structure and the substrate are joined together such that a connection that is stronger than the separable connection between the transfer support and the conductor structure is created between the conductor structure and the substrate. The separable connection between the transfer support and the conductor structure of the transfer support is separated while the connection between the conductor structure and the substrate remains intact. The method is particularly suitable for laterally disposing conductor structures comprising nanotubes at relatively low temperatures (T<600° C.), resulting in a substrate with a conductor structure which is connected to the substrate on a contact surface of the substrate and at least one additional contact surface of the substrate.

Abstract: To provide a carburetor in which, when a set screw is detached, a jet needle can also be detached along with the set screw. A carburetor of the variable venturi type has a venturi piston to adjust the venturi of an intake passage that is provided in a carburetor body. In the carburetor, the jet needle is attached as a unit with a cap member by screwing the cap member into the venturi piston. The carburetor includes a retaining mechanism, with help of which the cap member is engaged with the jet needle to form a single unit, when the cap member is detached from the venturi piston.

Abstract: An apparatus for vaporizing a liquid for subsequent thin film deposition on a substrate. The apparatus comprises a housing with an inlet and an outlet and a liquid reservoir. A mechanism controls the liquid level in the reservoir to a substantially constant level. A gas flow passageway extends along side a porous metal wall with interstitial spaces for containing liquid from the reservoir and with a package for a carrier gas to flow along side the porous metal wall, forming a gas/vapor mixture suitable for thin film deposition.

Abstract: In a tank for treating wastewater and including a first plurality of air diffuser elements and a second plurality of air diffuser elements, means for adjusting the relative height of the first diffuser elements with respect to the height of the second diffuser elements in response to changing operating conditions in the tank and changes in the characteristics of the diffusers.

Abstract: Method for producing a fibrous preform, especially by needling a fiber material (e.g., discontinuous pitch-based or PAN-based fiber). A needle-penetrable mold plate (10) having at least one mold cavity (12) therein for receiving the fiber material is provided. The use of a needle-penetrable mold plate allows the mold plate having the fiber material therein to be passed freely through a linear needling device, such as a linear needling loom, without having to take rigorous care to limit a needling path to the discontinuous fiber material, as in the conventional art. The mold plate is moved relative to the needling device one or more times until a desired level of material density (sometimes measured by fiber content percentage) is attained.

Abstract: An optical film manufacturing method, comprising steps of: forming a film by casting a liquid-state resin; embossing both ends of the formed film in a lateral direction of the film so as to form embossed sections for conveying the film; conveying the film having the embossed sections by a freely rotatable conveyance roller; trimming and removing the embossed sections of the film after the conveying step; and winding up the film.

Abstract: This invention relates generally to a method for treatment of lens surfaces by first coating the mold material with a reactive macromonomer and subsequently casting and curing the lens forming material along with the coating material present on the surface of the mold. The macromonomer reacts with the lens monomer mix and is covalently bound to the lens matrix. The modified lenses may ultimately show enhanced wettability, inhibition of bacterial adhesion and lower levels of protein and lipid deposition leading to increased comfort and longer wearing times.

Abstract: The methods of the invention employ electrostatic atomization to form a compound droplet of at least two miscible fluids. The compound droplet comprises a core of a first fluid and a layer of a second fluid completely surrounding the core. The first fluid contains the agent to be encapsulated and the second fluid contains an encapsulating agent. The first and second liquids are miscible. The encapsulated droplets can contain a variety of materials including, but not limited to, polynucleotides such as DNA and RNA, proteins, bioactive agents or drugs, food, pesticides, herbicides, fragrances, antifoulants, dyes, oils, inks, cosmetics, catalysts, detergents, curing agents, flavors, fuels, metals, paints, photographic agents, biocides, pigments, plasticizers, propellants and the like and components thereof. The droplets can be encapsulated by a variety of materials, including, but not limited to, lipid bilayers and polymer shells.

Abstract: An anti-solvent fluid technique is provided that assists in the formation, production and manufacture of fine particles including micro-sized and nanometer-sized particles for a wide variety of bio-medical and pharmaceutical applications. This technique is particularly effective for the manufacturing of polymers/biopolymers/drugs of micron, submicron or nano size as well as particle coating/encapsulation. Co-solvents are used to dissolve the polymer or mixture of polymers to make a solution. The method facilitates rapid drying of precipitated particles with reduced size and agglomerations.

Abstract: A method for making matting, wherein the method comprises forming a slurry into an uncured blanket, cutting a desired shape from the uncured blanket to form a mat precursor and uncured excess material, and feeding the uncured excess material into the slurry.

Abstract: A multilayer film includes a core layer having recycled, commercially used plastic therein and opposed skin layers, at least one of said opposed skin layers including a whitening agent or other pigmenting agent therein to mask any undesired coloration created by the recycled plastic. Laminations employing the above multilayer film also form part of this invention. A method of this invention for making a multilayer film including a core layer with recycled plastic therein includes the steps of: separating a plastic film or label from a package of commercial product; pelletizing the plastic film or label into pellets for introduction into an extruder of a film forming device and introducing the pelletized plastic film or label into said extruder for introducing the recycled plastic film or label pellets into a core layer of a multilayer film.

Abstract: Disclosed is a method for the production of a wood composite board comprising the steps of: providing a quantity of wood in the form of wood strands; drying the wood strands; coating the wood strands with a binder composition and diiodomethyl-p-tolylsulfone to from coated and treated strands; forming a mat from the coated and treated strands; pressing the mat, at a high temperature, to form the wood composite board having a final thickness.

Abstract: A devolatilizer nozzle comprising at least one perforated flow tube having a non-circular cross-section. In an embodiment, the non-circular cross-section has equal to or greater than 3 sides. The non-circular cross-section of said nozzle may be a triangle, diamond, pentagon, hexagon, heptagon, or octagon. A majority of the perforations in the flow tube of said nozzle may have a maximum strand angle of equal to or less than 45 degrees. The nozzle may further comprise tapered holes, which may be formed by a water jet. The nozzle may further comprise a plurality of parallel flow tubes. The nozzle may comprise 304 stainless steel, AL-6XN stainless steel, or LDX 2101 stainless steel.

Abstract: The invention is concerned with a mode of operation and a device to bring parallel fibres, threads or yarns from different delivery points and with individual unequal exit force to the same tension each with the others. The invention consists of three processing steps: decreasing the tension of the fibres from an arbitrary individual tension level to a tension level of about zero; slippage-free transport of the fibres through a slip lock unit with a known velocity determined beforehand; increasing the tension of each and every fibre from a tension level of about zero to the required collective tension level.

Abstract: In a method for producing a molded article having a resin part, the resin part is injection-molded to an opening of a main body part and the molded article has an excellent air-tightness between the resin part and the main body part. A foam sealant is attached to a peripheral portion around the opening of the main body part. Attached to the main body part is a retainer made of the same kind of resin as injected resin and adapted to keep the foam sealant compressed in its thickness direction. The main body part is placed within a mold so that the retainer is exposed inside a cavity of the mold. A molten resin is injected into the cavity of the mold. The injected resin and the retainer are integrated into the resin part.

Abstract: Composite tooling is fabricated with low cost dry fabrics and a neat resin instead of expensive prepregs. Dry, three-dimensional woven joint preforms are placed on a dry tool substrate and dry, 3D preforms are also placed between pre-cured egg crate-like junctions. The entire tool substrate and substrate-to-support structure joints are then resin-infused simultaneously through the use of rota-molded tooling aids, providing an additional reduction in cost. Tight control of resin content and distribution with vacuum infusion is thereby provided. This process eliminates the primary cause of structural weakness and cooling distortion, which typically occur at the attachment interface when existing methods are used. The preforms provide significantly greater pull-off strengths at interfaces than do hand-laid tie plies. Issues with tool surface durability are addressed through the use of ceramic-filled face coat.

Abstract: The two-sides in-mold decoration molding die includes a first mold on which the first decoration film is lengthwise movably disposed, and a second mold on which the second decoration film is laterally movably disposed and provided with a sprue and a runner, and a protruding section set higher than a region where the second decoration film passes is provided in a portion surrounding at least the runner, in an area directly confronting the first decoration film when the molds are clamped.

Abstract: Disclosed herein is a method for producing a molding compound resin tablet for wavelength conversion. The method comprises the steps of wet-dispersing a phosphor powder in a translucent liquid resin to form a molding compound resin body in which the phosphor powder is dispersed, and grinding the molding compound resin body into a powder form and applying a predetermined pressure to the resin powder. Further disclosed is a method for manufacturing a white light emitting diode using the molding compound resin tablet by a transfer molding process.

Abstract: A method for forming lugs of microSD ( Secure Digital ) including steps of: preparing a mold previously formed with multiple mold cavities, each mold cavity having a profile corresponding to a profile of a final glue-sealed microSD product with a lug; tightly closing the mold to hold the microSD units in the mold cavities; filling up glue material into the mold cavities; hardening the glue material in the mold cavities; opening the mold to take out the connecting board with the glue-sealed products; and cutting the connecting sections between the glue-sealed microSD products of the connecting board to achieve multiple microSD products.

Abstract: There is provided a stamper on which stamper-side concave/convex patterns are formed and which is capable of manufacturing an information recording medium on which at least servo patterns are formed by concave/convex patterns. First convex parts that are continuously formed along a direction corresponding to a radial direction of the information recording medium are formed in the stamper-side concave/convex patterns.