Abstract: In one embodiment, an organic light emitting diode (OLED) display is provided. The OLED display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting the first signal line, a first thin film transistor connected to the first and second signal lines, a second thin film transistor connected to the first thin film transistor, a first electrode connected to the second thin film transistor, a second electrode provided at least partially opposite to the first electrode, and a light emitting member formed between the first electrode and the second electrode, wherein at least one of the first thin film transistor and the second thin film transistor includes a plurality of semiconductor layers having different crystallinity.

Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.

Abstract: A mesa-type wide-gap semiconductor gate turn-off thyristor has a low gate withstand voltage and a large leakage current. Since the ionization rate of P-type impurities greatly increases at high temperatures when compared with that at room temperature, the hole implantation amount increases and the minority carrier lifetime becomes longer. Consequently, the maximum controllable current is significantly lowered when compared with that at room temperature. To solve these problems, a p-type base layer is formed on an n-type SiC cathode emitter layer which has a cathode electrode on one surface, and a thin n-type base layer is formed on the p-type base layer. A mesa-shaped p-type anode emitter layer is formed in the central region of the n-type base layer.

Abstract: A differential input/output device including an electro static discharge protection circuit is provided. The differential input/output device includes a P-type differential pair. The P-type differential pair includes two P-type transistors. The gate of each P-type transistor is coupled to an N-type transistor to protect the P-type transistor when CDM ESD occurs. Compared with the conventional technology, the protection device of the present invention provides a lower impedance current path when CDM ESD occurs in the input device.

Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.

Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.

Abstract: Arrangements are used to supply power to a semiconductor package.

Abstract: A semiconductor component arrangement is disclosed. In one embodiment, the semiconductor component arrangement includes a power transistor formed within a semiconductor layer in at least one first region and further semiconductor components formed at least in a second region, an effective thickness of the semiconductor layer being smaller in the first region than in the second region.

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract: A liquid crystal display device comprises: a first substrate and a second substrate facing and spaced apart from each other, the first substrate and the second substrate including an active area, a signal input area and a pad area, the signal input area and the pad area being disposed at a periphery of the active area; a gate line and a data line on the first substrate in the active area, the gate line and the data line crossing each other; first connection lines and second connection lines in the signal input area, the first connection lines extending to the pad area and crossing the second connection lines; a gate connection pattern contacting the first connection lines and the second connection lines; a common electrode on the second substrate; a shortage-preventing pattern on the common electrode and corresponding to the gate connection pattern; a seal pattern surrounding the active area, the seal pattern including a conductive ball; and a liquid crystal layer between the first and second substrates in th

Abstract: A rugged MESFET for power applications includes a drain region surrounded by a ring shaped gate. The gate is surrounded, in turn by a source region. This eliminates the high-field point between gate and drain along the device's etched mesa surface and results in improved avalanche capability.

Abstract: A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g.

Abstract: Disclosed is an organic light emitting display, which includes a large quantity of a hydroscopic layer having a good hydroscopic ability by changing a mounting structure of the hydroscopic layer. An organic light emitting display includes a first substrate. An organic emission portion is formed at one surface of the first substrate. A second substrate is formed at a surface of the first substrate on which the organic emission portion is formed for sealing the organic emission portion from external air. A first hydroscopic layer is formed between the first and second substrates. A third substrate is formed at another surface of the first substrate for sealing the first substrate. A second hydroscopic layer is formed between the first and third substrates.

Abstract: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may be a separate and individual transistor having the gate profile of a transfer gate or a reset gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor, adjusting the channel length of the transistor, or thinning the gate oxide on the transistor. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.

Abstract: A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors and a photodiode therein, wherein each transistor employs a gate insulator with a thickness ranging from 40 ? to 90 ?; and forming a logic circuit in the other predetermined location of the semiconductor substrate, the logic circuit having at least one transistor, wherein the transistor employs a gate insulator with a thickness ranging from 5 ? to 40 ?.

Abstract: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

Abstract: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager array. In the resulting structure, the conserved sections absorb incident light. The patterned portions of conserved material provide additional light shielding for array pixels.

Abstract: Methods and apparatuses are disclosed which provide imager devices having a light blocking material layer formed over peripheral circuitry outside a pixel cell array.

Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a planarization layer on the color filter layers, and having first micro-lens by intaglio in correspondence with the respective photosensitive patterns to condense the light secondly; and a plurality of second micro-lens layers on the planarization layer in correspondence with the respective photosensitive devices, to condense the light firstly.

Abstract: The invention provides a method of forming, on a substrate, a thin film of a perovskite type oxide in which at least either of a site A and a site B is constituted of plural elements and the plural elements in at least either site include elements different in valence number within such site, the method including steps of dividing the elements belonging to the site A and the site B in plural groups in such a manner that the elements different in valence number belong to a same group, and supplying the substrate with raw materials containing the elements belonging to such respective groups in respectively different steps.

Abstract: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) film over the oxygen barrier film; applying a thermal process to the titanium film in nitrogen atmosphere to allow the titanium film to turn into a titanium nitride (TiN) film; and forming a lower electrode film of a capacitor over the titanium nitride film.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate. Active regions are formed on the surface of the substrate, separated from one another by element separating regions and extend in a first direction. A first word line and a second word line extend in a second direction crossing the first direction. A pair of first select gate lines extend in the second direction between the first and second word lines. Memory cell transistors are each provided at each of intersections of the first and second word lines and the active regions on the surface of the substrate. First select gate transistors are each provided at each of intersections of the pair of first select gate lines and the active regions on the surface of the substrate. A first contact is provided between the pair of first select gate lines and contacts adjacent two of the active regions.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on a source side of the channel layer and a second thickness, thicker than the first thickness, on a drain side of the channel layer. Related methods of fabricating MESFETs are also provided herein.

Abstract: A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor units includes a first capacitor disposed in the first trench and a second capacitor disposed in the second trench. The isolation structure is disposed in the substrate between the first capacitor and the second capacitor. The conductive layer is disposed in the substrate above the isolation structure and electrically connected to the first upper electrode and the second upper electrode.

Abstract: A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are formed in the semiconductor body in a direction from the first contact to the second contact, wherein a basic doping density of the second semiconductor region is smaller than a doping density of the third semiconductor region, and wherein in the second semiconductor region a semiconductor zone of the second conductivity type is arranged in which the doping density is increased relative to the basic doping density of the second semiconductor region.

Abstract: A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.

Abstract: A memory cell having a low current memory device and a relatively high current output amplifier device, all built in the areawise footprint occupied by the memory device only. The low current memory device is a layered n-MOS or p-MOS lateral device having laterally spaced source and drain electrodes in a substrate and floating and control gates above the source and drain. The relatively high current output amplifier device is formed by contacts with layers or regions within layers having opposite conductivity types such that p-n junctions are arranged in forward and reverse bias configurations. These configurations form a vertical bipolar transistor that is beneath at least a portion of the lateral memory device and within the same footprint. The vertical bipolar transistor is connected as an output driver or amplifier for the memory device. An array of similar devices forms a memory array.

Abstract: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.

Abstract: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has: a first well formed in a substrate; a floating gate formed on the substrate through a gate insulating film to overlap a first region of the first well; first and second diffusion layers formed in the first well to contact the first region; and a MOS transistor whose gate electrode is the floating gate and through whose gate insulating film charges are transferred with respect to the floating gate. The first diffusion layer and the second diffusion layer are of opposite conductivity types.

Abstract: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has: a first well formed in a substrate; a floating gate formed on the substrate through a gate insulating film to overlap a first region of the first well; and first and second diffusion layers formed in the first well to contact the first region. A charge supply to the floating gate is performed through the gate insulating film between the first region and the floating gate. The first diffusion layer and the second diffusion layer are of opposite conductivity types and are provided such that efficiencies of the charge supply to the floating gate from respective of the first diffusion layer and the second diffusion layer are equal to each other.

Abstract: A method of forming a metal oxide layer having metal oxide particles and a binder for an electrochemical cell, comprises: depositing a layer of metal oxide; and depositing a polymeric linking agent onto the layer of metal oxide. Additionally, a method of forming an electrochemical cell comprises forming a metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; and applying a pressure to the metal oxide layer. Furthermore, an electrochemical cell comprising the metal oxide layer formed using the above mentioned method may be formed.

Abstract: A method of forming a metal oxide layer for an electrochemical cell is provided. The method includes: forming a plurality of adjacent metal oxide cells, spaced from one another; and performing localised heating of the plurality of adjacent metal oxide cells. A method of forming an electrochemical cell is also provided. The method includes: forming a first conductive oxide layer; forming the metal oxide layer on the first conductive layer; forming a functional dye layer on the metal oxide layer; and forming a second conductive layer; and providing an electrolyte between the functional dye layer and the second conductive layer, wherein at least one of the first and second conductive layers is transparent.

Abstract: A SONOS type non-volatile memory device includes a substrate having source/drain regions doped with impurities and a channel region between the source/drain regions. A tunnel insulation layer including silicon oxide is formed on the channel region of the substrate. A charge-trapping insulation layer including silicon nitride is formed on the tunnel insulation layer. A blocking insulation layer is formed on the charge-trapping insulation layer. The blocking insulation layer has a laminate layered structure in which a plurality of layers, at least one of which includes a metal oxide layer, are sequentially stacked. An electrode is formed on the blocking insulation layer.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A power IGBT includes a semiconductor body having an emitter zone of a first conduction type and a drift zone of a second conduction type proximate to the emitter zone. The IGBT further includes a cell array, each transistor cell of the array having a source zone, a body zone disposed between the source zone and the drift zone, the body zone and source zone short-circuited, and a gate electrode configured to be insulated with respect to the source zone and the body zone. The cell array has a first cell array section with a first cell density and a second cell array section with a second cell density that is lower than the first cell density. The emitter zone has a lower emitter efficiency in a region corresponding to the second cell array section than in a region corresponding to the first cell array section.

Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

Abstract: An integrated circuit device includes a substrate having a trench formed therein. An isolation layer is disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench. A buffer layer is disposed between the isolation layer and the trench. A gate insulating layer is disposed on the second sidewall portion of the trench and extends onto the substrate adjacent to the trench.

Abstract: An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on the substrate between the field oxide regions. Stacked hetero-doping rims are formed in the HV well and in self-alignment with outer edges of the gates. A buffer region of the first polarity type is formed in the HV well between and in self-alignment with inner edges of the gates. A drift region of the second polarity type is formed in the buffer region between and in self-alignment with inner edges of the gates. The drift region includes a region having a gradual dopant concentration change, and includes a drain region of the second polarity type.

Abstract: A method for manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate; forming an impurity diffusion layer in a region which includes an end of an active area adjacent to the isolation region; depositing a metal film on the semiconductor substrate; removing at least part of the metal film on the isolation region; and subjecting the metal film and the semiconductor substrate to a heat treatment, thereby forming a silicide film on the impurity diffusion layer in a self-aligned fashion.

Abstract: A negative differential resistance (NDR) transistor includes a gate stack formed from a gate, a barrier layer, and a dielectric layer formed between the gate and barrier layer. To enable the NDR characteristic of the transistor, the barrier layer is configured to dynamically transfer charge carriers to and from the channel region of the transistor (e.g., to a charge storage node between the barrier layer and the dielectric layer), thereby adjusting the threshold voltage of the transistor. An NDR transistor can also be formed with a gap between the edge of the source region and the edge of the gate (stack) to enhance the electric field in the portion of the channel region corresponding to the gap. The enhanced electric field can concentrate the distribution of charge carriers removed from the channel region in the proximity of the source region, thereby enhancing the NDR performance of the transistor.

Abstract: This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

Abstract: A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an electrical continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and a connecting portion that electrically connects the drive transistor with the initializing transistor. The power supply line includes a first portion extending in a predetermined direction. The electrical continuity portion and the connecting portion are formed from the same layer as that of the power supply line and are located on one side along the width of the first portion across the drive transistor.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is subjected to a heat treatment at a temperature of 900 to 1200° C. in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure. A system and method in accordance with the present invention utilizes a LDNMOS transistor as ESD protection element with optimised substrate contacts. The ratio of substrate contact rows to drain contact rows is smaller than one in order to reduce the triggering voltage of the inherent bipolar transistor.

Abstract: An electrostatic discharge protection device with a high trigger current includes a semiconductor layer, a well region formed in the semiconductor layer, an anode region formed in the well region, a cathode region formed in the semiconductor layer, a bridging region bridging a junction between the semiconductor layer and the well region, and a heavily doped P-region encircling the cathode region.

Abstract: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.