Abstract: An apparatus for generating a reference voltage in a semiconductor memory apparatus according includes: a first voltage generating unit that generates a voltage proportional to temperature; a second voltage generating unit that generates a voltage inversely proportional to temperature; and a reference voltage generating unit that adjusts the amount of current in the first voltage generating unit or the second voltage generating unit on the basis of a control signal, and outputs a constant reference voltage regardless of a variation in temperature. The apparatus can generate a constant reference voltage regardless of a variation in temperature and mismatch between elements. Thus, it is possible to improve the performance and reliability of a system using the apparatus to a maximum.

Abstract: Methods and apparatuses to sense current and voltage in circuits with voltage drop. In one aspect of the invention, a circuit includes a transistor coupled to a voltage reference. A light emitting diode (LED) is coupled to be driven by the transistor in response to a voltage across an output of the circuit. A first diode is coupled to the LED. A first resistor coupled to the first diode and the LED. The LED is coupled to be driven in response to a voltage drop across the first diode and the first resistor to sense a first current directed through the first diode and the first resistor.

Abstract: Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.

Abstract: A method and an apparatus for outputting an audio signal are provided. The apparatus includes a power source; a compensator for compensating an input signal by adding the input signal to an offset value reciprocally proportional to a source voltage; a pulse width modulator for modulating an audio signal transmitted from the compensator; and an output stage for outputting the modulated audio signal. Accordingly, audio quality can be improved directly for a listener by compensating the input signal damaged by periodical voltage drops.

Abstract: In an amplifying circuit, a first and a second switches are provided between an input terminal and output terminal of coupling capacitor and amplifier, and these switches are set in OFF state in a power-down state, and the second switch is turned on for a specified period when changed over to ordinary operation, and the capacitor is charged to a bias voltage corresponding to direct-current operating point, and then the second switch is turned off, and the first switch is turned on, and the mode is shifted to the ordinary operating state. Therefore, in a power-down state, a popping noise can be suppressed without resort to a charger for preliminarily charging the capacitor in a power-down state, and increase of current consumption due to charger is eliminated.

Abstract: A rectifier circuit powers three power conversion modules using a three phase AC input without a neutral connection. The rectifier circuit includes a first bridge rectifier that is connected to a first phase of the three phase AC input and that produces a first rectified waveform. A second bridge rectifier is connected to a second phase of the three phase AC input and produces a second rectified waveform. A third bridge rectifier is connected to a third phase of the three phase AC input and produces a third rectified waveform. A first inductor has one end that is connected to the first bridge rectifier. A second inductor has one end that is connected to the second bridge rectifier. A third inductor has one end that is connected to the third bridge rectifier. Opposite ends of the first, second and third inductors are connected to form a virtual neutral. A protection circuit prevents overvoltage when one of the DC outputs is shorted.

Abstract: A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Abstract: A RF variable gain amplifier with an extended linear tuning range is disclosed. The variable gain amplifier employs a wide swing cascode mirror formed by two cascode transistors and two gain transistors. The two cascode transistors track each other, so are the two gain transistor. The gain transistors operate on the saturation region.

Abstract: A variable gain power amplifier includes a power amplifying unit and a signal generating unit. The power amplifying unit includes a control terminal, and a gain of the power amplifying unit is variable by a control signal provided through the control terminal. The signal generating unit generates the control signal to be provided to the control terminal. The signal generating unit includes a switching circuit to be turned on and off by a binary signal, a constant current source that generates a constant current, and a variable current source that generates a variable current. Also, the signal generating unit generates, when the switching circuit is on, a control signal of a magnitude that turns on the power amplifying unit and depends on a magnitude of a sum of the constant current and the variable current. When the switching circuit is off, the signal generating unit generates a control signal of a magnitude that turns off the power amplifying unit.

Abstract: A wideband amplifier having an amplifier input terminal and an amplifier output terminal includes at least one transistor coupled to the amplifier input terminal and an impedance element coupled between the amplifier input terminal and the amplifier output terminal. A feedback signal is transmitted between the amplifier output terminal and the amplifier input terminal by way of the impedance element wherein the feedback signal varies in accordance with changes in an impedance of the impedance element so as to peak a frequency response of the amplifier.

Abstract: A CMOS class A/B output stage provides the advantages of high speed operation, low supply voltage requirements, and low quiescent current draw, resulting from the use of subthreshold biasing of the output driver transistors. The architecture of the output stage makes it particularly suitable for use in operational amplifiers in power demanding applications, such as portable instruments, smoke detectors, sensors, or the like.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A base station power amplifier for minimizing memory effect is provided. The power amplifier includes a bias circuit which supplies a direct current (DC) power to a transistor; the transistor which amplifies the DC power provided from the bias circuit; a matching circuit which transfers maximum power to a load by reducing loss of the power amplified by the transistor; and a large capacitor which lies between the matching circuit and the transistor, reduces a low-frequency second harmonic voltage by electrically connecting directly to the matching circuit, and has a preset capacitance value.

Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit, said current sensor producing an output current related to said common mode current; said active filter comprising a first and second transistor, each having first and second main electrodes and a control electrode, and an amplifier circuit driving said transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled to

Abstract: A method and apparatus for detecting capacitive devices are disclosed. A circuit including two circuit paths is connected to an oscillator voltage source. Connecting a test capacitive device to a path of the circuit modifies the electric potential waveform at a point along the path. Passing the first circuit path through a reference comparator and the second circuit path through a phase-shifting comparator produces two output signals that are phase-shifted with respect to each other when the test capacitive device is functional. Analysis of the output signals allows detection or measurement of the test capacitive device.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.

Abstract: A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output to input and to raise the resolution of the output frequency. First and second phase frequency detectors are used to measure the phase difference between the two input signals and generate a pulse corresponding to the phase difference. First and second reducing dividers are inserted before the first and second phase frequency detectors to decrease the input frequency of the respective phase frequency detector and keep the ratio of the input frequency and natural frequency (Wn) as a constant. A lock-state detector is used to detect whether the PLL is locked or unlocked. A charge pump is used to provide charge signals corresponding to the pulse.

Abstract: A plurality of variable load capacitance circuits is connected to each node between adjacent delay circuits of a ring oscillator, and changes load capacitance according to an external control signal. The control circuit adjusts timing the control signal is inputted to these variable load capacitance circuits, using a clock signal of one or more nodes of the ring oscillator.

Abstract: A surface mount crystal oscillator comprises a crystal blank, an IC chip having an oscillation circuit integrated thereon, and a hermetic package for accommodating the crystal blank and IC chip therein. The hermetic package comprises a substantially rectangular ceramic substrate formed with a metal film which makes a round on one main surface thereof, and a concave metal cover having an open end face bonded to the metal film. The IC chip is secured to the one main surface of the ceramic substrate through ultrasonic thermo-compression bonding using bumps, the crystal blank is disposed above the IC chip, and the ceramic substrate has the one main surface formed as a flat surface.

Abstract: An oscillator comprising a three-terminal device and circuitry coupled across a first terminal and a second terminal of the device. The circuitry is preferably operable to bias the device and feedback a select amount of noise generated by the device into the device so as to reduce a proportional amount of phase noise present at a third terminal of the device.

Abstract: A frequency generation unit (FGU) 160 includes a plurality of selectable voltage controlled oscillators (110) whose output frequencies are chosen in relationship with a predetermined intermediate frequency (IF) and frequency divider value (N) to provide multi-band frequency generation capability in a single communication device. A programmable reference divider (104), phase detector (174) and programmable charge pump (106) take an incoming reference frequency (120) and generate a charge pump output (124). A fixed loop filter (108) filters the charge pump output (124) to generate a control voltage (126) for the selectable VCOs (110). The desired frequency band is selected and enabled using control logic (128).

Abstract: A modulation apparatus which can be applied to the conventional analog PLL modulation system without using an enormous reference table, enables a phase distortion to be compensated accurately without requiring timing control with high accuracy, and can be applied to communication systems that do not perform amplitude modulation. In this apparatus, a signal generation section (101) generates a baseband phase signal. A phase distortion compensation section (102) obtains a phase distortion by multiplying a magnitude of a frequency change at predetermined time or magnitude of phase change between adjacent data of the baseband phase signal by a parameter specific to the apparatus, and thereby compensates the baseband phase signal for the phase distortion. A storage section (103) stores the parameter and calculation equation. A modulation section (105) modulates a frequency converted signal input from a frequency conversion section (104) using the baseband phase signal to generate a modulated signal.

Abstract: Circuit board (1) and method of producing thereof, the circuit board having a cavity for microstrip to waveguide transition means (2) defined by a hollow space on the walls of which a protection layer (21) is provided. A microelectronic substrate (33) is placed upon an adhesive film (31) adhered onto a surface of the circuit board (1), the adhesive film being pre-cut in selected areas (32) thereof providing openings therethrough. A metal layer (5) is disposed on the resulting structure, wherein a selected part (51) of the metal layer (5) present on a surface of microelectronics substrate 33, facing the hollow space defined by the cavity for microstrip to waveguide transition means (2) is removed.

Abstract: An SPNT switch has at least two operating states and comprises N circuit branches. Each circuit branch comprises a first input/output port connected to a second input/output port via a series active device, and a phase shifting component connected in series with a shunt active device. When the shunt active device is in an on state, the reflection co-efficient due to a path to ground from the series active device via the phase shifting component and the shunt active device is +1. At least one DC terminal controls the state of the active devices, whereby in one of the operating states of the switch, both active devices are in the on state simultaneously, and in another of the operating states, both active devices are in an off state simultaneously.

Abstract: A coupler is provided that includes a floating, exposed ground plane that can be partially removed to alter the coupling coefficient of the coupler's transmission lines. According to one embodiment, the coupler is formed using low temperature co-fired ceramic techniques to provide a small, stable and durable device suitable for installations in which miniaturization is required.

Abstract: The present invention is directed to a coupler structure that includes a first port, a second port, a third port, and a fourth port. L first transmission line layers are disposed in the structure. Each first transmission line layer includes a first transmission line conforming to a predetermined geometric configuration. The first transmission line is disposed on a first dielectric material between the first port and the second port. L is an integer. M second transmission line layers are disposed in alternating layers with the L first transmission line layers to form a total of N transmission line layers within the structure. M and N are integers and N is greater than or equal to three. Each second transmission line layer includes a second transmission line substantially conforming to the predetermined geometric configuration. The second transmission line is disposed on a second dielectric material between the third port and the fourth port.

Abstract: A combiner/splitter with distributed lines including a first line formed of a first planar winding in a first conductive level and of a second planar winding in a second conductive level; a second line formed of a third planar winding interdigited with the first winding in the first level, and of a fourth planar winding interdigited with the second winding in the second level; a first capacitive element connecting the external ends of the first and third windings; and a second capacitive element connecting the external ends of the second and fourth windings.

Abstract: A surface acoustic wave device in the present invention is provided with a piezoelectric substrate, a supporting substrate being jointed to the piezoelectric substrate and including a material different in expansion coefficient from the piezoelectric substrate and an interdigital electrode for exciting a surface acoustic wave, the electrode being arranged on the surface of the piezoelectric substrate. Either the interdigital electrode or the piezoelectric substrate is configured so that the interdigital electrode is 40% or more to 70% or less as long as the piezoelectric substrate in the direction to which a surface acoustic wave propagates.

Abstract: A ladder filter comprising a plurality of bulk acoustic wave resonators, the resonators comprising a plurality of series resonators series resonators in series between an input terminal and an output terminal of the filter, and one or more shunt resonators each connected between a junction between two series resonators and a common terminal, the series resonators comprising an input series resonator connected to the input terminal and an output series resonator connected to the output terminal, and wherein the shunt resonators are designed to satisfy: a unity aspect ratio and wherein the series resonators are designed to satisfy an aspect ratio different from unity. The aspect ratio is defined as the ratio of length to width of the resonator.

Abstract: The temperature-compensated film bulk acoustic resonator (FBAR) device comprises an FBAR stack that comprises an FBAR characterized by a resonant frequency having a temperature coefficient and a temperature-compensating layer comprising doped silicon dioxide. The FBAR comprises opposed planar electrodes and a piezoelectric element between the electrodes. The piezoelectric element has a temperature coefficient on which the temperature coefficient of the resonant frequency of the FBAR depends at least in part.

Abstract: A surface acoustic wave element 1 comprises a piezoelectric substrate 19, IDT electrodes 3, 4, 5 of an odd number not less than three formed along a propagation direction of surface acoustic waves that propagates on the piezoelectric substrate, wherein IDT electrodes 3, 5 of the odd number of IDT electrodes 3, 4, 5 disposed on both sides of an IDT electrode 4 that is located at the center are connected to first and second reference potential terminals 14, 15, respectively, and the first and second reference potential terminals 14 and 15 are formed asymmetrically with respect to a virtual central axis A that passes through the center of the IDT electrode 4 located at the center and provided in a direction perpendicular to the propagation direction.

Abstract: A bandpass filter includes a combline bandpass filter including tapped-line input and output terminals, at least three resonators, and a loading capacitor for each resonator. The bandpass filter further includes a plurality of loading inductors, each loading inductor being connected between one of the resonators and its respective loading capacitor; and a direct coupling capacitor connected between any two of the at least three resonators that are separated by at least one other resonator. By adding a direct coupling capacitor to a combline bandpass filter, an additional lower-passband side attenuation pole is created. The attenuation and rolloff characteristics of the lower-passband side can be controlled by altering the value of the direct coupling capacitance. By adding loading inductors to a combline bandpass filter, an upper-passband side attenuation pole is created. The attenuation and rolloff characteristics of the upper-passband side can be controlled by altering the value of the loading inductors.

Abstract: Provided is a dielectric waveguide filter. The filter includes: a multi-layered structure of dielectric substrates having first and second ground planes at its top and bottom; first, second, and third waveguide resonators disposed at multiple layers within the multi-layered structure; converters for signal transition between input/output ports and the first and third waveguide resonators; first vias for forming the first, second, and third waveguide resonators; and second vias disposed at a boundary surface of the first waveguide resonator and the third waveguide resonator.

Abstract: A resonator for magnetic resonance applications has a conductor element that extends from a first conductor end to a second conductor end. During operation of the conductor element at a resonance frequency, a resonance current oscillates from the first conductor end to the second conductor end and back. The conductor ends are coupled with one another via a circuit that tunes the conductor element to the resonance frequency. The conductor element is fashioned as a multi-layer conductor with a number of layers that exhibit layer ends at the conductor ends. The circuit causes layer currents that are of different magnitudes among one another to flow in the layers during operation of the conductor element at the resonance frequency.

Abstract: A cold mass for a superconducting magnet system in one example comprises a superconducting magnet, a cryogenic cooling circuit, and a magnet and cooling circuit support. The magnet and cooling circuit support comprises a substantially conductive coupler that serves to couple the superconducting magnet and the cryogenic cooling circuit. The cryogenic cooling circuit comprises an inlet path and a substantially upward outlet path. The inlet path avoids direct conductive thermal engagement with the substantially conductive coupler. The substantially upward outlet path comprises direct conductive thermal engagement with the substantially conductive coupler.

Abstract: A portable MRI or NMR imaging system comprising a cryogen vessel housing cooled equipment, said system being housed within a transportable container, said container being divided into at least three sections. A first section provides accommodation for an operator and access to equipment as required to operate the cooled equipment. A second section houses the cryogen vessel. A third section houses auxiliary equipment required for operation of the cooled equipment but which is not required to be accessed by the operator to operate the equipment. Also provided is a cryostat comprising an outer vacuum container, itself housing a cryogen vessel for containing cooled equipment, wherein space between the cryogen vessel and the outer vacuum container is evacuated. The outer vacuum container is in the form of at least a section of a standard shipping container.

Abstract: An electromagnetic switch has a magnetic core having a base member and a disc member. The disc member is made of plates laminated along a pulling direction and has an inner hole. The base member has both a first portion and a second portion having a groove on its outer surface and disposed in the hole. An inner portion of a particular plate among the plates is disposed in the groove so as to fasten the particular plate to the base member. When the core is magnetized in response to excitation of a coil, a plunger is moved toward the first portion of the core along the pulling direction, a movable contact moved with the plunger comes in contact with a fixed contact electrically connected with a motor, and electric power is supplied to the motor through the fixed and movable contacts.

Abstract: A solenoid actuator includes a pair of coils and a core body. The pair of the coils are coupled electrically to each other in series. The core body has a pair of magnets and a holding member, and moves with respect to the coils when the pair of the coils apply magnetic force to the pair of the magnets in substantially same direction. The magnets are inserted into the coils respectively. The holding member holds the pair of the magnets in common.

Abstract: A rotary transformer for coupling electrical power at a high level into a rotor operable at a high rotational speed without the introduction of undesirable electromagnetic torque and problems of dynamic mechanical instability comprises a stationary primary mounted in surrounding relationship with respect to the rotor, an electromagnetic shield having an exterior surface thereon mounted to the rotor, and a secondary mounted on the exterior surface of the shield. The secondary is connected in an electrical circuit with the load such that the application of an alternating current having a frequency of at least one (1) kilohertz to the primary produces an alternating electromagnetic field having flux lines in the secondary in the secondary oriented generally parallel to the axis of rotation. The alternation of the electromagnetic field induces a voltage in the secondary that generates an electric current to the load.

Abstract: An impact and vibration-resistant noise filter avoiding cracking of a core at the time of application of a vibration or impact. The noise filter includes a case and core. The case has a first case portion having a first wall portion, a second wall portion, and a first bottom wall portion. The first and second wall portions have first and second parting surfaces, respectively on the end surfaces thereof. The first bottom wall portion is positioned between the first and second wall portions. A first supporting piece 31B, whose base end is positioned on the side of the first bottom wall portion and whose free end extends toward the first parting surface, is formed on the first wall portion. Similarly, a second supporting piece is formed in the second wall portion. First and second presser pieces are formed respectively on the first and second bottom wall portions. The core is resiliently retained by the first and second supporting pieces, and first and the second presser pieces.

Abstract: A detachable transformer for contactless power system includes a first magnetic coupling element wound with coil and a second magnetic coupling element wound with coil. The first magnetic coupling element and the second magnetic coupling element are of symmetric shape and arranged in contactless manner to provide contactless power coupling. The first magnetic coupling element and the second magnetic coupling element are designed to have concave portion and convex portion on facing surface thereof. Therefore, the magnetic flux can be confined and the magnetic resistance is reduced to enhance conversion efficiency of the detachable transformer.

Abstract: A mode-switching transformer with a 1-to-4 impedance ratio having a first planar winding formed in a first conductive level from a first differential mode terminal outside of the winding; a second planar winding formed in a second conductive level from a second differential mode terminal outside of the winding; a via of interconnection of the central ends of the first and second windings intended to be connected to ground; and at least one third planar winding in one of the two conductive levels, interdigited with the first or the second winding from a first common-mode terminal outside of the winding, the internal end of the third winding being connected to the via for direct grounding.

Abstract: A noise filter available for various cable widths and capable of being easily attached to a cable. The noise filter has a first core having both ends to which first and second holding members and are attached, and a second core having both ends to which third and fourth holding members and are attached. First and second contacting portions and are formed on a first facing surface at the first core. Third and fourth contacting portions are formed on a second facing surface at the second core. When the first and second contacting portions are brought into contact with the third and fourth contacting portions an insertion hole is provided between the first and second contacting portions and between the first and second facing surfaces. The first and third holding members are coupled to each other by a retaining portion and retaining projection. The second and fourth holding members and are coupled to each other by a hinge portion.

Abstract: A component arrangement has a semiconductor body, a dielectric layer and a planar transformer. The semiconductor body includes a face. The planar transformer includes a primary winding, a first planar winding section, and a second planar winding section, each vertically spaced apart from each other. The first planar winding section forms at least a part of the secondary winding and has a first connection forming a first connection of the secondary winding. The dielectric layer is positioned on the face and isolates the primary winding from the first planar winding section. The second planar winding section is disposed between the first planar winding section and the primary winding.

Abstract: The present invention provides a plug with overload protection and a safety switch. It is comprised of an upper case, a bottom case, two conductive polar plates, two connective plates, two alloy plates, a safety switch, and a return spring. The main features are as follows: the end of one conductive polar plate is joined with an alloy plate by mortise and tenon joint, while the other alloy plate, located on the rear end of the said plate, is joined with the front end of the connective plate by mortise and tenon joint. Then it will become electric connected. Also, the protruding insulating plate that on the bottom of the upper safety switch is just located on the top of the gap between the two alloy plates.

Abstract: The invention relates to a programming apparatus for programming transmitter/receiver systems for contactless actuation of doors and gates. For actuation of a door or a gate by a transmitter of a transmitter/receiver system a transmitter code is read into an associated receiver and compared there with receiver codes. The programming apparatus according to the invention comprises a computer unit for management of the transmitter codes and the receiver codes of the transmitter/receiver systems. In addition, the programming apparatus according to the invention includes an input unit for definition of the transmitter codes and the receiver codes of the transmitter/receiver systems. Moreover, the programming apparatus according to the invention comprises an interface unit for connection of transmitters and receivers, by way of which receiver codes can be issued at connected receivers and transmitter codes at connected transmitters.

Abstract: A passive key fob reader for receiving a key fob and controlling actuation of a vehicle is provided with a “wake up” system that includes a sensor, such as a reed or Hall-effect switch which can sense the presence of a magnet on the key fob. The key fob is preferably provided with a magnet such that when inserted into the key fob reader, it wakes up the sensor, and causes the sensor to actuate a control to query the key fob and identify whether the key fob has an appropriate identification number. In a second embodiment, the sensor is located remotely from the key fob reader.