Abstract: A device in accordance with embodiments of the present invention comprises an atomic probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the atomic probe can include a core having a conductive coating. The core can comprise an insulating or conducting material, and the coating can comprise one or more of titanium nitride, platinum, diamond-like carbon, tungsten carbide, tungsten, and tungsten oxide. Atomic probes in accordance with the present invention can be applied to a phase change media, for example to form an indicia in the phase change media by changing the structure of a portion of the media from one of a crystalline or amorphous structure to the other of the crystalline and amorphous structure.

Abstract: A method and system is disclosed for preventing write errors in a Single Event Upset (SEU) hardened static random access memory (SRAM) cell. A compensating element has been connected to a feedback path of the SRAM cell. The compensating element operates to cancel out capacitive coupling generated in an active delay element of the SRAM cell. If the compensating element sufficiently cancels the effects of the capacitive coupling, a write error will not occur in the SRAM cell. The compensating element also occupies a smaller silicon area than other proposed solutions.

Abstract: A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground voltage, respectively. The power supply voltage line and the ground line are arranged so that a magnetic field generated by a current flowing through the power supply voltage line and a magnetic field generated by a current flowing through the ground line cancel each other in the memory array.

Abstract: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.

Abstract: A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

Abstract: A compact sense amplifier circuit for amplifying reading signal of an EPROM includes a bit line connected to cells of the EPROM and a transistor circuit for connecting a DC power source to the bit line. The transistor circuit includes a read circuit, a write circuit, a first path for passing current when a read signal for reading one of the cells that is not written is applied to the read circuit and a second path for passing current when a read signal for reading one of the cells that is written is applied to the read circuit. The first path and the second path are arranged to pass the same amount of current, thereby reducing sensor noises.

Abstract: An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed.

Abstract: A semiconductor memory device includes a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor which has a drain connected to a source of the first MOS transistor. Each of the word lines connects commonly the control gates of the first MOS transistors in a same row. Each of the select gate lines connects commonly the gates of the second MOS transistors in a same row. The switch elements, in an erase operation, electrically connect the select gate lines to a semiconductor substrate in which the memory cell array is formed.

Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

Abstract: A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data “one” is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data “one” bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data “one” values are to be programmed in parallel.

Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the NROM erase system is also described.

Abstract: A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (VDIFF) to a selected memory cell by providing a column line potential (VC) and a row line potential (VR). According to this method, VDIFF is increased by an increment less than a transistor threshold voltage (VT). It is then determined whether the increased VDIFF results in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying VDIFF and increasing VDIFF by an increment more than VT to set the selected memory cell to a one state.

Abstract: Method and apparatus for an interface to a system monitor (1600) is described. A controller (102) accessible via a port interface thereof (110) is configured for read/write access to configuration memory cells (1500) and for read access to status registers (1602). The configuration memory cells (1500) are addressable via a first address space, and the status registers (1602) are addressable via a second address space different from the first address space. The port interface (110) is configured to receive a plurality of signals including a data address signal (124) and a data clock signal (121). The data address signal (124) has address information for accessing either the first address space or the second address space.

Abstract: Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS latency, wherein the CAS latency control unit generates a signal for controlling the output driver by using time difference between the DLL clock signal and an external clock applied to the memory device from an exterior.

Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

Abstract: A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit outputs a redundancy judgment result of the redundancy replacement judging circuit chain. A semiconductor memory device includes the redundancy replacement judging circuit.

Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read out from the memory cell. The sense amplifier compares and amplifies the reference data and the cell data read from a memory cell. The voltage generator keeps constant rate of change with time of at least one potential supplied for a read operation for the time interval from readout of the cell data is started until completion of readout of the reference data.

Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Abstract: A method and apparatus for controlling a DRAM refresh rate. In one embodiment, a computer system includes a memory subsystem having a memory controller and one or more DRAM (dynamic random access memory) devices. The memory controller is configured to periodically initiate a refresh cycle to the one or more DRAM devices. The memory controller is also configured to monitor the temperature of the one or more DRAM devices. If the temperature exceeds a preset threshold, the memory controller is configured to increase the rate at which the periodic refresh cycle is performed.

Abstract: A non-volatile memory cell 100 includes a static latch 125 having a first terminal and a second terminal, a first transistor 124 having a first current electrode coupled to said first terminal of said static latch 125 and a fusible element 110 having a first terminal coupled to a second current electrode of the first transistor 125 and a second terminal coupled to a first power supply voltage terminal. In a particular embodiment, the non-volatile memory cell includes a fusible element programming circuit 140 coupled to the first terminal of said fusible element. In another particular embodiment, the non-volatile memory cell includes a cell preset circuit 120 coupled to a control electrode of the first transistor.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously.

Abstract: The present invention is intended to significantly enhance processing efficiency. The card-type semiconductor storage device has a first data communication line group for connecting nonvolatile memories in a first port to a controller block and a second data communication line group for connecting nonvolatile memories in a second port to the controller block.

Abstract: A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.

Abstract: A system to change a data window may include a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated in a predetermined sequence to latch a respective portion of the data from the bi-directional data bus so that each respective portion of the data has a longer data window at an output of each of the plurality of registers than at the respective input of each of the plurality of registers.

Abstract: Methods and apparatus determine if an intruder passes into a security zone that is associated with a waterfront asset. An embodiment of the invention provides a harbor fence system that is designed to be deployed in water around ships or other waterfront assets to serve as a line-of-demarcation in order to provide protection. The harbor fence system comprises a series of spars that protrude above the water surface and that are connected with an electrical computer with a telemetry subsystem. Each spar contains electronic sensors, e.g. water immersion sensors and accelerometers, and circuitry to detect an intrusion and to communicate the location of the intrusion to a computer control station. The embodiment also facilitates deploying and retrieving the harbor fence system. Additionally, the embodiment may also determine whether an underwater intruder is passing under a protective boundary, in which the harbor fence system interfaces to an underwater sonar sensor subsystem.

Abstract: A system and method is provided for determining the three dimensional location of an acoustic event using a system of five or more sound sensing elements. The sensing elements are positioned at substantially the same elevation and in spatially distributed locations with respect to the acoustic event. The sensing elements generate notification signals indicating occurrence of the acoustic event. A central processor receives the notification signals, associates the locations of each of the sensing elements with the time at which each sensing element sensed the sound, determines the speed of sound for the medium, and calculates a three dimensional location for the acoustic event using a linear error minimization algorithm. A system of six or more sensing elements enables the processor further to discriminate between near simultaneous acoustic events.

Abstract: A system for identifying flash events including an optical imaging module with one or more optical imaging array, the optical imaging module configured for monitoring a region of interest to identify a tentative flash event. The system further includes a ranging module associated with the optical imaging module and configured to derive an estimated range to a location of the tentative flash event, and an acoustic verification module associated with the ranging module and with one or more acoustic sensor. The acoustic verification module is configured to determine whether an acoustic event corresponding to the tentative flash event is detected within a time window derived from the estimated range, thereby classifying the tentative flash event as either a verified flash event or a rejected flash event.

Abstract: A magneto-optical disk which reproduces information with an optical pickup head which uses an electromagnetic force as the driving force is provided. Other areas than at least the recording track are magnetized uniformly in a direction of canceling the influence of external magnetic field applied by the optical pickup head or a recording pattern having a frequency higher than modulation transfer function (MTF) of the optical pickup head is recorded to the other areas than at least the recording track. Read signals SP12 and SP14 from the magneto-optical disk are low in bit error rate.

Abstract: A power supply module removably disposed within an automated data storage and retrieval system. An automated data storage and retrieval system which includes one or more power supply modules removably disposed therein. An accessor movably disposed with an automated data storage and retrieval system comprising a gripper mechanism which can be releaseably attached to a power supply module. A method to supply power to an automated data storage and retrieval system. A method to monitor the operation of a power supply module removably disposed within an automated data storage and retrieval system.

Abstract: A focus search control unit for outputting an order to move an objective lens to the vicinity of a targeted position is provided with a trajectory generating unit for generating a position trajectory to move the objective lens such that the objective lens approaches the targeted position gradually. The position trajectory output from the trajectory generating unit is a position trajectory with which resonance frequency components that the lens moving unit has are removed or attenuated by making smooth the variation of acceleration of the objective lens moved by the lens moving unit. The position trajectory is defined by, for example, a function of third order or higher with respect to time.

Abstract: A write-once optical recording medium, and a method and apparatus for recording management information on the recording medium are provided. The method includes recording, in a temporary defect management area (TDMA), management information produced while the recording medium is in use, and transferring and recording the latest management information of the TDMA in a final defect management area (DMA) of the recording medium at a DMA fill-in stage of the recording medium.

Abstract: An optical disk control device comprises a playback signal detection unit for detecting data recorded on a disk by irradiating the disk with a converged light beam; a signal switching unit for successively selecting plural data signals obtained by the playback signal detection unit, and performing time-division-multiplexing on the selected signals; an A/D conversion unit for converting an analog signal which has been time-division-multiplexed by the signal switching unit, into a digital signal; an A/D conversion command unit for generating an A/D conversion command of the A/D conversion unit; a serial transfer unit for serial-transferring the command signal generated by the A/D conversion command unit; a serial reception unit for receiving the signal from the serial transfer unit, and controlling the signal selection operation of the signal switching unit on the basis of the received signal; and an arithmetic unit for generating an optical disk drive controlling signal by performing arithmetic processing on t

Abstract: An optical disk device for recording data in an optical disk under ZCLV control is provided. The optical disk device divides the optical disk into a plurality of zones, and drives said optical disk at a linear velocity fixed in each zone but varied among the zones. At least one of the linear velocity and the number of zones of the optical disk is controlled in accordance with the amount of data to be recorded. Data recording time is reduced by dynamically changing at least one of the linear velocity and the number of zones of the optical disk in accordance with the amount of data to be recorded, rather than fixing the number of zones and the linear velocity thereof.

Abstract: In order to perform simultaneous recording and reproduction, a large capacity of buffer memories were required. In addition, it was difficult to record data while reproducing data which was recorded by a different apparatus. The present invention has an objective of providing an information recording medium, a simultaneous recording and reproduction method, and an information recording and reproduction apparatus which guarantee simultaneous recording and reproduction. The simultaneous recording and reproduction is guaranteed by reproducing data recorded in an area having at least a minimum size fulfilling the simultaneous recording and reproduction condition which allows for four access operations, recording data in an area having at least the same size, and performing reproduction and recording alternately by switching reproduction to recording when the data amount in the reproduction buffer becomes full and switching recording to reproduction when the data amount in the recording buffer becomes empty.

Abstract: A stabilization part stabilizes surface vibration of a flexible optical disk along a rotation axis direction of the optical disk by means of pressure difference of air flow created according to Bernoulli's law at a portion on which information writing/reading is performed, provided on a side of the optical disk opposite to a side on which information recording/reproducing is performed. In this case, areas are provide on the upstream side and down stream side along the disk rotation direction of the portion of the optical disk which is stabilized by said stabilization part, said areas of the optical disk not having pressure difference created thereon by the air flow.

Abstract: A method for adjusting an optical axis of an optical disc drive. The method includes the following steps. A first reflecting member is disposed on a turntable of the optical disc drive, and is rotated along with the turntable. A laser light is emitted on the first reflecting member by a laser collimator, and a normal vector of the turntable is measured based on a light point reflected to the laser collimator from the first reflecting member. A second reflecting member and a third reflecting member are disposed on a guide bar of the optical disc drive. A first initial vector and a second initial vector are measured based on a light point reflected to the laser collimator from the second reflecting member and the third reflecting member.

Abstract: A method for discriminating an optical disk is disclosed. Peak values and trough values of focus error signal and RF level signal are detected by an operation of focus search. Threshold levels for detecting each material layer of the optical disk are determined according to the peak values and the trough values. Thereafter another focus search for the optical disk is executed to calculate a thickness of the substrate and a distance between the first and the second recording layer of the optical disk according to the threshold levels. Thus the type of the optical disk can be discriminated.

Abstract: A method is disclosed for positioning an optical labeling mechanism substantially close to a particular track of a labeling surface on an optical disk. The method can include the operation of positioning the optical labeling mechanism adjacent to the particular track. A further operation can be measuring a first surface texture of the labeling surface using the optical labeling mechanism. Another operation can involve positioning the optical labeling mechanism adjacent to a different track. A further operation can be moving the optical labeling mechanism from the different track toward the particular track location. Another operation can involve measuring a second surface texture of the labeling surface using the optical labeling mechanism. A further operation can be comparing the first and second surface textures to determine if the optical labeling mechanism is positioned substantially near the particular track.

Abstract: A DVD seamless playback system has a first timer, a second timer, a register, a processor, a buffer, and a decoder. The processor is capable of parsing bit-streamed data and of setting count initial values of the first and the second timers alternatively if the data stored in the register is updated.

Abstract: An optical disc drive 1 of the present invention includes an electrically rewritable flash ROM 32 which stores firmware of the optical disc drive 1; means for judging whether or not the loaded optical disc 2 is a predetermined type of optical disc in which update data for updating the currently stored firmware is stored when the optical disc 2 is loaded into the optical disc drive 1; a buffer memory 31 for temporarily storing the update data recorded in the loaded optical disc 2 in the case where the judging means judges that the loaded optical disc 2 is the predetermined type of optical disc; and control means 9 for determining whether the currently stored firmware of the optical disc drive 1 should be updated with the update data based on the absence or presence of a predetermined signal (a signal outputted when an eject button is pushed), and updating the currently stored firmware with the update data stored in the buffer memory 31 in the case where it is determined that the currently stored firmware of th

Abstract: A method and device for recording multiple information volumes on a record carrier, usually called multi-session recording, has a mapping unit (31) for opening a session by recording intro data including a first buffer zone at the beginning of the start zone of the volume, and a session control block (SDCB) in a remaining blank area of the start zone after the buffer zone. The session control block includes volume data indicative of the status and the contents of the session. The session is closed by recording session control data indicating that the information volume is closed in the remaining blank area, and closure data after the last user information recorded in the data zone for constituting the end zone of the volume. Further, the device has a detecting unit (32) for retrieving the session control block from said start zone.

Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.

Abstract: When an extra-high density optical disc, a DVD having a recording density lower than that of the extra-high density optical disc, a CD having a recording density lower than that of the DVD, and a combined optical recording medium in which the extra-high density optical disc, DVD, and CD are appropriately combined and integrally stacked are selectively recorded or reproduced by an objective lens whose numerical aperture (NA) is set to 0.75 or more, the objective lens satisfies the following expression: t<a·f+b wherein t: an axial thickness of the objective lens, f: a focal distance of the objective lens, a: a coefficient, and b: a constant, and the coefficient a and the constant b satisfies that a=2.02, b=?1.94; a=2.08, b=?1.84; or a=2.11, b=?1.77.

Abstract: A polarizing optical element changes its optical reflectance and/or transmittance according to a polarization state of incoming light. The optical element includes: a first grating layer including multiple striped portions that extend in a predetermined direction; and a second grating layer including multiple striped portions that extend in that predetermined direction. Average grating pitches of the first and second grating layers are both defined to be shorter than the wavelength of the incoming light. The first grating layer is made of a first material that exhibits a light reflecting property to the incoming light. The second grating layer is made of a second material that reduces the reflection of the incoming light from the first grating layer.

Abstract: An optical disk apparatus which records/reproduces data on/from a plurality of types of optical disks. The optical disk apparatus has a plurality of laser diodes. Two laser light rays emanating from two laser diodes are coupled together by means of a coupling prism. The thus-coupled laser light is radiated onto an optical disk. A photodetector is disposed in close proximity to the coupling prism. The coupling prism guides, to the photodetector, a laser light component of at least one laser light ray of the two laser light to be coupled together, the component having not been radiated onto the optical disk on an optical path. Laser light which is not radiated onto the optical disk on the optical path includes diffracted light other than a main beam emanating from the laser diode or laser beam which has not been subjected to coupling at the coupling surface of the coupling prism.

Abstract: An increase in cost is minimized while realizing larger capacity. An optical disc 102 includes, from the bottom of the drawing: a substrate 104; a first information recording layer 108 formed on the substrate 104; and a first light transmission layer 110 having a thickness of about 20 ?m formed on the first information recording layer 108. A second information recording layer 114 is formed on the first light transmission layer 110, and a second light transmission layer 116 having a thickness of about 90 ?m is formed on the second information recording layer 114. A laser beam La is irradiated from the side of the second light transmission layer 116 to allow recording and/or reading of an information signal on/from the first and second information recording layers 108 and 114.

Abstract: In a 5×3 wavelet transform apparatus, a function-A module (11) calculates equations A1 and A2, a function-B module (12) calculates equations B1 and B2, function-C0 module (13) calculates an equation C0, and a function-C1 module (14) calculates an equation C1. Selectors have terminals thereof set to “1” for a forward transform, and to “0” for an inverse transform. The equations A1 and B1 are applied for reversible transform, and A2 and B2 are applied for irreversible transform. The aforementioned equations are as follows: Aout=RoundOff {(Ain0+Ain1+0×2000)>>2}. A1 Aout=0.25*(Ain0+Ain1). A2 Bout=RoundOff(Bin0+Bin1). B1 Bout=0.5*(Bin0+Bin1). B2 C0out=C0in0+C1in1. C0 C1out=C0in0?C1in1. C1.