Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Abstract: A level shifter ESD protection circuit with power-on-sequence consideration used for receiving a first signal and outputting a second signal is provided. The level shifter circuit includes an inverter, a first switch, a second switch, a voltage level shifting circuit, a first ESD clamp and a second ESD clamp circuits. When the first power supply has been powered on and the second power supply is off, the first and second switches will remain off resulting from the power-off of the second power supply. Therefore, the second power source would not be affected by the first power supply because of passing through the ESD protection circuit.

Abstract: Protection and filtering functions are provided for external circuits by internal circuits that use controlled elements.

Abstract: A distance relay apparatus includes a directional relay element which performs computation to detect a fault, which occurs in the forward direction from an installing point of the relay apparatus, based on a voltage and a current which are received from an object to be protected, a zone-1 distance relay element which performs computation to detect a fault within a predetermined zone, a fault detecting relay element which performs computation to detect a fault within a zone that is narrower than that of the zone-1 distance relay element in terms of data time length which is shorter than that used for the computation of the zone-1 distance relay element, and a logic element which outputs a relay signal in accordance with a detecting operation of the zone-1 distance relay element, the fault detecting relay element, and the directional relay element.

Abstract: An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.

Abstract: A highly efficient line transient protection circuit is provided for high power loads that are designed to operate through a high line transient. The transient protection circuit for high power loads is provided with a primary leg circuit, a load circuit and a secondary circuit. The load circuit may be a switching regulator circuit, a load circuit containing an oscillator, a push-pull circuit, a boost converter circuit, a buck converter circuit or the like. The transient protection circuit is provided with a simple driver circuit to turn on a bypass n-channel MOSFET. It operates at a higher efficiency; I.E., conduction losses are minimized during normal input voltage conditions. Furthermore, the transient protection circuit provides a programmable voltage clamp which is implemented through selecting zener diode VR1. The transient protection may be used to protect medium to large current circuits from line transients.

Abstract: A protection circuit and method are provided for a floating power transfer device having one or more switches for controlling charging of a reservoir capacitor across which a load is applied when in use. The protection circuit includes a control circuit, a fault detection circuit and a precharge driver circuit. The control circuit at least partially controls switching of the at least one switch, while the fault detection circuit detects when a fault in the floating power transfer device or the load occurs and sends a fault detect signal to the control circuit in response thereto. The precharge driver circuit, which is enabled by the control circuit responsive to receipt of the fault detect signal, attempts to precharge the reservoir capacitor to a voltage level sufficient for switching of the one or more switches to proceed without damaging the switches.

Abstract: An electrical protection device is provided. The device can be removably attached to or mounted inside of a power source, such as a vehicle, e.g., automobile, battery and can employ a replaceable fuse element. The device includes an overcurrent protection element, such as a fuse element, and provides any one or more of the following types of electrical protection: (i) overcurrent protection; (ii) accident or catastrophic event power cutout protection; and (iii) load dump protection. The system is configurable to protect certain vehicle electrical components from an overcurrent and allow others to operate independent of the overcurrent protection. Systems and methods employing the protection device are also illustrated and discussed.

Abstract: MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.

Abstract: Method and apparatus for providing thermal protection for actuators used in haptic feedback interface devices. An average energy in the actuator over a predetermined period of time is determined, and the maximum allowable current level in the actuator is reduced if the average energy is determined to exceed a predetermined warning energy level. The maximum allowable current level can be reduced to a sustainable current level if the average energy reaches a maximum energy level allowed, and the maximum allowable current level in the actuator can be raised if the average energy is determined to be below the predetermined warning energy level. Preferably, the maximum allowable current level is reduced smoothly as a ramp function.

Abstract: In a portable data erasing device, to prevent data leaks from magnetic disk devices to be disposed, data is erased by a simple operation. The data erasing device using a magnetic field generated by permanent magnets to erase data comprises a sliding tray, a main body and a swinging tray. The sliding tray is movable into and out from the main body, two permanent magnets, adjacently arranged so that the north and south poles thereof have mutually attracting polarities, are attached to the front end of the sliding tray. One end of the swinging tray is fixed to the upper surface of the main body by a shaft, so that a magnetic disk device can be mounted and swung on top of the main body. While the sliding tray is extracted stepwise from the main body, the magnetic disk device can be swung, and data on the magnetic disks erased.

Abstract: A circuit for protecting a solenoid and/or receipt printer in an electronic device, such as a point-of-sale terminal, includes a resistance and a capacitance. The resistance is electrically coupled in parallel with the capacitance, and the parallel network of resistance and capacitance is coupled in series with the solenoid. An energizing signal is applied to the parallel network to energize the solenoid. A method of protecting a solenoid and/or receipt printer in the electronic device includes the steps of coupling a resistance electrically in parallel with a capacitance, coupling the parallel network electrically in series with the solenoid, and applying an energizing signal to the parallel network to energize the solenoid. The capacitance preferably includes two polarized electrolytic capacitors electrically coupled in a back-to-back series configuration with common polarities connected to each other.

Abstract: The invention relates to a device for protecting a battery from electrostatic charging. In particular, the invention is directed to an electrically conductive covering for a vehicle battery having a plastic casing. The type of plastics typically used in casings for vehicle batteries have a tendency to develop electrostatic charges. The accumulation of such charges can result in flash overs that can damage the battery and, in certain circumstances, can result in explosions. The covering may be a film having a surface resistance of <1·109 ohms that is connected to one of the terminals of the battery, thus draining the electrostatic charges that might otherwise build up. The covering may be provided with various features, including ribbing that preserves the structural integrity of the covering as well as different structures to hold down the covering on the battery. The covering is designed so that it can be customized to fit various battery types and sizes and is also reusable.

Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.

Abstract: An electric double layer capacitor has a pair of activated carbon electrodes and an organic solution in which an electrolyte is dissolved in an organic solvent. An electrolyte solution is also provided. In the electric double layer capacitor, at least one of cycloalkane, cycloalkene, or derivatives thereof is contained in at least one of the activated carbon and the organic electrolyte solution. The organic solvent contains a main solvent and an additive solvent. The main solvent contains propylenecarbonate in a range of from 99.9 to 70 wt %, and at least one of ethylenecarbonate and dimethylcarbonate in a range of from 0.1 to 30 wt %, and the additive solvent contains cycloalkane in a range of from 5 to 30 wt % to the total amount of the organic solvent.

Abstract: A surface mount energy storage device in the form of a supercapacitor (1) includes a generally rectangular folded prismatic housing (2) and two energy storage elements (not shown) that are sealingly contained within the housing (2) and which are connected in series. A mount, in the form of an integrally formed tinned metal frame (3), extends about and captively retains housing (2) in the folded configuration shown. Two terminals, in the form of elongate contacts (4, 5) extend from the energy storage elements and terminate outside housing (2) for allowing external electrical connection to the elements.

Abstract: A solid electrolytic capacitor having an anode of valve metals or of an alloy of which main component is valve metals; a dielectric layer formed by anodizing said anode; an electrolyte layer formed on said dielectric layer; and a cathode formed on said electrolyte layer; wherein said cathode has a silver layer using silver and sulfur and/or sulfur compound is contained in said silver layer.

Abstract: In this solid electrolytic capacitor, a plate-shaped anode having a porous sintered body is formed covering one part of an anode lead. A dielectric layer is formed covering the anode. An electrolyte layer of tantalum carbide is formed covering the dielectric layer. A cathode is formed covering the electrolyte layer. A conductive adhesive layer is formed on the upper surface of the cathode, and the cathode and a cathode terminal are connected by the conductive adhesive layer. An anode terminal is connected by welding the anode terminal on the anode lead projecting from the anode. Further, a mold outer resin is formed around the second conductive layer, the cathode terminal and the anode terminal.

Abstract: A solid electrolytic capacitor includes: a capacitor element including an anode made of a valve metal having an oxide film formed on a surface thereof, a cathode provided with a valve metal, and a separator provided between the anode and the cathode, the anode and the cathode and the separator being wound around together; a solid electrolyte interposed between the anode and the cathode; an anode lead tab having an oxide film formed on a surface thereof and being fixed to the anode; and a cathode lead tab fixed to the cathode. The oxide film of the anode lead tab has a portion the thickness of which is equal to or greater than 75% but less than 100% of the thickness of the oxide film of the anode.

Abstract: A computer system includes an LCD display part provided with a main housing mounting part in a rear thereof, and a main housing to accommodate a main board and detachably combined with the main housing mounting part of the LCD display part. Different sizes of the LCD display parts are selectively combined with the main housing to be replaced. Thus, the present invention provides a computer system in which different sizes of LCD display parts are replaceable.

Abstract: A laptop computer stand for a cab for an over-the-road vehicle wherein the cab is provided with a passenger seat, comprising a pair of longitudinally extending horizontal arms having forward ends and rear ends, one horizontal arm being attached to an inboard side of the seat and the other horizontal arm being attached to an outboard side of the seat, a curved arm having a horizontal portion extending across the forward ends of the two horizontal arms and being connected thereto, a vertical arm having an upper end and a lower end, the curved arm also having a vertical portion at an inboard end thereof connecting with the lower end of the vertical arm, a diagonal arm connected to and extending from the vertical arm to the rear end of the inboard arm and being connected thereto, a horizontal rectangular bed for receiving and supporting a laptop computer thereon, means connecting the bed to the upper end of the vertical arm so as to support the laptop computer over the seat.

Abstract: A display device includes a display unit having a front surface for display, a rear surface formed with a vertical row of spaced-apart positioning hole units, and a bottom side. A supporting unit includes a first supporting rod that is connected pivotally to the rear surface of the display unit, that is disposed adjacent to the bottom side, and that is adapted to abut against a supporting surface, and a second supporting rod connected pivotally to the first supporting rod and having a free end formed with a positioning stub that engages a selected one of the positioning hole units in the rear surface of the display unit so that an acute angle is formed between the first and second supporting rods, thereby supporting the display unit on the supporting surface.

Abstract: A memory card drive is provided which can record a large amount of digital information. A plurality of memory card slots is provided in a memory card drive body having a memory interface. A plurality of memory cards is detachably accommodated in the memory card slots. Digital information is recorded into and played back from the memory cards through the memory interface.

Abstract: The present invention relates to a positioning clamp for CD-ROM drives and diskette drives, characterized in that no tools are required, but only clamps located at the periphery of a frame are needed to easily and rapidly position the CD-ROM drive and the diskette drive inside a CD-ROM slot and a diskette drive slot formed between a computer case and a computer frame.

Abstract: A computer system is described of the kind having a frame and a plurality of server unit subassemblies that are insertable into the frame. Each server unit subassembly has a chassis component which engages with a frame component on the frame. Heat can transfer from the chassis component to the frame component, but the server unit subassembly can still be moved out of the frame. In one embodiment, an air duct is located over a plurality of the frame components. Heat transfers from the frame components to air flowing through the duct. A modified capillary pumped loop is used to transfer heat from a processor of the server unit subassembly to thermal components on the frame.

Abstract: The described embodiments relate to devices and cooling systems for same. One exemplary device includes a housing and at least one fan unit configured to move air through the housing. The device also includes a fluid channel comprising an impeller for moving fluid contained in the fluid channel, wherein the impeller is configured to be driven, at least in part, by air moving through the housing.

Abstract: A ductwork assembly can be used with an electronic device wherein the electronic device includes a fan and the ductwork assembly is configured to receive a heat transfer fluid from the fan. A disperser lies within the ductwork assembly and is attached thereto in order to affect at least a portion of a flow of the heat transfer fluid. The ductwork assembly may also include a first channel and the first channel is characterized by a first average fluid velocity that is a highest average fluid velocity of all channels within the ductwork assembly. The ductwork assembly may include a second channel that is characterized by a second average fluid velocity that is a lowest average fluid velocity of all channels within the ductwork assembly. The second averaged fluid velocity may be no less than 90% of the first averaged fluid velocity.

Abstract: A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat generating electronic device. The cooling apparatus includes a plurality of thermally conductive fins coupled to and projecting away from a surface to be cooled. The fins facilitate transfer of heat from the surface to be cooled. The apparatus further includes an integrated manifold having a plurality of inlet orifices for injecting coolant onto the surface to be cooled, and a plurality of outlet openings for exhausting coolant after impinging on the surface to be cooled. The inlet orifices and the outlet openings are interspersed in a common surface of the integrated manifold. Further, the integrated manifold and the surface to be cooled are disposed with the common surface of the manifold and the surface to be cooled in spaced, opposing relation, and with the plurality of thermally conductive fins disposed therebetween.

Abstract: A circuit configuration member has a space capable of storing a resin in a liquid state is formed on the adhering face and on an inner side of the case main body. The adhering face of the heat radiating member and the circuit configuration member are adhered by an adhering member at inside of the space by integrally molding the case main body arranged to surround the circuit configuration member and the heat radiating member.

Abstract: A heat dissipation device includes a retention frame (60), a heat sink (40) and a pair of wire clips (20). The retention frame is mounted on a PCB (120) having an electronic component (140) thereon. The heat sink is surrounded in the retention frame. The heat sink includes a base (42) attached on the electronic component and a plurality of fins (44) extending from the base. The base defines holes (46) at opposite sides thereof along a length direction of the fins. Receiving spaces (48) are defined in the heat sink above the holes respectively. The clips respectively include resilient arms (26) received in the receiving spaces and pins (28) extending from the arms. The pins are received in the holes. A pair of latching portions (24) depends from each of the clips and are engaged with the retention frame, to thereby secure the heat sink to the electronic component.

Abstract: A heat sink surface mounts to a printed circuit board in direct separation, thermal and physical, from components on the board. The heat sink cools the components by conducting heat from the components through the printed circuit board to the heat sink.

Abstract: A method for forming a medium is provided. In accordance with the method a base layer is provided. A material layer is formed on the base layer. The material layer has void. A transponder having a memory is positioned in the void. A medium is also provided. The medium has a base layer and a material layer having a void. A transponder having a memory is positioned in the void.

Abstract: An extended memory card capable of coupling to a reduced size memory card and having an electrical connection to a card reader is disclosed. The extended memory card comprises a first flash memory and a first client controller, where the card reader accesses to the first flash memory by controlling the operation of the first client controller. The reduced size memory card further comprises a second flash memory and a second client controller, where a host controller accesses to the second flash memory by controlling the operation of the second client controller. The extended memory card coupled to the reduced size memory card has the same size as an MMC card. The reduced size memory card has the same size as the RS-MMC card.

Abstract: A card connector includes a card-mounting seat formed with an insertion groove that is defined by opposite end walls, opposite side walls and a bottom wall. Each end wall has two opposite upright extension wall portions defining a receiving groove therebetween. Two anchoring blocks are connected pivotally and respectively to the extension wall portions of the end walls of the card-mounting seat. When an insertion side of an electronic card is inserted into the insertion groove in the card-mounting seat, conductive members, which are mounted in the card-mounting seat, contact electrically and respectively conductive terminals of the electronic card, and a protrusion of one of the anchoring blocks engages a notch in a lateral side of the electronic card while the electronic card is anchored between the anchoring blocks.

Abstract: A heat sink comprises a heat sink base and a row of heat sink extensions that are attached to one side of the heat sink base. An interleaved heat sink structure includes a first row and a second row of heat sink extensions. The first row and the second row of heat sink extensions are coupled respectively to a first and a second heat sink bases. The first and the second heat sink bases are thermally coupled to a first plurality of memory packages and a second plurality of memory packages, respectively. The first row of heat sink extensions is parallel to and at least partially interleaved with the second row of heat sink extensions. A memory heat dissipation control system and a method for assembly a memory part that includes a DIME and two heat sinks are also described.

Abstract: A twin-substrate wireless electronic module includes a main substrate, a plurality of integrated circuit chips, a frame substrate, a filter, and a shield member. The main substrate has a first surface and a second surface, and is formed with a notch that extends from the first surface through the second surface. The integrated circuit chips are surface-mounted on the first and second surfaces of the main substrate. One of the integrated circuit chips disposed on the first surface is a transceiver integrated circuit chip. The frame substrate has a first frame surface and a second frame surface. The first frame surface has a filter-mounting area aligned with the notch. The filter is surface-mounted on the filter-mounting area and is accommodated in the notch. A method for manufacturing the twin-substrate wireless electronic module is also disclosed.

Abstract: An assembled structure. A first substrate having a base surface is connected to a second substrate by at least one metallic clamping device. The clamping device, vertically disposed on the second substrate, comprises two parts: a first half and a second half having a supporting surface. The first half comprises a main unit and a plurality of spaced arm units disposed on the main unit, and each arm unit comprises a first part extending from the main unit and a second part extending from the first part. When the base surface of the first substrate contacts the supporting surface of the second half, at least one of the second parts of the arm units presses the first substrate on the second half, so that the first substrate is positioned by and electrically connected to the clamping device.

Abstract: Various techniques directed to the digital control of a switching regulator are disclosed. In one aspect, a method for regulating an output level at a power converter output includes receiving a feedback signal representative of the output level at the power converter output. In response to a state of the power converter, at least one of the feedback signal or a threshold level is adjusted. A feedback state signal is generated having a first feedback state that represents that the output level is above the threshold level and a second feedback state that represents that the output level is below the threshold level. A duty cycle signal that cycles is generated. In response to a control signal, energy from a power converter input is enabled or disabled to flow to the power converter output. The control signal is responsive to the duty cycle signal and to a change between the first and second feedback states. The control signal is also responsive to a change between the first and second feedback states.

Abstract: A flyback converter is comprised of a primary side and a secondary side. The primary side includes a primary winding and a switch both connected in series. The secondary side includes a secondary winding, a tertiary winding, a first resistor, a capacitor, a second resistor, and an MOSFET (metal-oxide-semiconductor field-effect transistor). The first resistor, the capacitor, and the second resistor are connected in series and together connected in parallel with the tertiary winding. The MOSFET is connected in parallel with the first resistor at its gate and source. Accordingly, when the switch is turned on/off, the power energy provided at the primary side can be transferred to the secondary side in a flyback manner.

Abstract: A polygon connected autotransformer in conjunction with zero sequence blocking inductor(s) enables multipulse AC to DC converters to use lower kVA parts rating by using appropriate phase-shifted voltage sets in conjunction with inductors that extend the conduction period and reduce rms current. Also, lower harmonic voltages in the transformer facilitate use of lower performance magnetic steel. Designs for 12, 18, and 24-pulse use the same conceptual approach. Very efficient high power ratings are feasible. Means are given to limit the maximum no-load DC output voltage. A technique is disclosed that reduces the size of polygon transformers supplying loads with substantial third harmonic.

Abstract: A new type of the passive non-dissipative snubber with a single saturable reactor improves the performance of the boost converter used as a front-end active Power Factor Correction (PFC) in two critical areas: excess voltage stresses caused by high voltage spikes on input high voltage switching transistor of the boost converter is eliminated and EMI noise is much reduced. The high voltage spike energy instead of being dissipated as in a dissipative snubber circuits is recovered resulting in increased conversion efficiency. High voltage spike elimination also allows use of lower voltage rated devices with lower ON resistance, hence further increasing the efficiency of the PFC boost converter.

Abstract: A charge pump circuit is provided for generating a voltage (1+1/n) times as high as a supply voltage. The charge pump circuit eliminates the need for diodes for preventing a current from flowing back from a high potential side of capacitors to prevent a reduction in the voltage due to a forward voltage, and reduces a reactive current and latch-up when the charge pump circuit is integrated into a single IC chip. The charge pump circuit includes a fourth switching element having a substrate gate connected to a drain for preventing a current from flowing back to an input terminal from a high potential side of fly back capacitors connected in series, and a second switching element having a substrate gate connected to a drain for preventing a current from flowing back from a high potential side of a catch-up capacitor to the fly back capacitors connected in series.

Abstract: A multiplicity of synchronized inverters for driving a multiplicity of loads such as CCFLs that require high ac voltages are arranged in close proximity of the respective loads and controlled in phase. A frequency determination capacitor and a frequency determination resistor are connected to one of the inverters to generate a triangular wave signal and a clock signal. The triangular wave signal and clock signal thus generated are supplied to other inverters to synchronize all the loads so that they can be controlled in phase. The resistance of the frequency determination resistor is set to a substantially small magnitude at the time of startup to increase the frequency of the triangular wave signal, thereby enabling quick startup of the loads.

Abstract: The invention relates to an integrated circuit configuration proposed for the actuation of power switches disposed in bridge connection and an associated method. The primary side of this circuit configuration is herein connected with the secondary side, which actuates the TOP switch, via a level shifter. The circuit configuration comprises furthermore between the primary side and a secondary side a diode for error status conveyance from the secondary side to the primary side. The anode-side terminal of the diode is connected with the primary side and its cathode-side terminal with the secondary side of the driver circuit. The primary side applies a voltage to this diode. In the presence of error-free operation the secondary side applies level “high” (Vd) to the cathode of the diode and, in the presence of faulty operation, level “low” (Vg).

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. Each word line is formed by connecting commonly the control gates in a same row. The row decoder selects any one of the word lines. The first metal wiring layers are provided for the word lines in a one-to-one correspondence. The first metal wiring layers are electrically connected to the corresponding ones of the word lines and transmit a first row select signal for the row decoder to select one of the word lines. The metal wiring lines are formed at a plurality of levels. The first metal wiring layers are made of the metal wiring lines located at the level of the lowest layer.

Abstract: A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to a respective local bitline, and, wherein one of the source/drain regions of a neighboring memory cell is connected to one of the local bitlines, the other source/drain region of the neighboring memory cell being connected to another local bitline, comprising the steps of connecting the local bitline that connects the source/drain region of the memory cell and the source/drain region of the neighboring memory cell to a first global bitline, connecting the local bitline that connects the other source/drain region of the memory cell to a second global bitline, connecting the local bitline that connects the other source/drain region of the neighboring memory cell to one of a plurality of local power rails, applying a gate potential to the gate of the memory cell, applying a potential to the first global bitline and applying another potential to the secon

Abstract: An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method.

Abstract: A semiconductor device includes a first DRAM section formed on a semiconductor substrate and composed of a plurality of first memory cells and a second DRAM section formed on the semiconductor substrate and composed of a plurality of second memory cells. The operating speed of the first DRAM section is higher than that of the second DRAM section, and the capacitance of each said first memory cell is larger than that of each said second memory cell.