Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.

Abstract: An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature.

Abstract: In order to provide a semiconductor device which makes it possible to mount a semiconductor element on the substrate of the semiconductor device main body at the correct position with a higher degree of accuracy, a semiconductor element 2 is mounted at a circuit forming surface of a semiconductor substrate 1 at the periphery of which pad electrodes 5 are provided and a specific area in the semiconductor device containing the semiconductor element 2 is sealed with resin. At the circuit forming surface of the semiconductor substrate 1, reference lines 3 are formed in correspondence to the positions of at least three corners of the semiconductor element 2 to be mounted.

Abstract: A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the electronic component; coupling the first surface of the electronic component to a first surface of a lower dielectric strip; coupling the second surface of the electronic component to a first surface of an upper dielectric strip; forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component; forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component; filling the lower and upper via apertures with an electrically conductive material to form lower and upper vias electrically coupled to the first and second selected bond pads of the pl

Abstract: After a first adhesive layer having high adhesion to a supporting base is locally formed, a second adhesive layer having low adhesion to the supporting base is formed all over the supporting base so as to cover the first adhesive layer. When a wiring structure is separated, a predetermined portion of the wiring structure where the first adhesive layer is formed is cut to thereby separate the integrated wiring structure and second adhesive layer from the first adhesive layer.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulating, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.

Abstract: It is an object of the present invention to provide a method for manufacturing a crystalline semiconductor film comprising the steps of crystallizing with the use of the metal element for promoting the crystallization to control the orientation and irradiating the laser once to form a crystalline semiconductor film having a small crystal grain arranged in a grid pattern at a regular interval. In the present invention made in view of the above object, a ridge forms a grid pattern on a surface of the crystalline semiconductor film in such a way that a crystalline semiconductor film is formed by adding the metal element for promoting the crystallization to the amorphous semiconductor film and the pulsed laser whose polarization direction is controlled is irradiated thereto. As the means for controlling the polarization direction, a half-wave plate or a mirror is used.

Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

Abstract: The present invention provides a method for manufacturing a display device having a TFT that can be operated at high speed while using a small number of photomasks and improving the utilization efficiency of materials, where the threshold value is difficult to be varied. In the invention, a catalytic element is applied to an amorphous semiconductor film and the amorphous semiconductor film is heated to form a crystalline semiconductor film. After removing the catalytic element from the crystalline semiconductor film, a top-gate type thin film transistor with a planar structure is manufactured. Moreover, by using the droplet discharging method where an element of a display device is formed selectively, the process can be simplified, and loss of materials can be reduced.

Abstract: A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.

Abstract: This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.

Abstract: A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N?-type drain junction region on the N+-type drain junction region; a P?-type body region provided in a trench region of the N?-type drain junction region; a plurality of gate patterns including a gate insulation layer and a gate conductive layer in other trench regions bordered by the P?-type body region and the N?-type drain junction region; a plurality of source regions contacted to a source electrode on the P?-type body region; and a plurality of N+-type drain regions contacted to the N?-type drain junction region and individual drain electrodes.

Abstract: A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidewall spacer on a gate, selectively growing an epitaxial layer in a lateral direction relative to the sidewall spacer and the gate, and forming a contact on the epitaxial layer.

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Abstract: A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.

Abstract: Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.

Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.

Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract: The present invention discloses a fabrication method and structure of spiral RF inductor on porous glass substrate. Thick porous silicon layer is natively formed on a silicon wafer by anodic etching the silicon material to a high degree of porosity. The porous silicon is than thermally oxidized at high temperature converting it into porous glass texture. The oxidation rate can be rapid due to open pore character of the etched structure, which allows oxidizing agents to penetrate deeply into the wafer. If the porosity is large enough, the pores will not be sealed by the expansion of oxide during the oxidation, which results a porous structure of glass-and-air mixture of low relative dielectric constant slightly over a value of 2. The final holes appear on the wafer surface can be sealed by CVD coating step, if necessary. This ultra-flat, low-k, silicon-based substrate allows RF spiral inductor to be made on its surface with excellently low loss, or high Q value.

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

Abstract: In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric.

Abstract: A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing a counter wafer; bonding the germanium thin film to a counter wafer to form a bonded structure; annealing the bonded structure at a temperature of at least 375° C. to facilitate splitting of the bonded wafer; splitting the bonded structure to expose the germanium thin film; removing any remaining silicon from the germanium thin film surface along with a portion of the germanium thin film defect zone; and incorporating the low-defect germanium thin film into the desired end-product device.

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 ? thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge.

Abstract: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.

Abstract: The present invention achieves a shallow junction of a source and a drain, and provides a doping method which makes device properties reproducible and a semiconductor device fabricated using the method. In the present invention, doping for the semiconductor is conducted by attaching a molecular species with a higher electron affinity or lower ionization energy out of fullerene derivatives or metallocenes to the semiconductor surface to induce charge transfer from the molecule to the semiconductor.

Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium silicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.

Abstract: A silicon carbide-based device contact and contact fabrication method employ a layer of poly-silicon on a SiC substrate, with the contact's metal layer deposited on top of the poly-silicon. Both Schottky and ohmic contacts can be formed. The poly-silicon layer can be continuous or patterned, and can be undoped or doped to be n-type or p-type. The present contact and method provide excellent contact adhesion, and can be employed with a number of different device types, to provide electrical contacts for Schottky diodes, pn diodes, and transistors, for example.

Abstract: The invention provides a substrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite structure, a method for manufacturing a substrate for an electronic device, and an electronic device provided with such a substrate for an electronic device. A substrate for an electronic device includes a Si substrate, a buffer layer which is formed by epitaxial growth on the Si substrate and which contains a metal oxide having a NaCl structure, and a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation on the buffer layer and which contains a metal oxide having a perovskite structure. The Si substrate is preferably a (100) substrate or a (110) substrate from which a natural oxidation film is not removed.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to terminals that are adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals, respectively.

Abstract: The present invention generally relates to methods used for fabricating integrated circuits (“ICs”), using Ruthenium (“Ru”) and its oxides and/or Iridium (“Ir”) and its oxides as the diffusion barrier to contain and control copper (“Cu”) interconnects. The invention also covers ICs incorporating such materials in the diffusion barrier to contain and control the Cu interconnects. The present invention advantageously provides better integration and fabrication of advanced IC chips with sub-micron features.

Abstract: A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.

Abstract: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

Abstract: Processes are disclosed for producing electronic interconnect devices, particularly semi-conductor wafers, with metal interconnect traces thereon wherein the surface of said device has improved planarity. Said planarity is achieved initially through the use of pulse reverse electrolytic plating techniques. Planarity is further enhanced by cathodically protecting the metal interconnect traces during the polishing operation. Cathodic protection is achieved by overtly applying a cathodic charge to said traces and/or by contacting said traces, during polishing, with a metal that is capable of sacrificial corrosion when in contact with the metal of the interconnect traces.

Abstract: The invention provides a process for forming a planar copper structure on a wafer surface in a first module and a second module of a system. During the process, a copper layer is formed on the wafer surface by utilizing an electrochemical deposition process in the first module. After the deposition, the wafer is moved to the second module of the system and an electrochemical mechanical polishing process is applied to planarize the copper layer to a predetermined thickness. The first and second modules can be positioned in a cluster tool. The wafer is subsequently processed by selective copper CMP and selective barrier layer CMP, which are conducted in another cluster tool.

Abstract: A method has been disclosed that allows the selective deposition of the metal for double damascene silicon wafer processing. This selective deposition allows the metal to be deposited only in the via holes, contact holes, channels or where ever the deposition is targeted to be deposited on the wafer where it is needed. This method allows double damascene wafers to be processed with out the necessity of polishing back the whole surface of the wafer to remove metal from most of the wafer surface, as is currently the practice.

Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

Abstract: The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, a finished dimension of a resist mask, an etching technique and the like. An insulating film covering a gate electrode is formed, and a source region and a drain region are exposed, a conductive film is formed thereover, a resist having a different film thickness is formed by applying the resist over the conductive film, the entire surface of the resist is exposed to light and developed, or the entire surface of the resist is etched to form a resist mask, and the conductive film is etched by using the resist mask to form a source and drain electrode.

Abstract: One embodiment of the invention is a method for void-free filling with a metal or an alloy inside openings by electrochemical deposition (ECD), said method including steps of: (a) providing a substrate with at least one opening and a field surrounding the at least one opening, said at least one opening having a bottom and sidewalls surfaces, said substrate including an electrically conductive surface, said conductive surface including at least the bottom surface of the at least one opening; (b) immersing the substrate in an electrolyte contained in an electrochemical deposition (ECD) cell, the ECD cell including at least one anode and a cathode, wherein the cathode including at least a portion of the conductive surface of the substrate, and wherein the electrolyte includes plating metallic ions and at least one inhibitor additive, said metallic ions and at least one inhibitor additive having concentrations; (c) providing agitation of the electrolyte across the surface of the substrate immersed in the electrol

Abstract: One embodiment of a method of making an electronic device includes forming on a substrate surface a first layer having a peak-valley-peak profile, and forming a second layer on the first layer by use of a target positioned along a line-of-sight that excludes a floor of the valley such that the second layer is not formed on the floor of said peak-valley-peak profile.

Abstract: Methods for fabricating a copper interconnect are disclosed. A disclosed method comprises: employing a damascene process to form a first trench in a first insulating layer; depositing a first barrier layer and a first copper layer on the first insulating layer; forming a bottom copper interconnect by planarizing the first copper layer; depositing and planarizing a second barrier layer; depositing a second insulating layer; forming a via hole in the second insulating layer; employing a damascene process to form a second trench in the second insulating layer; and forming a via and an upper copper interconnect by depositing a third barrier layer and a second copper layer on the second insulating layer.

Abstract: The invention relates to chemical mechanical polishing of substrates using an abrasive and a fluid composition, wherein certain organosulfonic acid compounds are used as oxidizers, and particularly relates to a method of polishing substrates comprising copper, tungsten, titanium, and/or polysilicon using a chemical-mechanical polishing system comprising organosulfonic acids having an electrochemical oxidation potential greater than 0.2V as an oxidizer.

Abstract: The invention provides a method of chemically-mechanically polishing a substrate comprising tungsten through use of a composition comprising a tungsten etchant, an inhibitor of tungsten etching, and water, wherein the inhibitor of tungsten polishing is a polymer, copolymer, or polymer blend comprising at least one repeating group comprising at least one nitrogen-containing heterocyclic ring or a tertiary or quaternary nitrogen atom. The invention further provides a chemical-mechanical polishing composition particularly useful in polishing tungsten-containing substrates.

Abstract: A conductive pattern, made of a transparent conductive oxide, such as ITO including electrodes (2) and conductive paths (4) is formed on one face of a transparent substrate (3) made of sapphire or toughened glass, then coated with a first layer (5) of a transparent dielectric with a low refractive index, such as MgF2 or LiF2, and then a second layer (7) of another transparent dielectric having a higher refractive index than the first, such as Al2O3, Ta2O5 or DLC.

Abstract: The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

Abstract: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.