Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A compensating circuit for calibrating reference voltage, which is coupled to an operation amplifier having an input end and an output end within a reference voltage driving circuit, is provided in the present invention. The compensating circuit comprises a first capacitor, a second capacitor, and a first switch. The first capacitor is utilized for storing the potential with respect to the reference voltage. The second capacitor is coupled to the operation amplifier for storing the potential difference between the input end and the output end of the operation amplifier. The first switch is electrically connecting to the first capacitor and the second capacitor. When turning on the first switch, the potentials stored in the first capacitor and the second capacitor are combined and input to the operation amplifier to have an output voltage level substantially identical to the reference voltage.

Abstract: The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current is inputted to perform the set operation. A predetermined potential can be obtained rapidly as the precharge operation is performed before the set operation. The predetermined potential is approximately equal to a potential after completing the set operation. Therefore, the set operation can be rapidly performed and a write operation of a signal current can be rapidly performed. By using two transistors, a gate width W can be long or a gate length L can be short in the precharge operation or the gate width W can be short and the gate length L can be long in the set operation.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: A method for adjusting a clock and an electronic device with clock adjusting function are provided. In the method of adjusting the clock, the electronics device is driven with a first clock when the electronic device is during the reset-inactive state. Then, the electronic device is driven with a second clock when the electronic device receives a reset signal. Wherein, the cycle of the second clock is larger than that of the first clock.

Abstract: A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back to the phase detector. During this time, a signal replicating the adjusted signal is temporarily fed to the phase detector until the adjusted signal reaches the phase detector.

Abstract: A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.

Abstract: A phase synchronization circuit comprises: a measurement delay line which includes a plurality of delay elements having different delay times and to which a first clock signal is inputted; a phase comparator line which includes a plurality of phase comparators in accordance with the measurement delay line and to which a signal from the measurement delay line and a second clock signal are inputted so as to measure a transition timing difference between the first clock signal and the second clock signal; and a generation delay line which includes a plurality of delay elements having different delay times in accordance with the measurement delay line and to which a signal from the phase comparator line and a third clock signal are inputted. The delay time of the respective delay elements is fixed.

Abstract: A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded number of electrical pulses from the oscillator. The prescaler is operably connected to a compensator module for adjusting the number loaded into the prescaler. By adjusting the number that is loaded into the prescaler, the timing may be advanced or retarded to more accurately synchronize the clock pulses with a reference time source. The compensator module is controlled by a counter-based trigger module configured to trigger the compensator module to load a value into the prescaler. Finally, a time-base logic module is configured to calculate the drift of the downhole clock by comparing the time of the downhole clock with a reference time source.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating element operates according to a first control clock and generates a first output clock of the set of multi-phase clocks according to an input clock. The second gating element operates according to a second control clock and generates a second output clock of the set of multi-phase clocks according to the first output clock. The second control clock is an inverted signal of the first control clock.

Abstract: A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.

Abstract: The bootstrapping circuit capable of sampling inputs beyond supply voltage includes: a bootstrapped switch MN20 coupled between an input node and an output node; a first transistor MP13 having a first end coupled to a control node of the bootstrapped switch MN20; a clock bootstrapped capacitor C13 having a first end coupled to a second end of the first transistor MP13; a second transistor MN27 coupled between the first end of the first transistor MP13 and a supply node, and having a control node coupled to a first clock signal node PHI; a third transistor MN26 coupled between the second end of the first transistor MP13 and the supply node; a charge pump having a first output coupled to a control node of the third transistor MN26; a level shifter having a first output coupled to a second end of the clock bootstrapped capacitor C13; a fourth transistor MN25 coupled between the supply node and a control node of the first transistor MP13, and having a control node coupled to a second output of the charge pump; a

Abstract: A semiconductor device that includes a clock generator which generates a clock signal; a booster which boosts a supply voltage by using the clock signal to output the boosted voltage; a potential detector which detects an output potential of the booster to output a frequency changing signal depending on the output potential; and a frequency changer which is interposed between the clock generator and the booster to change the frequency of the clock signal from the clock generator to the booster on the basis of the frequency changing signal.

Abstract: A supply voltage bias circuit includes: an output circuit which comprises a first transistor having a terminal from which output voltage or output current is supplied, the output voltage and output current having values proportional to a supply voltage at a supply line; a second transistor forming a current mirror circuit together with the first transistor, the second transistor being connected to a first connection node; a third transistor connected to the first connection node; and a current source connected between the first connection node and the supply line. Drains of the second and third transistors or sources of the second and third transistors are commonly connected to the first connection node. The drains or sources of the second and third transistors which are not connected to the first connection node are grounded or earthed. The first connection node is connected to a gate of the third transistor and is functioning as an output terminal of the bias circuit.

Abstract: Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred to the drain of a transistor via the gate-to-source voltage drops of a pair of gate-coupled transistors.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: A system and method for compensating an amplifier apparatus for low frequency and/or DC components of an externally applied input signal as well as for any voltage offsets contributed by the amplifier circuitry. Band-limited servo feedback is applied to predetermined nodes in the forward gain path to null out unwanted signal components, leaving a residual signal that, when amplified, will be centered around ground, so that the full dynamic range of the amplifier system may be utilized. Consequently, the signal-to-noise ratio available at the output of the amplifier system will be maximized. The servo compensation may either operate in continuous time, or it may be held constant once a suitable level of compensation has been established, or it may be adjusted from time to time to accommodate slow variations of the average DC component of the input signal.

Abstract: An amplifier circuit for amplifying radio frequency signals includes a radio frequency power amplifier to receive an input radio frequency signal and to output an amplified radio frequency signal; one or more sensors coupled to the radio frequency power amplifier to provide a closed-loop feedback signal; and a power sensor coupled to the amplified radio frequency signal.

Abstract: The antenna amplifier for mobile FM radio reception includes a signal amplifier, a controllable adjusting element having a PIN diode for impedance adaptation, and a control amplifier for regulating the adjusting element. The antenna amplifier has a compensation for the temperature response occurring as a result of very great differences (summer/winter) in ambient temperature, the PIN diode connection point is optimized, and the control range is maximized.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: A class AB amplifier capable of easily controlling the amount of quiescent current and the amount of amplifier output current. The amplifier includes an input circuit that transform a voltage difference between input signals into a current; a current mirror including the (the Pull Up and Pull Down transistors of the) output circuit of the amplifier controls the quiescent current through the Pull Up and Pull Down transistors output circuit; and a control circuit in the current mirror (to which a first control voltage and a second control voltage are applied), adjusts the amount of quiescent current flowing through the output circuit in a first operating mode (by controlling a first bias current that is proportionate to the quiescent current in the current mirror), and controls the amount of the output current sourced or sinked (in response to the change in the voltages at the first and second output nodes of the input circuit) in a second operating mode.

Abstract: Differential amplifier embodiments are provided for amplifying input signals with enhanced gain and dynamic range. They include first and second amplifier stages and at least one common-mode feedback circuit that is arranged to mirror and adjust a tail current to control the common-mode level of a respective one of the stages. The stages are configured with cascode elements to obtain high impedances that enhance their signal gain and the common-mode feedback circuit is configured to controllably lower the output voltage of a current source that provides the tail current to thereby enhance the amplifier's dynamic range. The amplifier embodiments are particularly suited for use in applications where they must operate with reduced supply voltages and operate in alternating operational modes.

Abstract: A differential input operational amplifier has a voltage clamp differential transistor pair coupled to an input differential transistor pair of the operational amplifier. The voltage clamp differential transistor pair limits the output voltage of the operational amplifier by taking over control of the operational amplifier circuits from the input differential transistor pair as the output voltage approaches a clamp voltage value. A reference voltage may be used to set the output voltage at which the input differential transistor pair will be clamped by the voltage clamp differential transistor pair. Below the clamp voltage, operation of the input differential transistor pair will not be affected. At the clamp voltage the input differential transistor pair will no longer control the output of the differential amplifier, rather the voltage clamp differential transistor pair will control the maximum voltage output of the differential amplifier.

Abstract: Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.

Abstract: A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.

Abstract: A low noise amplifier (LNA) comprises a bias circuit having an output. A first transistor includes a control input that communicates with the bias circuit, a first terminal that generates a LNA output current and a second terminal. A device communicates with the second terminal of the first transistor, includes a variable resistor, and has a resistance that is modulated in response to an input signal to the LNA.

Abstract: A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.

Abstract: The invention is directed to a phase locked loop. The phase locked loop comprises a variable frequency divider for performing a fraction frequency division by switching a dividing value having an integer portion and a fraction portion; a memory for storing the fraction portion; and a data converter for adding the integer portion to the fraction portion from the memory based on a clock signal from the variable frequency divider to determine the dividing value to be supplied to the variable frequency divider.

Abstract: A variable capacitance circuit includes a first and a second capacitor. A switch having an associated first nonlinear capacitance, selectively couples the first and second capacitors. To compensate for the first nonlinear capacitance, a second nonlinear capacitance is coupled to the switch that has a capacitance value responsive to a change in voltage that moves in a direction of change opposite to a direction of change of the first nonlinear capacitance.

Abstract: A method provides a temperature controlled frequency source. The method reduces the effects of temperature variations on an operating frequency of the temperature controlled frequency source by temperature compensating the temperature controlled frequency source.

Abstract: In a function generating circuit which comprises a temperature sensor 1 for outputting an output current (Ilin) with a linear temperature characteristic or an output voltage (Vlin) with the linear temperature characteristic, a cubic function generating circuit 2 for receiving the output current (Ilin) or the output voltage (Vlin) of the temperature sensor 1 as an input and generating a cubic temperature characteristic voltage (Vcub), and a control data storing circuit 3 for recording control data to control the output characteristic of the cubic function generating circuit 2, an external control signal is applied to the temperature sensor 1 from an external control terminal 4 to cause the sensor to output variably the output current (Ilin) or the output voltage (Vlin) such that the temperature characteristic of the cubic function generating circuit 2 can be controlled at the ordinary temperature.

Abstract: A bi-crystal heterostructure includes a first, substantially uniaxial, crystal layer; a second, substantially uniaxial, crystal layer positioned adjacent to the first crystal layer, and wherein the first and second crystal layers have mutually opposite rotations of their respective principal cross-sectional axes of a degree sufficient to impart negative refractivity in the heterostructure; a conductive metal strip positioned between the crystal layers and having a principal longitudinal axis sufficiently aligned with an unrotated principal axis of each of the first and second crystal layers to permit unidirectional electromagnetic wave propagation in the conductive metal strip; and a lossy metal strip positioned between the crystal layers and having a principal axis positioned substantially parallel to the principal axis of the conductive metal strip.

Abstract: A two-port isolator includes a first center electrode and a second center electrode which are wound around a ferrite to which a direct-current magnetic field is applied from permanent magnets, and the ferrite is mounted on a circuit board having built-in matching circuit devices. The ferrite is preferably substantially rectangular-parallelepiped-shaped having first and second principal surfaces that are substantially parallel to each other, and the long-side length of the principal surfaces is about 1.5 to about 5 times the short-side length. The second center electrode is wound between one and four turns around the ferrite.

Abstract: A line converter includes ground conductors, a transmission-line conductor and a coupling-line conductor disposed on a dielectric substrate. A dielectric-filled waveguide includes a lower conductor plate, an upper conductor plate, a lower dielectric strip, and an upper dielectric strip, where the dielectric substrate is sandwiched between the lower conductor plate and the lower dielectric strip, and the upper conductor plate and the upper conductor strip, so that a conductor portion S that is part of the ground conductors of the dielectric substrate defines a shield area of the dielectric-filled waveguide. The coupling-line conductor is coupled to a standing wave generated by the shield area, at a position where the electric-field intensity of the standing wave is high. Subsequently, a plane circuit can be arranged so as to be substantially parallel to the direction in which an electromagnetic wave propagates through the three-dimensional waveguide.

Abstract: An impedance matching structure for a RF MEMS switch having at least one closeable RF contact in an RF line, the impedance matching structure comprising a protuberance in the RF line immediately adjacent the RF contact that forms one element of a capacitor, the other element of which is formed by the switch's ground plane.

Abstract: A circuit for a digitally operating linear-in-decibels attenuator circuit controlled using an analog control signal. The attenuator circuit includes a resistor ladder, digitally controlled switches, and a flash analog-to-digital converter. The resistive ladder includes resistances coupled in series between an input and output electrode. The resistive ladder also includes shunt resistances, each of which is coupled to a corresponding series resistance and to a corresponding digitally controlled switch that is controlled by a corresponding digital control signal. Each of the switches include a pole electrode coupled to a corresponding shunt resistance and to the input electrode, and a throw electrode coupled to the corresponding shunt resistance and to the common node for attenuating voltage from an input signal. The flash analog-to-digital converter is controlled by an analog control signal and outputs digital control signals in a thermometer code for controlling the digitally controlled switches.

Abstract: Multiple sensor signals are used to modulate an equal number of frequency-spaced carrier signals in a directional parametric upconverting amplifier. Basically, the carrier signals are separated in a cascaded or parallel configuration of narrow frequency passbands, which also modulate the carrier signals with low-frequency sensor signals. The modulated carrier signals are multiplexed and output over a single signal path, thereby reducing power dissipation. Preferably implemented in superconducting circuitry, the multiplexed amplifier facilitates multiplexing of as many as hundreds of sensor signals and achieves both amplification and upconverting with minimal dissipation of power.

Abstract: A high-frequency switch module, including a laminate constituted of dielectric layers having electrode patterns, the high-frequency switch module also including a high-frequency switch circuit for switching a transmitting circuit and a receiving circuit of transmitting/receiving systems, and a filter circuit connected to a receiving side of the high-frequency switch circuit.

Abstract: An air-gap type thin film bulk acoustic resonator (FBAR) and method for fabricating the same. Also disclosed are a filter and a duplexer employing the air-gap type FBAR. The air-gap type FBAR includes: a first substrate having a cavity part at a predetermined region on its upper surface; a dielectric film stacked on the upper part of the first substrate; a first air gap formed between the first substrate and the dielectric film; a stacked resonance part including a lower electrode/piezoelectric layer/upper electrode formed on the upper part of the dielectric film; a second substrate having a cavity part at a predetermined region on its lower surface and joined to the first substrate; and a second air gap formed between the stacked resonance part and the second substrate. A thin film of predetermined thickness made of a liquid crystal polymer (LCP) may be used as the dielectric film.

Abstract: A compact and high-performance RF duplexer and fabrication method thereof, the RF duplexer includes a first filter and a second filter suspended over the substrate connected in series and in parallel and having a plurality of resonators, for passing signals of different frequency bands. A plurality of inductors are connected in series with the parallel resonators of the first and second filters and formed on the substrate. A phase shifter is formed on the substrate for preventing a signal interference between the first and second filters, and a supporter supports the first and second filters and has a plurality of bumps at certain parts on the substrate to electrically connect terminals of the first and second filter with terminals of the substrate. Accordingly, the size of the duplexer is reduced by forming the tuning inductors around the bumps of the PCB.

Abstract: An air-gap type thin-film bulk acoustic resonator. The air-gap type thin-film bulk acoustic resonator has a substrate having a cavity formed on a predetermined portion of an upper surface thereof; a resonance part having a structure of a first electrode, a piezoelectric substance, and a second electrode deposited in order and formed over the upper side of the cavity; and at least one via hole penetrating a lower surface of the substrate and connecting to the cavity.

Abstract: A method for manufacturing a surface acoustic wave element including: forming a conductive film on a surface of a piezoelectric substrate; forming a photoresist film on the conductive film; printing a pattern by exposing and developing the pattern, which is originally provided on a photomask, onto the photoresist film by reduced projection; forming an electrode of a surface acoustic wave element by etching the conductive film using the patterned photoresist film as a mask; measuring a resonant frequency of the surface acoustic wave element formed on the piezoelectric substrate; calculating an anodic oxidation voltage based on an amount of anodic oxidation of the electrode that is calculated in advance from the measured resonant frequency and a preset target resonant frequency; and performing anodic oxidation based on the anodic oxidation voltage calculated in the voltage calculation step and finishing anodic oxidation after detecting an end-point of oxidation reaction of the electrode.

Abstract: An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.

Abstract: An RF cavity resonator that includes: a resonator chamber for containing an RF field; an RF coupling element coupled to the resonator chamber for introducing the RF field into and extracting the RF field from the resonator chamber; a tuning assembly for causing the RF field to resonate at a desired frequency, wherein at least a portion of the tuning assembly is coupled within the resonator chamber; and a heat transport element included in the tuning assembly for transporting heat from the RF cavity resonator, the heat transport element comprising a phase change material, a housing for enclosing the phase change material, means for circulating the phase change material within the housing, and an electrically conductive surface for isolating the phase change material from the RF field, wherein the phase change material undergoes a phase change during circulation within the housing.

Abstract: Apparatus for a micro-electro-mechanical switch that provides for latching switching action. The switch has a cantilever arm disposed on a substrate that can be moved in orthogonal directions for latching and unlatching. To latch the switch, the cantilever arm is moved back by a comb-drive actuator and then pulled down by electrodes disposed on the substrate and the cantilever arm. The comb-drive actuator switch is then released and the cantilever arm moves forward to be captured by a dove-tail structure on the substrate. When the voltage to the electrodes on the substrate and the cantilever arm is removed, the cantilever arm is held in place by the dove-tail structure. The switch is unlatched by actuating the comb-drive actuator to move the cantilever arm away from the dove-tail structure. The cantilever arm will then pop up once it is released from the dove-tail structure.

Abstract: Systems and methods for actuating micro-magnetic latching switches in an array of micro-magnetic latching switches are described. The array of switches is defined by Y rows aligned with a first axis and X columns aligned with a second axis. Each switch in the array of switches is capable of being actuated by a coil. In an aspect, a row of coils is moved along the second axis to be positioned adjacent to a selected one of the Y rows of switches. A sufficient driving current is proved to a selected coil in the row of coils to actuate a selected switch in the selected one of the Y rows of switches. In another aspect, a plurality of first axis drive signals and a plurality of second axis drive signals are generated. These signals drive an array of coils, wherein each coil in the array of coils is positioned adjacent to a corresponding switch in the array of switches. Each first axis drive signal is coupled to coils in a corresponding column of coils in the array of coils.

Abstract: A method for making an embedded toroidal inductor (118) includes forming in a ceramic substrate (100) a first plurality of conductive vias (102) radially spaced a first distance from a central axis (101) so as to define an inner circumference. A second plurality of conductive vias (104) is formed radially spaced a second distance about the central axis so as to define an outer circumference. A first plurality of conductive traces (110) forming an electrical connection between substantially adjacent ones of the first and second plurality of conductive vias is formed on a first surface (106) of the ceramic substrate. Further, a second plurality of conductive traces (110) forming an electrical connection between circumferentially offset ones of the first and second plurality of conductive vias is formed on a second surface of the ceramic substrate opposed from the first surface to define a three dimensional toroidal coil.