Patents Issued in November 22, 2007
-
Publication number: 20070267672Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a plurality of first trenches passing through the second semiconductor layer and reaching the first semiconductor layer; a gate insulating film provided on an inner wall of the first trench; and a gate electrode filling in the first trench via the gate insulating film. A PN junction interface is provided between the first semiconductor layer and the second semiconductor layer. A distance from an upper face of the second semiconductor layer to the PN junction interface is minimized nearly at a center between the first trenches.Type: ApplicationFiled: May 4, 2007Publication date: November 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshitaka HOKOMOTO, Akio Takano, Shunsuke Katoh
-
Publication number: 20070267673Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Applicant: International Business Machines CorporationInventors: Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
-
Publication number: 20070267674Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.Type: ApplicationFiled: May 22, 2006Publication date: November 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
-
Publication number: 20070267675Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.Type: ApplicationFiled: May 16, 2007Publication date: November 22, 2007Inventors: Sung-Il Cho, Choong-rae Cho, Eun-hong Lee, In-kyeong Yoo
-
Publication number: 20070267676Abstract: Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including at least one buried gate structure, buried entirely below an upper surface of an active fin and an upper surface of the isolation region.Type: ApplicationFiled: March 6, 2007Publication date: November 22, 2007Inventors: Keunnam Kim, Makoto Yoshida, Donggun Park, Wounsuck Yang
-
Publication number: 20070267677Abstract: A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, an assist gate, or assist gates are formed on the dielectric layer next to and between the control gate and floating gate respectively. The assist gates are used to form inversion diffusion regions in the substrate. By using the assist gates to form inversion diffusion regions, the overall size of the device can be reduced, which can improve device density.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Chang Kuo, Chao-I Wu
-
Publication number: 20070267678Abstract: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventor: Cheng-Yao Lo
-
Publication number: 20070267679Abstract: A memory device includes a gate stack on a substrate. The gate stack is disposed between a source and a drain. The gate stack includes a tunneling film, storage node, and control oxide film. A thickness of the control oxide film is greater than or equal to about 5 nm and less than or equal to about 30 nm. A method of manufacturing a memory device, including a gate stack on a substrate, wherein the gate stack is disposed between a source and a drain, includes: sequentially forming a tunneling film, a first silicon-rich oxide film, and a control oxide film on the substrate, wherein the first silicon-rich oxide film comprises a SiOx film (1.5<x<1.7); converting the first silicon-rich oxide film into a silicon oxide (SiO2) film comprising silicon nano-crystals; and patterning the control oxide film, the silicon oxide film, and the tunneling film to form the gate stack.Type: ApplicationFiled: March 15, 2007Publication date: November 22, 2007Inventors: Young-kwan Cha, Suk-ho Choi, Kyu-il Han, Young-soo Park, Sang-jin Park, Yong-min Park
-
Publication number: 20070267680Abstract: A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors are provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.Type: ApplicationFiled: May 16, 2007Publication date: November 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukinori Uchino, Muneaki Maeno, Yoichi Takegawa, Hisato Oyamatsu
-
Publication number: 20070267681Abstract: Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.Type: ApplicationFiled: May 18, 2007Publication date: November 22, 2007Inventors: Kyung Joong Joo, Han Soo Kim
-
Publication number: 20070267682Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.Type: ApplicationFiled: May 21, 2007Publication date: November 22, 2007Inventors: Masayuki Tanaka, Hirokazu Ishida
-
Publication number: 20070267683Abstract: A method for producing a nonvolatile memory cell in a semiconductor chip is provided, wherein a gate electrode is produced, a read region is produced, which together with the gate electrode forms a transistor arrangement, a first programming region is produced, which together with the gate electrode forms a first capacitor, a second programming region is produced, which together with the gate electrode forms a second capacitor, and a dielectric insulator is produced, which insulates the gate electrode from the read region and from the first programming region and from the second programming region. The gate electrode is deposited as a conductive layer on the dielectric insulator over the read region and also over the first programming region, as well as over the second programming region.Type: ApplicationFiled: May 22, 2007Publication date: November 22, 2007Inventor: Franz Dietz
-
Publication number: 20070267684Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively.Type: ApplicationFiled: May 17, 2007Publication date: November 22, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Hee-seog Jeon, Jeong-uk Han, Hyun-khe Yoo, Yong-kyu Lee
-
Publication number: 20070267685Abstract: A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a floating gate electrode layer located on the first gate insulating film, a first inter-gate insulating film located on the floating gate electrode layer, a control gate electrode layer located on the first inter-gate insulating layer, and a first low-resistance layer located on the control gate electrode layer. Each resistor has a second gate insulating film located on the semiconductor substrate, a first electrode layer located on the second gate insulating film, a second inter-gate insulating film located on the first electrode layer, a second electrode layer located on the second inter-gate insulating film, a second low-resistance layer located on the second electrode layer, and a contact plug connected to the second low-resistance layer.Type: ApplicationFiled: May 17, 2007Publication date: November 22, 2007Inventor: Shigeru ISHIBASHI
-
Publication number: 20070267686Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.Type: ApplicationFiled: July 24, 2007Publication date: November 22, 2007Applicant: SPANSION LLCInventors: Ashot MARTIROSIAN, Zhizheng Liu, Mark Randolph
-
Publication number: 20070267687Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.Type: ApplicationFiled: July 31, 2007Publication date: November 22, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Hang-Ting Lue
-
Publication number: 20070267688Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: ApplicationFiled: July 23, 2007Publication date: November 22, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
-
Publication number: 20070267689Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.Type: ApplicationFiled: July 24, 2007Publication date: November 22, 2007Inventors: Cem Basceri, Gurtej Sandhu
-
Publication number: 20070267690Abstract: This invention disclosed a novel method for the reduction the resistance of the drift region by using the minority carrier current injector near the drift region. This current injector is a p-n junction or a p-n junction in connection with a resistor to the gate or the p-n junction in connection with a current limiting device to the gate or a combination of the other devices. The current injecting reduces the chip size especially for the high voltage operations. The deep trench filled with oxide near the current injector is also disclosed as the diverter for redirection of the minority carrier current. The current injectors can also be used to shut off the main current flow of the DMOSFET during reverse bias and injecting minority carriers in the forward bias.Type: ApplicationFiled: May 14, 2007Publication date: November 22, 2007Inventor: Ho-Yuan Yu
-
Publication number: 20070267691Abstract: A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.Type: ApplicationFiled: July 23, 2006Publication date: November 22, 2007Applicant: PROMOS TECHNOLOGIES INC.Inventors: Yu-Chi Chen, Jih-Wen Chou, Frank Chen
-
Publication number: 20070267692Abstract: Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.Type: ApplicationFiled: January 25, 2007Publication date: November 22, 2007Inventors: Kyung Joong Joo, Han Soo Kim
-
Publication number: 20070267693Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.Type: ApplicationFiled: May 22, 2006Publication date: November 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsing-Yi Chien, Yu-Chang Jong, Ruey-Hsin Liu, Te-Yin Hsia
-
Publication number: 20070267694Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.Type: ApplicationFiled: May 22, 2006Publication date: November 22, 2007Inventors: Chih-Hsin Ko, Chung-Hu Ke, Hung-Wei Chen, Wen-Chin Lee
-
Publication number: 20070267695Abstract: Methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; methods of forming a partial SOI structure which include providing a single crystal silicon substrate having a device pattern formed thereon where the device pattern comprises a non-SOI region and an SOI region having a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; structures formed by such methods; and partial silicon-on-insulator structures comprising a single crystal silicon substrate having an device pattern disposed on a surface thereof where the device pattern includes a non-SOI region and an SOI region having a protrusion, and aType: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Ming-Hsiu Lee
-
Publication number: 20070267696Abstract: A mobile transforming plug includes an insulating main body, a shell cover, a linking element and a linker. At the front side of the insulating main body, a connecting part is formed. A carrying part is formed at the rear side of the insulating main body. There is a connection area on the carrying part. The front two sides of the insulating main body each have a concave slot and a wedging-buckling end. A wedge extends from each of the two sides of the shell cover. The wedges are positioned in the concave slots and are wedged movably at the wedging-buckling end. The linking element is located at the connection area and connected with the pins. The linker is linked with the linking element. Thereby, the plug is plugged movably with the Internet or telephone plug. It can be plugged movably with the external plughole of electronic information products.Type: ApplicationFiled: April 25, 2006Publication date: November 22, 2007Inventor: Sheng-Hsin Liao
-
Publication number: 20070267697Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.Type: ApplicationFiled: September 7, 2006Publication date: November 22, 2007Applicant: Industrial Technology Research InstituteInventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
-
Publication number: 20070267698Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: July 9, 2007Publication date: November 22, 2007Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Paul Kartschoke, Anthony Stamper
-
Publication number: 20070267699Abstract: A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge density within the portion relative to a remainder of the channel region.Type: ApplicationFiled: July 24, 2007Publication date: November 22, 2007Inventor: Randy Hoffman
-
Publication number: 20070267700Abstract: According to one embodiment of the present invention, an ESD protection element for use in an electrical circuit is provided, including a plurality of diodes which are connected in series with one another and which are formed in a contiguous active area, wherein the ESD protection element has a fin structure.Type: ApplicationFiled: May 18, 2007Publication date: November 22, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Christian Russ, Harald Gossner, Michael Fulde
-
Publication number: 20070267701Abstract: A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.Type: ApplicationFiled: December 27, 2006Publication date: November 22, 2007Inventors: Myung-Hee Sung, Young-Man Ahn
-
Publication number: 20070267702Abstract: A dynamic threshold voltage p-channel MOSFET (PMOS) for ultra-low power ultra-low voltage applications is disclosed. These applications are of low-to-moderate performance requirements; hence ultra-low voltage subthreshold operation, where the supply voltage is less than the transistors threshold voltage, is suitable. By tying the PMOS body to the output node of the transistor circuit in which this PMOS is part of will provide the necessary body bias for this PMOS threshold voltage to change dynamically with the circuit's output status. The dynamic change of the PMOS transistor threshold voltage will consequently dynamically increase or decrease the subthreshold leakage current which is the switching current in subthreshold circuits.Type: ApplicationFiled: May 11, 2007Publication date: November 22, 2007Inventors: Walid Elgharbawy, Magdy Bayoumi
-
Publication number: 20070267703Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yung Fu Chong, Zhijiong Luo, Judson Holt
-
Publication number: 20070267704Abstract: A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form first and second semiconductor layers; implanting first impurities into the first and second semiconductor layers; implanting second impurities into the first or second semiconductor layer; and performing a second annealing process on the semiconductor layers to remove the metal catalyst remaining in the first or second semiconductor layer, on which the second impurities are implanted, wherein the first impurities are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the second impurities are implanted at a dose of 1×1011/cm2to 3×1015/cm2.Type: ApplicationFiled: April 27, 2007Publication date: November 22, 2007Applicant: Samsung SDI Co., Ltd.Inventors: Tae-Hoon YANG, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
-
Publication number: 20070267705Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.Type: ApplicationFiled: October 27, 2006Publication date: November 22, 2007Inventors: Seok-Jun Won, Jung-Min Park
-
Publication number: 20070267706Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.Type: ApplicationFiled: July 27, 2007Publication date: November 22, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Hiroaki Niimi
-
Publication number: 20070267707Abstract: A semiconductor device includes: a first active region surrounded with an isolation region of a semiconductor substrate; a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region; a first side-wall insulating film; an auxiliary pattern formed to be spaced apart in the gate width direction from the protrusion of the first gate electrode; a second side-wall insulating film; and a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film. In this device, the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film.Type: ApplicationFiled: May 15, 2007Publication date: November 22, 2007Inventor: Masafumi Tsutsui
-
Publication number: 20070267708Abstract: Disclosed are methods for attaching an integrated circuit to a substrate, and in particular, a fused silica substrate, along with apparatus fabricated using the methods. Exemplary apparatus comprises a glass substrate, a metallic layer disposed on the substrate, and an integrated circuit eutectically bonded to the glass substrate via the metallic layer. The integrated circuit and fused silica substrate form part of a hermetic sensor. In an exemplary sensor, a first trench is formed in a first substrate. A second trench that is deeper than the first trench is formed in the first substrate. A first plurality of electrodes are formed in the first trench. An integrated circuit is attached to the first substrate within the second trench using a solder preform.Type: ApplicationFiled: May 15, 2007Publication date: November 22, 2007Inventor: Christophe Courcimault
-
Publication number: 20070267709Abstract: A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate. The semiconductor region is a diffusion layer including a conductive impurity doped and diffused therein. The semiconductor region is made of diffusion layer so that the device has high design degree of freedom.Type: ApplicationFiled: June 28, 2007Publication date: November 22, 2007Applicant: DENSO CORPORATIONInventor: Satoshi Oohira
-
Publication number: 20070267710Abstract: A photosensor includes a photovoltage generator for generating a photovoltage, and a comparator for determining a number of integer multiples of a threshold voltage associated with the photosensor. A primary counter is incremented by the determined number of integer multiples. A voltage injector adds at least one unit of voltage to the comparator, with each voltage unit having a value less than the threshold voltage. A secondary counter determines a number of voltage units needed to cause the voltage in the comparator to attain an integer multiple of the threshold voltage.Type: ApplicationFiled: May 17, 2007Publication date: November 22, 2007Applicant: STMicroelectronics (Research & Development) LimitedInventor: Jeffrey Raynor
-
Publication number: 20070267711Abstract: An optical receiving device has a photoelectric conversion layer including a matrix semiconductor containing silicon atoms as a main component, an n-type dopant D substituted for the silicon atom in a lattice site, and a heteroatom Z inserted into an interstitial site positioned closest to the n-type dopant D, in which the heteroatom Z has an electron configuration of a closed shell structure through charge compensation with the dopant D.Type: ApplicationFiled: March 20, 2007Publication date: November 22, 2007Inventors: Kazushige Yamamoto, Tatsuo Shimizu, Shigeru Haneda
-
Publication number: 20070267712Abstract: With the reduced size of a solid state imaging device, the invention provides: a solid state imaging device of a chip size and having good environmental durability; a semiconductor wafer used for fabricating a solid state imaging device; an optical device module incorporating a solid state imaging device; a method of solid state imaging device fabrication; and a method of optical device module fabrication. The solid state imaging device comprises: a solid state image pickup device formed on a semiconductor substrate; a light-transparent cover arranged opposite to an effective pixel region, so as to protect (the surface of) the effective pixel region formed in one surface of the solid state image pickup device against external environment; and an adhering section formed outside the effective pixel region in the one surface of the solid state image pickup device, so as to adhere the light-transparent cover and the solid state image pickup device.Type: ApplicationFiled: April 30, 2007Publication date: November 22, 2007Inventors: Kazuya Fujita, Hiroaki Tsukamoto, Takashi Yasudome
-
Publication number: 20070267713Abstract: A communication device capable of transmitting a signal by two-dimensional diffusive signal transmission technology includes: a signal layer in which the signal is transmitted; a plurality of communication chips which are connected to the signal layer to transmit the signal by the two-dimensional diffusive signal transmission technology; a power supply layer which supplies electric power to each of the communication chips; a ground layer which is electrically connected to each of the communication chips as ground for the electric power; and an attenuation layer which is placed between the signal layer and the power supply layer, attenuates electric current that can flow between the signal layer and the power supply layer, and pulls up electric potential of the signal layer toward that of the power supply layer.Type: ApplicationFiled: May 14, 2007Publication date: November 22, 2007Applicant: PENTAX CORPORATIONInventor: Tadashi MINAKUCHI
-
Publication number: 20070267714Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: ApplicationFiled: August 2, 2007Publication date: November 22, 2007Inventor: Mou-Shiung Lin
-
Publication number: 20070267715Abstract: Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first silicon dioxide liner substantially lines the first trench. A second silicon dioxide liner substantially lines the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner. A silicon nitride liner is on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Inventors: Sunil Mehta, Stewart Logie, Steve Fong
-
Publication number: 20070267716Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.Type: ApplicationFiled: May 20, 2006Publication date: November 22, 2007Inventors: SERGEY ANTONOV, ALEXEI I ANTONOV
-
Publication number: 20070267717Abstract: An insulator supporting an inner conductor within the outer conductor of a coaxial device formed from a portion of thermally conductive polymer composition with a thermal conductivity of at least 4 W/m-K. The portion is dimensioned with an outer diameter in contact with the outer conductor and a coaxial central bore supporting there through the inner conductor. Cavities may be formed in the portion for dielectric matching and or material conservation purposes. The insulator may be cost effectively fabricated via injection molding.Type: ApplicationFiled: March 22, 2007Publication date: November 22, 2007Applicant: ANDREW CORPORATIONInventor: Kendrick Van Swearingen
-
Publication number: 20070267718Abstract: A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each other. Each looped conductive trace has a gap to define first and second ends and at least two conductive plugs disposed between the neighboring looped conductive traces. The single-level interconnect structure is located over the multi-level interconnect structure, comprising an uppermost looped conductive trace and a second conductive plug. The uppermost looped conductive trace has a gap to define first and second ends, and the second conductive plug is disposed between the second end of the uppermost looped conductive trace and the first end of the looped conductive trace adjacent thereto, thereby electrically connecting the multi-level and single-level interconnect structures.Type: ApplicationFiled: November 13, 2006Publication date: November 22, 2007Applicant: VIA TECHNOLOGIES, INC.Inventor: Sheng-Yuan Lee
-
Publication number: 20070267719Abstract: The present invention provides a structure and the manufacturing method of high precision chip capacitor fabricated on silicon substrate. The structure of the chip capacitor consists of a dielectric layer formed on the surface of a heavily doped silicon substrate with an inner primary portion of thin oxide and an outer secondary portion of thicker oxide; both oxides are merged seamlessly together into the single dielectric layer thus allowing a layer of electrically conducting film deposited on its surface as the first electrode of the capacitor, while the heavily doped silicon substrate on the opposite surface of the dielectric oxide plays as the bottom electrode. The bottom electrode is electrically connected up to a second electrode on the upper surface through a via so that both the first and second electrodes can be on the same surface for subsequent bumping process, finally, two solder bumps is formed on the top as a surface mountable chip capacitor component.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Inventor: Jin Shown Shie
-
Publication number: 20070267720Abstract: A semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. Adjacent first and second conductive strips of the upper conductive strip group are adapted to receive a first voltage, a third conductive strip of the lower conductive strip group is adapted to receive a second voltage. A capacitor is provided at a first intersection between the first and third conductive strips and at a second intersection between the second and third conductive strip, and the capacitor extends from the first intersection to the second intersection.Type: ApplicationFiled: May 17, 2007Publication date: November 22, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Takeshi Toda, Naoya Nakayama
-
Publication number: 20070267721Abstract: A phase change memory cell includes an interlayer insulating layer formed on a semiconductor substrate, and a first electrode and a second electrode disposed in the interlayer insulating layer. A phase change material layer is disposed between the first and second electrodes. The phase change material layer may be an undoped GeBiTe layer, a doped GeBiTe layer containing an impurity or a doped GeTe layer containing an impurity. The undoped GeBiTe layer has a composition ratio within a range surrounded by four points (A1(Ge21.43, Bi16.67, Te61.9), A2(Ge44.51, Bi0.35, Te55.14), A3(Ge59.33, Bi0.5, Te40.17) and A4(Ge38.71, Bi16.13, Te45.16)) represented by coordinates on a triangular composition diagram having vertices of germanium (Ge), bismuth (Bi) and tellurium (Te).Type: ApplicationFiled: May 11, 2007Publication date: November 22, 2007Inventors: Bong-Jin Kuh, Yong-Ho Ha, Doo-Hwan Park, Jeong-Hee Park, Han-Bong Ko