Abstract: Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Abstract: A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.

Abstract: Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

Abstract: A programmable logic block for an asynchronous circuit design is disclosed. After a programmable setup, the logic block not only has the processing function of common devices, but also communicates using the asynchronous protocol so as to design an asynchronous device.

Abstract: The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: Methods and computer readable media are provided for implementing state machines in parallel. A control vector is generated from current state and input bits. This vector is then used to determine the next state and any output bits for each of a plurality of state machines in parallel. In some implementations, the Altivec vperm instruction is used to perform a parallel table look-up.

Abstract: A level shifter for use in a dual power supply circuit operating from a VDD power supply and a VDDH power supply greater than the VDD power supply. The level shifter indicates to a status circuit in the VDDH power supply domain that the VDD power supply is enabled. The level shifter detects when the VDD power supply is on and sets an enable signal to the status circuit. The level shifter also detects when the VDD power supply is off and clears the enable signal to the status circuit.

Abstract: A buffer and organic light emitting display with data driving circuit using the buffer is provided. A buffer comprises a first capacitor for receiving an analog voltage; a first inverter having an input terminal connected to the first capacitor; a second inverter having an input terminal connected to an output terminal of the first inverter through a second capacitor; a third capacitor connected to an output terminal of the second inverter; a first transistor for controlling a current which flows from a first power source to a data line so that the buffer output voltage is supplied to the data line in response to a control signal supplied to the third transistor which is connected between the data line and the first capacitor.

Abstract: In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.

Abstract: A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

Abstract: A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.

Abstract: A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections are provided between those components and the remainder of the PLD so that if the PLL is not being used in a particular user design of the PLD, the PLL modular components may be used by other portions of the PLD. Similarly, those connections allow other portions of the PLD to be used in place of one or more of the modular components where more complex or special filtering than can be provided by the modular components is required.

Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).

Abstract: A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

Abstract: A driver circuit for a transistor provides a soft start feature where pulses provided to the transistor are varied in duration during startup. The driver also provides an overcurrent protection feature for disabling a driver output for a safe period of time when an overcurrent condition is detected. The driver circuit includes an oscillator that produces a saw tooth wave and a narrow width pulse train for determining pulse width and dead time, respectively. The driver circuit may be used in half-bridge or full-bridge drivers.

Abstract: A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

Abstract: A system and method for providing a voltage. The system includes a first transistor with a first gate, a first terminal, and a second terminal, a second transistor with a second gate, a third terminal, and a fourth terminal, and a third transistor with a third gate, a fifth terminal, and a sixth terminal. Additionally, the system includes a fourth transistor with a fourth gate, a seventh terminal, and an eighth terminal, a fifth transistor with a fifth gate, a ninth terminal, and a tenth terminal, and a sixth transistor with a sixth gate, an eleventh terminal, and a twelfth terminal. The tenth terminal and the eleventh terminal are directly connected at a third node, which is directly connected to a first substrate for the third transistor, a second substrate for the fourth transistor, a third substrate for the fifth transistor, and a fourth substrate for the sixth transistor.

Abstract: To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.

Abstract: An integrated semiconductor circuit has a potential detector for detecting a potential boosted by a high voltage generator. One terminal of a first capacitor is connected to a potential detection terminal via a first switching device, the other terminal thereof being connected to a reference potential terminal. A terminal of a second capacitor is connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, the other terminal thereof being connected to the reference potential terminal. A third switch is connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal. A clock generator generates clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices.

Abstract: A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: A voltage supply circuit for generating a composite bandgap reference voltage includes a single bandgap reference voltage circuit and a select circuit. The bandgap reference circuit has a first output to generate a first bandgap voltage having a first temperature coefficient and has a second output to generate a second bandgap voltage having a second temperature coefficient that is different from the first temperature coefficient. The select circuit has a first input to receive the first bandgap voltage, a second input to receive the second bandgap voltage, and an output to selectively provide either the first bandgap voltage or the second bandgap voltage as the composite bandgap reference voltage.

Abstract: A step-down power supply receives an external power supply voltage and supplies power at a reduced voltage from an output node to a load. The power supply also receives a reference voltage and a control signal indicating the whether the load is active or not. The reduced power supply voltage is held equal to the reference voltage by adjustment of the voltage at an internal control node. To prevent fluctuations in the reduced power supply voltage at active-inactive transitions of the load, the power supply includes circuitry for pulling the voltage at the internal control node both up and down, circuitry for leaking current from the output node to ground, circuitry for temporarily raising and lowering the reference voltage, or a capacitor coupling the reference voltage signal line to the control signal line.

Abstract: A semiconductor device includes a current mirror circuit having a plurality of transistors; a current source configured to supply a constant reference current to the current mirror circuit through a node; and a compensating circuit configured to supply a compensation current to the node to compensate for at least a part of gate leakage currents of the plurality of transistors. The compensating circuit may supply the compensation current equal to a summation of the gate leakage currents.

Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Abstract: An amplitude demodulation method and device comprising a converter sampling an input signal having its sampling frequency corresponding to three times the modulation carrier frequency.

Abstract: Disclosed is a distortion compensating and power amplifying apparatus including: a transistor to power amplifies an input signal; a branch circuit to branch the input signal into two signals; distortion compensation means for generating a second harmonic of a fundamental wave for one of branched signals and adding the generated second harmonic to the other branch signal from said branch circuit for input to an input terminal of said transistor; and a termination circuit connected to an output terminal of said transistor and grounding the second harmonic.

Abstract: An amplifier is provided. The amplifier comprises an H-bridge with two halves. A capacitor and two inductors are coupled to the H-bridge. Each inductor, a half of the H-bridge, and the capacitor are configured as a boost converter.

Abstract: A radio frequency (RF) generator includes a first half bridge including first and second power transistors; a second half bridge including first and second power transistors; an output node coupling the first and second half bridges and RF signals to a load; positive and negative rails coupled to an AC power source via a rectifier; a first blocking capacitor provided between the positive rail and the load; a second blocking capacitor provided between the negative rail and the load; and a voltage regulator configured to output a given voltage to the first and second bridges, wherein the first and second blocking capacitors are configured to isolate the load from the AC power source.

Abstract: A circuit and a method for nullifying temperature dependence of a circuit characteristic. The circuit includes a plurality of transistors configured such that they generate a gate voltage that includes a threshold voltage as a component. The gate voltage is applied to a transistor to generate a current that is proportional to a process transconductance parameter. The current is applied to a comparator having a differential pair of transistors, wherein each transistor has a process transconductance parameter. The circuit takes the ratios of the process transconductance parameter associated with the current to that of each transistor of the differential pair. By rationing the process transconductance parameters, temperature dependence is nullified or negated. The ratios can be used to set the hysteresis voltage of the comparator.

Abstract: An apparatus for affecting operation of a signal treating device that is provided an operating voltage ranging between an upper voltage limit and a lower voltage limit for treating at least one input signal includes: a respective dynamic bias unit coupled with the signal treating device for each respective input signal of the at least one input signal; and a respective transconductance control unit coupled with each the respective dynamic bias unit. Each respective dynamic bias unit and transconductance control unit cooperates to operate the signal treating device responsive to the at least one input signal approaching at least one of the upper voltage limit and the lower voltage limit.

Abstract: An adjustable power amplifier includes an input capacitor, an input transistor, an inductor, an output capacitor, and a gain module. The input capacitor includes a first plate and a second plate, wherein the first plate of the input capacitor is operably coupled to receive an input radio frequency (RF) signal. The input transistor includes a gate, a drain, and a source, wherein the gate of the input transistor is operably coupled to the second plate of the input capacitor and the source of the input transistor is operably coupled to a circuit ground. The inductor includes a first node and a second node, wherein the first node of the inductor is operably coupled to a power supply and the second node of the inductor is operably coupled to the drain of the input transistor.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

Abstract: A minimum frequency synchronization discriminator for use in providing a clock signal for a switch mode power supply automatically detects when the frequency of a sync signal is above a minimum frequency and causes the sync signal to serve as the clock signal for the controller. If the frequency of the sync signal is below the minimum frequency, the minimum synchronization frequency discriminator causes the output signal of the internal oscillator to serve as the clock signal.

Abstract: A ring oscillator setting apparatus and method depending on an environmental change of an image formation apparatus is provided. The apparatus includes a plurality of ring oscillators for generating different oscillation frequencies. The apparatus further includes a loopspeed detection unit to detect a loopspeed representing the number of pulses generated at the oscillation frequency by one of the ring oscillators selected from the plurality of ring oscillators for a predetermined unit time. Moreover, a state sensing unit is provided to detect a state of system environment of the image formation apparatus. A setting control unit is also provided to select and set one of the ring oscillators selected corresponding to change of the loopspeed detected from the loopspeed detection unit among the plurality of ring oscillators in response to the detected state of the state sensing unit.

Abstract: Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; at least one integrated circuit block formed in the semiconductor substrate; a first electrode pad which receives a first clock, the first electrode pad being disposed on the semiconductor substrate; a wiring line which electrically connects the integrated circuit block and the first electrode pad, the wiring line being disposed on the semiconductor substrate; and a second electrode pad which receives a second clock having the same frequency as and opposite polarity from the first clock, the second electrode pad being disposed in a position adjacent to the first electrode pad on the semiconductor substrate and isolated from the integrated circuit block.

Abstract: An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.

Abstract: An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Abstract: A driver device for a voltage-controlled oscillator, having an unstable voltage source, a voltage regulator, a driver for generating a control voltage for the oscillator, and a feedback loop which controls the driver as a function of the output signal of the oscillator; the voltage regulator supplying the feedback loop with operating voltage while the driver is powered by the unregulated voltage of the voltage source, and the feedback loop compensates for voltage fluctuations of the voltage source with the aid of the driver.

Abstract: The invention relates to a method of estimating an intersection between at least two continuous signal representations (SR1, SR2) in a pulse width modulator, at least one of said continuous signal representations (SR1, SR2) being non-linear, said method comprising the step of providing an intersection estimate (CPE) between said at least two continuous signal representations on the basis of at least one iteration comprising at least one iterative call of a function describing said continuous signal representations (SR1, SR2) being non-linear and whereby said estimating of intersections are performed in a pulse width modulation modulator. According to an embodiment of the invention, a simple iterative call of the established continuous signal representation, e.g. an interpolation polynomial, will provide the desired intersection. It should be noted that the established estimate might be provided without any complicated root solving and avoiding division and even square root.

Abstract: A magnetic rotor includes a soft ferrite substrate and a plurality of central conductors. The magnetic rotor is provided inside a casing. A permanent magnet is provided inside the casing, and disposed to overlap the magnetic rotor so as to apply a DC magnetic field to the magnetic rotor. The casing includes a magnetic metal material. The casing is coupled with the permanent magnet so as to form a yoke. A coupling portion is formed in a direction crossing a magnetic circuit of the yoke. The casing is coupled in a direction of the magnetic circuit through the coupling portion. The coupling portion includes a capacitance element which has high impedance in response to a DC current and has low impedance in response to a high frequency current.

Abstract: A high frequency switch device has SPDT(A), SPDT(B), and SPDT(C) switches, each having one pole and a first port and a second port, wherein the second port of the SPDT(A) is grounded via a terminating resistor and the second port of the SPDT(B) is grounded via a terminating resistor, respectively, and the first port of the SPDT(A) and the first port of the SPDT(B) are respectively connected to the first port and the second port of the SPDT(C).

Abstract: RF switching system (100, 200) formed from a structure (102, 202) comprised of dielectric material. The structure can have two or more faces (104, 204), with at least one face located in a plane exclusive of at least a second one of the faces. For example, the structure can define a geometric shape that is a polyhedron. RF switches (106, 206) can be disposed on two or more of the faces. Conductive RF feed stubs (110, 210) are provided for each RF switch extending from an interconnection point (114, 214) to electrical contact terminals (116, 216) that are respectively connected to the RF switches. The interconnection point is located within the structure at a location generally medial to the two or more of terminals.

Abstract: An apparatus that includes a first conducting strip having a narrowed width where the first conducting strip also acts as a first electrode for a first tapping capacitance. The first tapping capacitance has a second electrode that is: 1) parallel to the first conducting strip; and 2) closer to the first conducting strip than a second conducting strip. The second conducting strip is parallel to the first conducting strip and has a narrowed width where the second conducting strip also acts as a first electrode for a second tapping capacitance. The second tapping capacitance has a second electrode that is: 1) parallel to the second conducting strip; and 2) closer to the second conducting strip than the first conducting strip.

Abstract: A hybrid 180° microwave balun device is provided to convert an unbalanced RF signal at the common port into two radio frequency signals with equal amplitude and 180° phase difference at two differential ports. The hybrid device includes a coplanar waveguide connecting to the common port. A power divider separates the coplanar waveguide into two symmetrical slotline waveguides to carry balanced signals. Two broadband multioctave slotline to microstrip transitions constructed in a way that the microstrip lines carry 180° phase separated signals to the differential output ports.

Abstract: One aspect of the invention provides a signal separating device comprising a first and a second circuit branch connected to an antenna port, the first circuit branch comprising a filter for passing signals in a first frequency band, and the second circuit branch comprising a filter for passing signals in a second frequency band. The first and second circuit branches being arranged so that a respective reactive impedance is presented to the antenna port in both said first and said second frequency bands. The device further comprises an impedance matching circuit at the antenna port arranged to substantially to cancel out the respective reactive impedances. In the preferred embodiment, each circuit branch presents a respective shunt capacitance to the antenna port when out-of-band and the matching circuit comprises a shunt inductor at the antenna port.

Abstract: An electrical filter assembly including a housing; at least one electrical wire extending into the housing; and a filter subassembly on the housing, the filter subassembly comprising a lead frame and a filter circuit connected to the lead frame. The filter circuit has a plurality of capacitors attached to the lead frame as a modular block. The lead frame comprises at least one insulation displacement contact section which makes electrical connection with the at least one electrical wire.