Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.

Abstract: The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

Abstract: In a NAND flash memory device, a dummy NAND string is arranged between a plurality of normal NAND strings. A dummy bit line connected to the dummy NAND string is formed and/or controlled such that when program voltages are applied to the normal NAND strings, memory cells within the dummy NAND string are not programmed.

Abstract: Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.

Abstract: Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.

Abstract: Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

Abstract: A column decoding system (140, 150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage (PEN) to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi, Mij, Pij) each one having a threshold voltage, and selection means for selecting a path corresponding to a selected bit line, the selection means including means for biasing at least one transistor in each non-selected path to an open condition to have the corresponding non-selected bit line floating; the selection means further includes means for biasing at least one other transistor in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of the other transistor in absolute value.

Abstract: Provided are a semiconductor device and a method for compensating for a voltage drop of a bit line. The semiconductor device includes at least one monitoring bit line and at least one main memory bit line, and monitors a voltage of the at least one monitoring bit line after a precharging operation and supplies a predetermined compensation current to the at least one monitoring bit line and the at least one main memory bit line based on a monitoring result. Accordingly, it is possible to precisely compensate for a voltage drop occurring in the main memory bit line due to under precharge or leakage current, thereby preventing unnecessary compensation current from being supplied. Therefore, it is possible to stably perform a read operation of the semiconductor device.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite to the predetermined logic value, an erasing operation is needed and the data writing is regulated. By rewriting a pointer value stored in a pointer memory in place of performing the erasing operation, an operation of switching a memory core to be selected to a second memory core (data “11111111”) is performed. Data is newly written into the second memory core selected by the rewritten pointer value.

Abstract: Systems and methods are provided for handling instances of providers in a plurality of frameworks. An instance of a first provider is created and registered to store a first change to a buffer. An instance of a second provider is created and registered to store a second change to the buffer. The buffer is checked to determine whether data consistency is guaranteed to result from the first and second changes. If data consistency is guaranteed, the first and second changes are committed to a database.

Abstract: Reducing power consumption of a semiconductor memory device having a serial interface is disclosed. After parallel read-out data from a memory-cell matrix 14 are held in a data latch 17, the parallel read-out data are selected sequentially by a serial output selector 18 according to timing signals SL0-SL15 from a controller 20 and are outputted serially from an output buffer 19 as an output data DO. In an activating control unit 23, outputting an operation control signal AC to a gate-voltage generating unit 21, a drain-voltage generating unit 22, and a sense amplifier 16 is being halted during from when a timing signal SL0 is finished to when a timing SL10 is finished. Consequently, during the above mentioned period, the unnecessary operations of the gate-voltage generating unit 21, the drain-voltage generating unit 22, and the sense amplifier 16 are being halted and then the power consumption thereof can be reduced.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.

Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current.

Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

Abstract: A temperature gain compensation system for disk label laser etching process contains a servo device, a DSP, a driver IC, and a temperature compensator. A temperature sensor in the servo device transmits a temperature signal to the temperature compensator. Then the temperature compensator obtains a temperature difference and calculates a corresponding feedback control signal. The DSP and the driver IC process the feedback control signal to adjust the servo device.

Abstract: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.

Abstract: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

Abstract: A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).

Abstract: Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.

Abstract: The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input to the cell. The reduced voltage reduces the current leakage of the electronic components within the cell. Some embodiments provide a memory circuit that has a level converter. The level converter receives a reduced voltage and converts the reduced voltage into values that can be used to store and retrieve data with stability in the cell. Some embodiments provide a method for storing data in a memory circuit that has a storage cell. The method applies a reduced voltage to the input of the cell. The method level converts the reduced voltage. The reduced voltage is converted to a value that can be used to store and retrieve data with stability in the cell. The reduced voltage reduces a current leakage of electronic components within the cell.

Abstract: A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports.

Abstract: In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only provide signals, and the control circuitry is to control whether the third ports are to only receive signals or only provide signals. Other embodiments are described and claimed.

Abstract: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.

Abstract: Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS latency, wherein the CAS latency control unit generates a signal for controlling the output driver by using time difference between the DLL clock signal and an external clock applied to the memory device from an exterior.

Abstract: A flat portable mixing sheet with handles for manually blending materials in heterogeneous phases, particularly dry and liquid materials into a homogeneous mixture. The materials to be blended will be placed in the center of the mixing sheet and the handles of the sheet will be pulled alternately upward and toward the center of the sheet to tumble the materials while supported on the ground or floor into the required consistency. The mixed materials can then be transported on the sheet by the handles and poured into the designated location utilizing the midpoint along the side of the sheet as a spout. The handles are preferably made of high density polyethylene and thermally bonded to the mixing sheet.

Abstract: A stirring rod includes a soft pipe having a protrusion at an end, an open end at another end, and one or more grooves at the periphery of the pipe. A rod is inserted into the pipe, and the length of the rod sheathed into the pipe is shorter than the length of the pipe. The rod and the pipe are latched by the latch, such that when the pipe is compressed by the rod to spread open the groove, the position adjacent to each groove is extended outward, and the pipe is changed from a linear shape to a shape of an outwardly extended flower, so as to increase the stirring area and give more fun to the use of the stirring rod. After the stirring rod is used, the rod can be pressed gently to separate the latch, and then the pipe resumes its original shape.

Abstract: An improved magnetic drive for a mixing system and method, wherein stagnation or collection of material in the region of the containment shell and any magnetic rotor are alleviated by the provision of pitched blades provided as radially extending spokes in the inner magnetic rotor. This bladed rotor design may be particularly advantageous in the case of a side entry mixer.

Abstract: An automatic stirring and rotating cup holder comprises a stand, a power mechanism and a stirring device, wherein the stand has a disk for holding a cup and a coupling part for coupling with the power mechanism. A transmission is mounted inside the stand, wherein the disk is rotated by the transmission. Several control keys are mounted on the power mechanism, and the stirring device is mounted on the power mechanism for performing a stirring process corresponding to the movement of the disk. Accordingly, the solution inside the cup can be mixed adequately for drinking the solution easily and increasing the visual enjoyment.

Abstract: A cooking apparatus includes a spatula assembly and a cooking container comprising an upper access opening and an inner, cooking surface having a spherical surface portion. The spatula assembly includes a spatula driver and a curved spatula pivotally mounted to the cooking container for moving along the cooking surface and about a pivot axis between first and second positions. The pivot axis passes through the center point of the spherical surface portion. The spatula assembly may be constructed so that at least one of the first and second positions is above the pivot axis. The curved spatula may also include a spatula body having an outer surface and a barrier member extending radially inwardly from the outer surface, the outer surface contacting the cooking surface of the cooking container.

Abstract: An improved method and apparatus for mixing is provided that features a drive system that is removable from a bearing housing that supports the impeller shaft in the vessel. Some versions of the system and method use a magnetic drive system having a canister projecting outward from the bearing housing. The drive system has a lower shell that engages with the bearing housing and is quickly releasable and/or detachable to facilitate mounting and dismounting of the drive system from the bearing assembly.

Abstract: The method for exploring desired characteristics of a subsurface sector, having at least one resonant frequency, is based on selectively transmitting suitable narrowband energy waves into the subsurface sector, thereby producing narrowband signals reflected off the subsurface sector. The transmitted narrowband energy waves can be selectively and optimally adjusted in real time so as to provide optimum illumination of the desired characteristics from the explored sector.

Abstract: A method and system for acquiring seismic data from a seismic survey plan is provided. A survey area is selected in which the seismic data will be acquired. A coordinate for at least one point of interest within the survey area is determined and input into a portable navigation device. A navigation solution is determined between a GPS-determined location of the portable navigation device and the determined coordinate and thereupon presented in a human cognizable media. A seismic device may be positioned at the determined coordinate to insonify a subterranean formation with seismic energy or for detecting reflected seismic energy. Data may be periodically entered into and retrieved from the portable navigation device by an in-field operator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A seismic spread has a plurality of seismic stations positioned over a terrain of interest and a controller programmed to automate the data acquisition activity. In one aspect, the present disclosure provides a method for forming a seismic spread by developing a preliminary map of suggested locations for seismic devices and later forming a final map having in-field determined location data for the seismic devices. Each suggested location is represented by a virtual flag used to navigate to each suggested location. A seismic device is placed at each suggested location and the precise location of the each placed seismic devices is determined by a navigation device. The determined locations are used to form a second map based on the determined location of the one or more of the placed seismic devices. Using the virtual flag eliminates having to survey the terrain and place physical markers and later remove those physical markers.

Abstract: A seismic spread has a plurality of seismic stations positioned over a terrain of interest and a controller programmed to automate the data acquisition activity. In one embodiment, the controller forms a queue of sources that are ready to fire and initiating the firing of the sources according to a preset protocol. The sensor stations each include power management circuitry that may shift or adjust the power level of the sensor station during the data acquisition activity. During operation, the controller broadcasts data that the power management circuitry of each sensor station uses to determine the appropriate energy state for that sensor station. This determination may be made using the broadcast data alone or in conjunction with other data such as a GPS-determined position of the sensor station. Thus, in one aspect, each sensor station self-selects an energy state according to the broadcast status of the data acquisition activity.

Abstract: A seismic data acquisition system includes a controller, a plurality of sensor stations and a plurality of seismic sources. Each sensor station includes a sensor coupled to the earth for sensing seismic energy in the earth. The sensor provides a signal indicative of the sensed seismic energy and a recorder device co-located with the sensor unit that receives and stores the signals. A communication device is co-located with the sensor station and provides direct two-way wireless communication with the central controller. In one embodiment, in-field personnel determine elevation values, or Z values, for the sensor stations and seismic source by accessing a digital elevation model or a look-up table based on the digital elevation model. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A method, system and apparatus for Resonance-Based Acoustic Reflectometry that uses a hybrid approach. A method of manufacture, system and apparatus for a modified circle system that allows for the connection of extra devices like exemplary embodiments of the present invention.

Abstract: In order to locate electromagnetic or acoustic signal sources of a sensor configuration (1 a through 1 c) fitted with at least two electric outputs; where the incidence-dependent transfer functions between the acoustic signals incident on the input(s) of the sensor configuration (1 a through 1 c) and the electric output signals are different, the ratio (7X through 7XX) of the output signal is formed and the result then is correlated with the previously determined ratio function (11).

Abstract: Disclosed is an underwater projector projecting a sound underwater. The underwater projector includes a first disk-type resonator unit, a second disk-type resonator unit, and a central space. The second disk-type resonator unit is installed so that a central axis corresponds with that of the first disk-type resonator unit. The central space is set up between the first disk-type resonator unit and the second disk-type resonator unit, and water can enter the central space.

Abstract: The invention relates to an electromechanical programmer which includes a manual adjustment programming dial, a synchronous drive motor for rotating the dial and which is equipped with a terminal pinion. The movement of the terminal pinion is transmitted to the dial enabling the angular position of the dial to be adjusted by rotating the dial in the same direction as that in which the dial is driven by the motor. In order to facilitate dial time setting, the transmission of the movement is done with successive friction gear assemblies which are designed to allow the angular position of the dial to be adjusted by rotating the dial in the opposite direction to that in which the dial is driven by the motor.

Abstract: Apparatuses, circuits, and methods for receiving at least one radio signal in a radio controlled timing apparatus using a single timing source. The present invention advantageously eliminates the need to provide an additional timing source to receive at least one radio signal, and therefore reduces the material cost and eliminates many engineering challenges.

Abstract: An educational alarm clock radio is provided that speaks a new word each day when the alarm goes off, the words each being stored in a memory cartridge as an individual increments of information in a sequential set of increments. When the alarm goes off, the word of the day, the definition of that word of the day and its use in a sentence are spoken via the audio portion of the device as the next information increment in the sequence. The word will also be displayed on a screen so the user can see the correct spelling of the word. The word may be replayed at any time during the day by activating a device control. Prior words may be displayed by energizing a reverse control. The entire sequence of previously played words, moreover, can be played in serial fashion through further activation of control or combination of controls. The device also serves as an alarm clock radio with alarm types such as wake by buzzer or radio as well as the wake by words function.

Abstract: The disclosed system, device and method for representing time generally includes an input module, a run module, and a display module. The input module may be suitably configured to produce a user request data set in response to a user input. The run module may be suitably configured to generate a time series in response to the user request data set. The display module may be suitably configured to produce an on-screen timer in accordance with the user request data set and the time series.

Abstract: Provided is an optical near-field recording and reproduction apparatus capable of adjusting the intensity of optical near-field and the amount of light bouncing off on the bottom of a slider around a scatterer and the surface of a medium and traveling back to a light source. A reflecting layer is formed above a structure for generating an optical near-field, and multiple beam interference is caused between the reflecting layer and the surface of the medium. The amount of returning above an optical near-field generator element is adjusted by adjusting the distance between the reflecting layer and the surface of the medium.