Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.

Abstract: An internal signal test device tests a cycle of a specific internal signal by distinguishing a high level period and a low level period of the internal signal, at a wafer and package state by using an external test equipment. The internal signal test device comprises a refresh cycle generating unit, an input/output selecting control unit and an output buffer. The refresh cycle generating unit generates a refresh cycle signal having a predetermined cycle at entry of a refresh mode. The input/output selecting control unit selectively outputs the refresh cycle signal and a data signal in response to a test mode signal. The output control unit outputs an output signal from the input/output selecting control unit to an external output pin in response to an output clock signal controlled by the test mode signal.

Abstract: A macro block MB2 including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB1 at a clock frequency CF1. A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CF2 that is lower than the frequency CF1, and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CF3 that is lower than the frequency CF1. After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF2, it outputs the stored transmission data signal to the MB2 at the frequency CF1. After the reception buffer RXB has stored the reception data signal from the MB2 at the frequency CF1, it outputs the stored reception data signal to the terminal TPO at the frequency CF3.

Abstract: An integrated circuit having a plurality of processing stages includes a low power mode controller operable to control the integrated circuit to switch between an operational mode and a standby mode. At least one of the processing stages has a non-delayed latch to capture a non-delayed value of an output signal from that processing stage and a delayed latch operable during the operational mode to capture a delayed value of the same signal. A difference between these two captured signals is indicative of the processing operation not being completed at the time the non-delayed signal was captured. The delayed latch is operable during the standby mode to retain the signal it captured whilst the non-delayed latch is powered down and loses its value. The delayed latch is formed to have a lower power consumption than the non-delayed latch.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.

Abstract: A method and an apparatus for requesting packet redelivery in a mobile ad hoc network environment. The method includes receiving a first packet periodically broadcasted, extracting packet delivery information of a second packet from the first packet, the second packet including data generated by an application program, determining loss of the second packet based on the packet delivery information, and broadcasting a request packet to request redelivery of the second packet, when it is determined that the second packet is lost.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the outer parity is scattered with respect to each of the sectors of the data block to be interleaved.

Abstract: A method for recording data on an optical medium and the associated optical medium (e.g. DVD), player, and playback method. The recording method includes receiving main data from a data source, determining a plurality of data frame values in response to the main data, inverting at least one selected bit in at least one of the data frame values compared to the standard DVD format to generate a plurality of encoded data frames, scrambling the encoded data frames by a feedback shift register to generate scrambled data frames, generating ECC values in response to the scrambled data frames, adding the ECC values to the scrambled data frames to generate an ECC block, rearranging the ECC block to generate a plurality of recording frames, encoding the recording frames by an eight-to-sixteen modulation (ESM) encoder to generate code words, adding sync values to the code words to generate a plurality of physical sectors, and recording the physical sectors on the optical medium.

Abstract: A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.

Abstract: Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.

Abstract: A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi of Y and a test pattern Zi of one or more test patterns, wherein if the hard decoding is successful a codeword produced by the hard decoding of Xi is added to a set S, removing redundant codewords in S to form a reduced set S? based on processing a number of errors found during the hard decoding and a guaranteed error correcting capability of the block code decode, and an extrinsic value estimator generating n soft outputs based on c estimated soft output values and (n-c) non-estimated soft output values wherein the c estimated soft output values are computed from one or more positions of soft input vector and one or more codewords in S?.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: Methods and apparatus, including computer program products, to process an electronic document that includes a non-coded representation of characters of text. Based on text coding information that identifies the characters of the non-coded representation, a coded representation is generated and associated with the non-coded representation. In the coded representation, each identified character has a code value. Each code value is associated with a glyph that has no semantic relation with the identified character. A visual representation of the non-coded representation can be displayed, and the coded representation can be used to identify or search characters in the visual representation.

Abstract: A method and system is provided for detecting, commanding and controlling diverse home devices currently connected to a home network. An interface is provided for accessing the home devices that are currently connected to a home network. According to the method, a device link file is generated, wherein the device link file identifies home devices that are currently connected to the home network. A device link page is created, wherein the device link page contains a device button that is associated with each home device that is identified in the device link file. A hyper-text link is associated with each device button, wherein the hyper-text link provides a link to an HTML page that is contained on the home device that is associated with the device button, and the device link page is displayed on a browser based home device.

Abstract: A computer-implemented method and computer-readable medium are provided for providing page and table layout services. According to the method, a layout manager program provides layout services to client application programs. The layout manager receives requests from client application programs to format document content. In response to such requests, the layout manager performs one or more callback operations to the client application to retrieve portions of the document to be laid out. Once the portions of the page to be laid out have been retrieved through the callback operations, the layout manager lays out the portions of the document and notifies the client application that the layout is completed. The client application can then query the layout manager for the formatting result.

Abstract: The invention comprises a graphic designation method for visually differentiating each number individually for a set of telephone numbers within a printed telephone directory. In a particular instance, the invention is applied in cases in which each said telephone number in the set has been established as a link element for linking to online digital resources associated with said telephone number. The invention also teaches a method for establishing a printed telephone number directory simultaneously as a directory for a telephone number directory service. The invention also teaches a method for displaying instructions for Internet addressing within a printed directory.

Abstract: Method and apparatus for removing lines of extraneous text from a document. Similarities are identified between lines of text on each page and corresponding lines on a selected subset of pages. Different weight values are associated with different line numbers of text on a page, each weight value indicating a degree of likelihood that a line of text contains extraneous text. One or more lines of text are selectively removed from a page as a function of the similarities and associated weight values of line numbers of the lines of text.

Abstract: Systems and methods for displaying network node ports and related information in a network topology display. The user is able to clearly view ports of a connection device in the network and to view additional port information, such as the port type and the port number, for connected and unconnected ports of a network connection device. In addition, the user is able to toggle between a “show ports” mode and a “hide ports” mode for each connection device to view detailed information about the connection device ports or to hide the information in order to simplify the display.

Abstract: A system and method that centrally manages desktop packages is provided allowing the administrator to recover component files previously sent to servers located throughout the organization. Applications are assigned to users and workstations. Self-contained desktop packages are transmitted to servers. The servers, in turn, provide the desktop packages to clients. The packages and the components included in the packages include unique identifiers used to identify the packages and components. A manifest is maintained detailing the individual components included in each of the self-contained desktop files. When a disaster event occurs at the administrator's computer system, the administrator retrieves the self-contained desktop files from the servers to which the packages were previously transmitted. The administrator repopulates the component libraries by unpacking the components from the self-contained desktop files.

Abstract: A control system for a personal mobility vehicle has a menu structure that can be ordered so that commonly used areas of the menu are grouped together, thus avoiding the need to frequently navigate through seldom-used portions of a standard menu structure.

Abstract: Data about a transaction is accessed. The transaction has a set of components. A graphical representation of the components of the transaction is displayed such that the graphical representation includes a time axis and a call stack position axis. In one embodiment, the time axis depicts time left to right and the call stack position axis depicts call stack position top to bottom. Additionally, the user interface can receive a selection of one of the components, access data for the selected component and display additional details about that selected component.

Abstract: A graphical element selection program facilitates the selection of a concave portion of a model, by introducing a water source model with which an image of water flowing down from a water source can be conjured and selecting the concave portion in which the water is accumulated from the model.

Abstract: A system, method and program product for presenting and selecting an active region of a physical document page. A transparent electro-luminescent tablet or touch sensitive plate positioned over the physical document page is coupled and identified to the workstation. The workstation stores information defining an active region for the physical document page and a hyperlink to a web page. The workstation directs the tablet or plate to display the active region over the physical document page. A user touches a point within the active region. In response, the tablet or plate conveys the touch point to the workstation which displays on a computer screen the hyperlink. The active region can be identified by an outline that encompasses the active region and can encompass another such active region, so that touching a point within the inner active region elicits display of hyperlinks or documents related to both active regions.

Abstract: Methods, systems and computer program products are configured to display graphical objects on an electronic display by providing a tether that visually relates two spaced apart graphic objects on the display, with the tether configured to be less visually prominent than the objects that it indicates are related.

Abstract: Content is transferred from one computer resource to another computer resource by receiving a first insertion point or replacement area from a first user interface to a destination computer resource, receiving an enablement to perform automatic paste operation, switching to a user interface to a source computer resource, receiving a user selection of content from said source user interface, and automatically copying the selected content to a transfer buffer and to the designated insertion point(s) in the destination computer resource. Additional content may be copied to the destination computer resource by simply selecting additional content in the same source computer resource or other computer resources without need to toggle back to the destination user interface between every copy and paste operation.

Abstract: A computer system includes a display and a processor. The processor operable to implement a user interface on the display. The user interface including a plurality of program controls for initiating processing tasks. The processor is operable to, responsive to an activation of a selected program control, place an I/O control associated with the selected program control proximate the selected program control to allow visual association between the I/O control and the selected program control.

Abstract: A method and mechanism for enforcing a one-submission-only policy for a graphical button is provided. The method provides a button object defined to be enabled for only one submission action upon the button object. When a first submission action upon the button object is detected, the action associated with the button object is executed. When another submission action upon the button object is detected, the other submission action is discarded without executing the associated action. Subsequent submission actions are similarly ignored until the button object is re-instantiated to restore its functionality. In this manner, the one-submission-only behavior is embedded into the button object itself, without reliance on external mechanisms.

Abstract: The preferred embodiments described herein provide methods for identifying cells in a path in a flowchart and for synchronizing graphical and textual views of a flowchart. In one preferred embodiment, a method for identifying cells in a path in a flowchart is provided comprising the acts of displaying a flowchart comprising a plurality of cells, selecting a cell in the flowchart, determining a path comprising the selected cell, and identifying at least some of the cells in the path. In another preferred embodiment, a method for synchronizing graphical and textual views of a flowchart is provided. This method comprises the acts of displaying a graphical view of a flowchart comprising a plurality of cells in a first display region, displaying a textual view of at least some cells in the flowchart in a second display region, and in response to input received in either the first or second display regions, applying the input to both the first and second display regions.

Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

Abstract: An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.

Abstract: Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

Abstract: Disclosed are apparatus and methods for obtaining and analyzing various unique metrics or “target diagnostics” from one or more semiconductor overlay targets. In one embodiment, an overlay target is measured to obtain one or both of two specific types of target diagnostic information, systematic error metrics and/or random noise metrics. The systematic error metrics generally quantify asymmetries of the overlay target, while the random noise metrics quantify and/or qualify the spatial noise that is proximate to or associated with the overlay target.

Abstract: Processes for formal verification of circuits and other finite-state systems are disclosed. For one embodiment, a process is disclosed to provide for significantly reduced computation through automated symbolic indexing of a property assertion and to compute the satisfiability of the property assertion directly from a symbolic simulation of the indexed property assertion. For an alternative embodiment a process using indexed property assertions on a symbolic lattice domain to represent and verify properties, provides an efficient symbolic manipulation technique using binary decision diagrams (BDDs). Methods for computing symbolic simulations, and verifying satisfiability may be applicable with respect to property assertions that are symbolically indexed under specific disclosed conditions.

Abstract: A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout is examined for the presence of layout errors with the aid of predetermined design rules, identical layout errors are combined in a respective error class, and all layout errors of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error of the respective error class that is used as an error representative has been performed.

Abstract: A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit parameter values. This delay equation calculates the delay for any value in the circuit parameter range. Similar methodology is used to model simultaneous variation of two circuit parameters. The cell is characterized at just six circuit parameter pairs to interpolate the delay equation for any circuit parameter pair in the characterized ranges. This methodology can be extended to accommodate variation of multiple circuit parameters using similar interpolation techniques.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: A computer-readable medium is encoded with a computer program for directing a computer to convert a first bitstream operable to configure, for example, an earlier-generation PLD to a second bitstream operable to configure, for example, a later-generation PLD, wherein functionality is preserved from one PLD to another. The computer divides each PLD into similar regions, and replicates a function of each region of the first PLD in a corresponding region of the second PLD. The computer interconnects the regions of the second PLD to replicate the interconnections of the regions of the first PLD. The computer allows a user to manipulate the connection scheme of the second PLD.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.

Abstract: Simulated aerial images for an optical system are made by forming a reference aerial image of a first mask used in connection with the optical system, and then capturing and processing the reference aerial image to generate a set of expansion functions representative of the optical system. The expansion functions account for aberrations and misalignment of the optical system, as well as any aberrations or other defects of a camera therein. The expansion functions are then used to compute simulated aerial images of other masks projected by the optical system. Thus, the expansion functions implicitly represent a calibration of the optical system for purposes of aerial image simulation, obviating the need for direct measurement of the actual aberrations and misalignment. Hence, a simulated aerial image of a second mask for the optical system can be computed by applying the expansion functions to a design of the second mask.

Abstract: System and method is disclosed for breaking an integrated circuit design to be printed into two or more exposures by lithographic equipment, each of the two or more exposures has at least the minimum pitch. Together, these multiple exposures print an integrated circuit design that could not be printed in one exposure alone.

Abstract: A simulator tool for testing software is provided. The simulator tool includes a simulator to test the software, an interface to promote communication between the simulator and the software, a message including a component utilized by the simulator to promote testing of the software, and a test controller operable to communicate the message to the simulator, such that the message is utilized by the simulator to test the software. A method for testing software and applications is also provided.

Abstract: A method for improving program performance including reordering a global data area of a program and for each load instruction referencing global variables within range of the immediate part of an add immediate instruction from a TOC anchor, replacing the load instruction with an add immediate instruction. The method may further include placing a TOC at the top, or within a predetermined distance from the top, of the global data area. The method may also include placing the global variables after the TOC, wherein more frequently referenced global variable are closer to the TOC than less frequently referenced global variables. Also, the method may further include placing in run-time order, groups of the global variables that frequently follow each other in run-time.

Abstract: A method and system for overriding selected ROM code functions or adding new ROM code functions within a processing system. A system designer determines an existing ROM address for the selected existing code function or a desired ROM address for the new code function. The system designer then programs a patch to replace the selected existing code function or programs a new code function. The patch or new code function is then loaded into a first memory. A loader module is also programmed and loaded into the first memory. Upon system boot-up, the loader module transfers any patches or new code functions within the first memory into a second memory that is memory-mapped to the ROM. This second memory can be accessed by the processor at a faster rate than the processor can access ROM. During a processor request cycle, the processor first examines the second memory for the presence of a desired ROM code function.

Abstract: Updating component-based software product with files stored in a service package. The service package also includes a plurality of instruction sets each corresponding to a state or operating context of a component in the software product. A component installer determines the state of the component and applies the instruction set corresponding to the determined state to install the files.