Abstract: EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell strings, segments, and arrays. These memory cell architectures allow for improved high density memory devices or arrays with integral select gates that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.

Abstract: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

Abstract: To refine a semiconductor device (100), in particular a S[ilicon]O[n]I[nsulator] device, comprising: at least one isolating layer (10) made of a dielectric material; at least one silicon substrate (20) arranged on said isolating layer (10); at least one component (30) integrated in the silicon substrate (20), which component has at least one slightly doped zone (34); as well as at least a first, in particular planar, metallization region (40) arranged between the isolating layer (10) and the component (30), in particular between the isolating layer (10) and the slightly doped zone (34) of the component (30), as well as a method of manufacturing at least one semiconductor device (100) in such a manner that trouble-free operation also of slightly doped components (30), such as pnp transistors, is guaranteed in a SOI process transferred onto the insulator, it is proposed that at least a second, in particular planar, metallization region (42) is arranged on the side of the silicon substrate (20) facing away fr

Abstract: A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed on the insulative layer.

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: The invention concerns a magnetic memory, whereof each memory point consists of a magnetic tunnel junction (60), comprising: a magnetic layer, called trapped layer (61), whereof the magnetization is rigid; a magnetic layer, called free layer (63), whereof the magnetization may be inverse; and insulating layer (62), interposed between the free layer (73) and the trapped layer (71) and respectively in contact with said two layers. The free layer (63) is made with an amorphous or nanocrytallized alloy based on rare earth or a transition metal, the magnetic order of said alloy being of the ferromagnetic type, said free layer having a substantially planar magnetization.

Abstract: A dye-sensitized solar cell with high conversion efficiency is provided. The dye-sensitized solar cell according to the present invention has, between an electrode (2) formed on a surface of a transparent substrate (1) and a counter electrode (6), a light-absorbing layer (3) containing light-absorbing particles carrying dye and an electrolyte layer (5), characterized in that the light-absorbing layer (3) containing light-scattering particles (4) different in size from the light-absorbing particles. In such a dye-sensitized solar cell according to the present invention, the energy of light, which passes through a light-absorbing layer in a conventional cell structure, can be strongly absorbed by the dye in the light-absorbing layer of the present invention. This will increase the conversion efficiency and output current of the dye-sensitized solar cell.

Abstract: The semiconductor device according to this invention is characterized by a package structure of a semiconductor substrate 100 equipped with a photoelectric converting portion, wherein a light-shading means 104 is arranged in an area corresponding to at least the photoelectric converting portion on the side of the rear surface of the semiconductor substrate.

Abstract: An optoelectronic component has a lens that is formed in the surface of an encapsulant surrounding a semiconductor diode element. With respect to emitters, the lens reduces internal reflection and reduces dispersion to increase overall efficiency. With respect to detectors, the lens focuses photons on the active area of the detector, increasing detector sensitivity, which allows a detector having a reduced size and reduced cost for a given application. The lens portion of the encapsulant is generally non-protruding from the surrounding portions of the encapsulant reducing contact surface pressure caused by the optoelectronic component. This non-protruding lens is particularly useful in pulse oximetry sensor applications. The lens is advantageously formed with a contoured-tip ejector pin incorporated into the encapsulant transfer mold, and the lens shape facilitates mold release.

Abstract: A dye-sensitized solar cell with high conversion efficiency is provided. The dye-sensitized solar cell according to the present invention has, between an electrode (2) formed on a surface of a transparent substrate (1) and a counter electrode (6), a light-absorbing layer (3) containing light-absorbing particles carrying dye and an electrolyte layer (5), characterized in that the light-absorbing layer (3) containing light-scattering particles (4) different in size from the light-absorbing particles. In such a dye-sensitized solar cell according to the present invention, the energy of light, which passes through a light-absorbing layer in a conventional cell structure, can be strongly absorbed by the dye in the light-absorbing layer of the present invention. This will increase the conversion efficiency and output current of the dye-sensitized solar cell.

Abstract: Embodiments of the present invention provide pixel cells with increased storage capacity, which are capable of anti-blooming operations. In an exemplary embodiment a pixel cell has an electronic shutter that transfers charge generated by a photo-conversion device to a storage node before further transferring the charge to the pixel cell's floating diffusion node. Each pixel cell also includes an anti-blooming transistor for directing excess charge out of each respective pixel cell, thus preventing blooming. Additionally, two or more pixel cells of an array may share a floating diffusion node and reset and readout circuitry.

Abstract: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that the first conductive layer is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer laminated on an upper surface of the first conductive layer; and a second conductive layer laminated on an upper surface of the dielectric layer so that the second conductive layer forms a capacitor together with the first conductive layer and the dielectric layer. Accordingly, when the integrated circuit structure is used in a rectification circuit, the size of an entire circuit can be reduced.

Abstract: The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complimentarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complimentarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.

Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Abstract: A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a plurality of dummy gate electrodes are disposed covering the respective dummy active layers. The arrangement pattern of the dummy active layers and the arrangement pattern of the dummy gate electrodes nearly match, so that the dummy gate electrodes are aligned accurately on the dummy active layers.

Abstract: A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi2) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi2. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi2. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSi2 and converts a portion of the C49 TiSi2 to C54 TiSi2. The lower resistance of the C54 TiSi2 decreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.

Abstract: A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier layer covering at least a portion of the one surface adjacent the control contact, the dielectric barrier layer having a bandgap greater than the bandgap of the Group III nitride and a conduction band offset from the conduction band of the Group III nitride; and a dielectric protective layer covering the remainder of the Group III nitride surface.

Abstract: Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing an insulating layer on the surface of the resulting structure; and forming an metallic interconnect on the insulating layer.

Abstract: The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

Abstract: Provided is a non-contact ID card which is superior in the productivity and the electrical properties, and a method capable of manufacturing such non-contact ID card. The non-contact ID card of the present invention is characterized in that the non-contact ID card comprises an antenna circuit board in which an antenna is formed on a substrate and an interposer board in which an enlarged electrode, which is connected to an electrode of an IC chip, is formed on a substrate on which the IC chip is mounted. The non-contact ID card is formed by laminating both boards in such a manner that the electrode of the antenna and the enlarged electrode are bonded, in which both electrodes are adhesively bonded by an insulating adhesive filled in minute recesses dispersed on bonding faces of the electrode of the antenna and/or the enlarged electrode.

Abstract: A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

Abstract: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

Abstract: An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the second die. The wires of first die are coupled to the bond sites for wires of the substrate. The balls of the second die are coupled to the bond sites for the array of balls of the substrate.

Abstract: A package for semiconductor light emitting element is described. The package includes a first metal substrate having a cup shaped recess portion, an insulating member having a first cup shaped opening, provided on the first metal substrate, and a second metal substrate having a second cup shaped opening, provided on the insulating member with being electrically insulated from the first metal substrate, having a cavity in the inner surface.

Abstract: A circuit device is provided comprising leads and electrical circuitry. The circuit device has a first semiconductor element, a second semiconductor element, first leads electrically connected to the first semiconductor element or the second semiconductor element via fine metal wires and having an end thereof extending outwardly, second leads electrically connected via metal wires to both the first semiconductor element and the second semiconductor element to thus electrically connect the first and second semiconductor elements.

Abstract: A semiconductor device and manufacturing the semiconductor device are described. There is provided a method of manufacturing a semiconductor device including, disposing a lead frame inside an outer lead so as to couple between a coupling portion and a coupling acceptance portion, the lead frame including a chip mounting portion and the coupling acceptance portion, the outer lead including a frame portion with outer terminal portions and the coupling portion, disposing a semiconductor chip on the chip mounting portion, connecting between the outer terminal portions and the semiconductor chip with a plurality of wires or leads, sealing the outer terminal portion, the lead frame disposed the semiconductor chip on and the wires or the leads by a mold resin, cutting off the outer terminal portions from the outer lead, and uncoupling the coupling portion from the coupling acceptance portion.

Abstract: An electronic package and method for forming such package that expands the current capability of lines and/or reducing line resistance for packages with a given feature dimension while relaxing feature tolerances. The methods and structures include electrical wirings having regions of larger wire cross-sectional areas in locations where the package must supply higher current distribution to the electronic devices and/or where signal lines need lower electrical resistance. These larger wire cross-sectional areas are vertically extended conductors applied to either the entire conductor or portions of the conductor.

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Abstract: A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements is exposed upward; a sensor which is mounted on the back surface of the circuit board; and a thin metallic wire which electrically connects the circuit board with the leads. The island, the resin sealing body, the sensor, and parts of the leads are sealed by a second sealing resin.

Abstract: A press mold for fabricating a glass substrate, the glass substrate comprising a substrate; and a terrace-shaped flat portion formed on the substrate and having a grooved portion formed therein, is characterized in that the press mold comprises a top mold and a bottom mold; at least one of the top mold and the bottom mold having an indented portion formed therein so as to correspond to the terrace-shaped flat portion, the indented portion having an entire periphery surrounded by a mold reference surface.

Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.

Abstract: A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film (102) and a copper containing metallic film (103) can be formed within an insulating film (101). An interlayer insulating film (104 or 104a and 104b) can be formed thereon. An upper layer wiring made from a barrier metal film (106 or 106a and 106b) and a copper containing metallic film (111 or 111a and 111b) is formed within the interlayer insulating film (104 or 104a and 104b). A silver containing metallic protective film (108a and 108b) can be formed on surfaces of the lower layer wiring and upper layer wiring.

Abstract: A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated therewith, with a first bond wire connected between a first one of the landing zones and a second one of the landing zones. The first bond wire forms a sense resistor with a resistance of a known value. A second bond wire is connected between the first one of the landing zones and a first one of the bond pads.

Abstract: The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided. A semiconductor device of the invention comprises a plurality of conductive layers, a plurality of first element groups each of which selects one among the conductive layers and a plurality of second element groups each of which amplifies a signal each transmitted from the conductive layers. Each of the second element groups is disposed between the first element groups. Stated another way, the first element group and the second element group are disposed alternately. The delay of the signal transmission with the plurality of conductive layers is controlled because a load by a parasitic capacitance is reduced due to the above feature.

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein.

Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

Abstract: Semiconductor devices and stacked die assemblies, are provided which have at least two semiconductor dies disposed on a substrate in a stacked arrangement, the first and second dies having first surfaces having bond pads, the second die having a second surface with a recessed edge portion along a perimeter of that die, and the recessed edge portion having a height sufficient for clearance of bonding elements extending from the first die.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.

Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

Abstract: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that comprises a principal underfill composition of a rigid octaaminophenyl silsesquioxane (OAPS) that is used as a curing agent for a tetrafunctional, low viscosity, and relatively rigid TGMX epoxy resin. An embodiment is also directed to the assembly of a flip chip package that uses the underfill mixture.