Abstract: In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

Abstract: A method for manufacturing a light-emitting diode (LED) is disclosed. In the method, a substrate is firstly provided, in which a first conductivity type cladding layer, an active layer, a second conductivity type cladding layer, a superlattice contact layer and a transparent conductive oxide layer are stacked on the substrate in sequence. Next, an etching mask layer is formed on a portion of the transparent conductive oxide layer, in which the etching mask layer is an insulator. Then, a definition step is performed by using the etching mask layer to remove an exposed portion of the transparent conductive oxide layer, and the superlattice contact layer, the second conductivity type cladding layer and the active layer under the exposed portion of the transparent conductive oxide layer until the first conductivity type cladding layer is exposed. The etching mask layer is then removed.

Abstract: A fabricating method of a flat panel display includes the steps of spreading an etch-resist on a thin film formed on a substrate, a polarity of the etch-resist changed by irradiation with a first light; providing a soft mold having a projected surface and a groove at an upper surface of the etch-resist at a distance from the substrate, the soft mold surface treated to be the same polarity as the etch-resist; performing a first and a second alignments of the soft mold and substrate; changing the polarity of the etch-resist by irradiation with the first light such that the etch-resist moves into a groove of the soft mold; forming an etch-resist pattern by irradiating a second light onto the etch-resist in the groove; separating the soft mold from the etch-resist pattern; and forming a thin film pattern by etching a portion of the thin film and the etch-resist pattern.

Abstract: A Method for manufacturing an optical disc substrate comprises a first substrate with at least one structured surface, on which an anti-adhesive layer, preferably carbon, is deposited and first layer on top of said anti-adhesive layer. On a second substrate with a structured surface also a layer is deposited. Both substrates are bonded together with the layers facing each other. The separation now easily can take place afterwards alongside the adhesive layer. This way the first layer from the first substrate is being transferred to the second substrate.

Abstract: A package structure of a light emitting diode includes a substrate structure, a connection layer, and at least one conductive passage. The substrate structure sequentially includes a conduction board, an insulation layer, and a conductive layer. The insulation layer is configured to electrically insulate the conduction board from the conductive layer, and also to insulate a first portion from a second portion of the conduction board. The substrate structure has an opening to expose the conduction board. The connection layer configured to support and electrically couple to a first electrode of a light emitting diode (LED) is disposed in the opening. The connection layer is also configured to electrically couple to the conduction board and to be electrically insulated from at least one portion of the conductive layer, which is coupled to a second electrode of the LED.

Abstract: A light-emitting device comprising a light-emitting unit including a plurality of first connecting pads, a base substrate including a plurality of second connecting pads, and a plurality of conductive bumps that connect the first connecting pads of the light-emitting unit to the second connecting pads of the base substrate. In the manufacturing process, a reflow process is performed to bond the conductive bumps to the first and second connecting pads. The light-emitting unit is configured to emit a first light radiation upon the application of an electric current flow, and the base substrate is configured to emit a second light radiation when stimulated by the first light radiation.

Abstract: A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer by using a mask having a plurality of semiconductor patterns with a second interval different from the first interval to form a semiconductor, forming both a data line including a source electrode and a drain electrode on the semiconductor and the gate insulating layer, and forming a pixel electrode coupled with the drain electrode.

Abstract: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager array. In the resulting structure, the conserved sections absorb incident light. The patterned portions of conserved material provide additional light shielding for array pixels.

Abstract: A ChemFET Sensing system is Described.

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

Abstract: Nanotube films and articles and methods of making the same. A conductive article includes an aggregate of nanotube segments which contact other nanotube segments to define a plurality of conductive pathways along the article. Segments may have different lengths and may be shorter than the article. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining within the fabric a pattern corresponding to the conductive article. The nanotube fabric may be grown on the substrate using a catalyst, such as a gas phase a metallic gas phase catalyst. The nanotube fabric may be formed by depositing a solution of suspended nanotubes on the substrate, which may be spun to create a spin-coating of the solution. The solution may be deposited by dipping the substrate into the solution. The nanotube fabric may be formed by spraying an aerosol having nanotubes onto the substrate.

Abstract: A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer.

Abstract: An implantable medical device substrate is free form cut to the shape of the interior of the device. The free form shape allows more efficient use of not only the interior space of the device but also of the substrate itself. Integrated circuit components are formed to fit the shape of the substrate, freeing areas in the device for additional components, or allowing the device to be made smaller through a maximized use of the available space-volume.

Abstract: A semiconductor device including a semiconductor device package providing a capacitor in its circuit board and a semiconductor chip mounted on that package, wherein the capacitor is provided directly under a semiconductor chip mounting surface of the circuit board on which the semiconductor chip is to be mounted and the conductor circuit electrically connecting the semiconductor chip and capacitor is made the shortest distance by having the external connection terminals of the capacitor directly connected to the other surface of the connection pads exposed at one surface at the semiconductor chip mounting surface of the circuit board and to which the electrode terminals of the semiconductor chip are to be directly connected.

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device adjacent to the first semiconductor device in superimposed relation thereto. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing or hardening, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates.

Abstract: The present invention provides a lubricant container inside a microelectromechanical device package. The lubricant container contains selected lubricant that evaporates from the container and contact to a surface of the microelectromechanical device for lubricating the surface.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Abstract: A method for manufacturing liquid crystal display substrates comprises the steps of: (a) providing a substrate having a transparent electrode layer and a metal layer; (b) forming a patterned photoresist layer through half-tone or diffraction; (c) defining signal line area and thin film diode area, or pixel area and conductive electrode-lines by etching; and (d) forming an oxidized layer on partial surface of the metal layer. The disclosure here provides a patterning process of lithography and etching with one photolithography of one single mask in the manufacturing of liquid crystal display substrates. Furthermore, the method disclosed here can effectively increase the yield of manufacturing, and reduce the cost of manufacturing.

Abstract: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the position of the semiconductor thin film irradiated with the laser beam at a predetermined velocity so that excess hydrogen can be removed from the region irradiated with the laser beam without evaporating and expanding hydrogen ions in the semiconductor thin film.

Abstract: A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the performance of a plasma treatment to adjust the threshold voltage of the low temperature polysilicon thin film transistor. Because the threshold voltage of the low temperature polysilicon thin film transistor can be adjusted through a plasma treatment, the manufacturing process is more flexible.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon layer is overlying the gate dielectric layer. A mask layer is overlying the gate polysilicon layer. The device also has a gate electrode formed within the gate polysilicon layer. The gate electrode has a first predetermined width and a first predetermined thickness. Preferably, the gate electrode has a first side and a second side formed between the first predetermined width. The gate electrode is coupled to the double diffused drain region within the well region.

Abstract: A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.

Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

Abstract: According to an exemplary embodiment, a method for integrating bipolar and CMOS devices on a substrate, where the substrate includes bipolar and CMOS regions and has a sacrificial oxide layer situated thereon, includes removing a portion of the sacrificial oxide layer in the bipolar region of the substrate to expose a top surface of the substrate. The method includes forming a base layer on the top surface of the substrate in the bipolar region. The base layer forms a bipolar transistor base. The method further includes forming a sacrificial post on the base layer in the bipolar region and at least one gate electrode in the CMOS region of the substrate. A common mask is used to form the sacrificial post and the at least one gate electrode. The method further includes forming LDD regions adjacent to the at least one gate electrode in the CMOS region.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer is etched back to form spacers on the sidewalls of the gate structure. Finally, a source/drain region is formed in the substrate on each side of the spacer-coated gate structure.

Abstract: An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The transistor further includes a gate insulating film that has a thin oxide silicon film (a thin film portion) and a LOCOS film (a thick film portion). The body region has an impurity profile in which the concentration reaches a maximum value near the surface and decreases with distance from the surface. The drain offset region has an impurity profile that has an impurity-concentration peak in a deep portion located a certain depth-extent below the lower face of the LOCOS film.

Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Abstract: A thin film non volatile memory scalable to small sizes and its fabrication process are disclosed. The thin film memory comprises a thin film transistor control circuitry fabricated on a flexible substrate, together with an optoelectronic cross bar memory comprising a photoconducting material. The thin film non volatile memory can be used in RFID communication tag with the control circuitry further comprises wireless communication circuitry such as an antenna, a receiver, and a transmitter.

Abstract: A method of forming a conductor on a substrate including steps of depositing tantalum on a glass layer of the substrate; oxidizing the tantalum; and depositing a noble metal on the oxidized tantalum to form the conductor. The method can be used to form a ferroelectric capacitor or other thin film ferroelectric device. The device can include a substrate comprising a glass layer; and an electrode connected to the glass layer. The electrode comprising can include a noble metal connected to the glass layer by an adhesion layer comprising Ta2O5.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming a sacrificial layer over the substrate and filling the first trench, etching the sacrificial layer to have a portion of the sacrificial layer remain in the first trench in the BLC region of the substrate, forming a second trench extending horizontally by etching the substrate underneath the first trench, and filling the first and second trenches to form an isolation structure.

Abstract: A buried-contact solar cell, in-process buried-contact solar cell components and methods for making buried contact solar cells wherein a self-doping contact material is placed in a plurality of buried-contact surface grooves. By combining groove doping and metallization steps, the resulting solar cell is simpler and more economical to manufacture.

Abstract: The present invention provides a manufacturing method of a semiconductor device having a semiconductor nonvolatile memory element that is highly reliable and that can increase a variation of a threshold voltage. Further, the present invention provides a method for manufacturing a semiconductor device having a highly reliable semiconductor nonvolatile memory element using a large substrate. According to the present invention, sputtering using, as a target, a solid solution containing silicon that exceeds a solid solubility limit is conducted, so that a conductive film including a conductive layer of a metal element that is a main component of the solid solution and silicon particles is formed, and then, the conductive layer of the metal element is removed to expose silicon particles. Furthermore, a semiconductor device having a semiconductor nonvolatile memory element using the silicon particles as a floating gate electrode is manufactured.

Abstract: A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

Abstract: A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the cell region and forming selection gates on the semiconductor substrate of the select transistor region; forming an oxide film on the entire structure and then forming a nitride film; etching the nitride film so that the nitride film remains only between the selection gates and adjacent edge cell gates; and, blanket etching the oxide film to form spacers on sidewalls of the selection gates. Accordingly, uniform threshold voltage distributions can be secured, and process margins for a spacer etch target can be secured when etching the spacers. Furthermore, the nitride film partially remains between the edge cell gates and the selection gates even after the gate spacers are etched.

Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

Abstract: A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first polysilicon layer is formed on the second oxide layer and the exposed portion of the nitride layer. The first polysilicon layer and the nitride layer are etched so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer. The polysilicon spacers are etched so as to expose portions of the nitride layer. The exposed portions of the nitride layer may function as charge trapping layers. The exposed portion of the first oxide layer is etched to expose a portion of the substrate. A third oxide layer is formed on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer. A second polysilicon layer is formed on the third oxide layer.

Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

Abstract: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

Abstract: A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined thickness by using the moat pattern, forming a trench isolation layer by depositing a trench filling material on an entire surface of the substrate including the trench by using a high density plasma (HDP) process, partially masking a center region of the substrate and etching the trench isolation layer on edge regions of the substrate to a predetermined thickness, and planarizing the entire surface of the substrate having the trench isolation layer etched.

Abstract: A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the second conductivity type in the second layer proximate the upper surface of the second layer, the first source/drain region being spaced laterally from the second source/drain region, the gate being formed at least partially between the first and second source/drain regions; and forming at least one electrically conductive trench in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate.

Abstract: A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the drain region free from the dopant impurities.

Abstract: Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to form an auxiliary pattern; depositing a polysilicon layer; dry etching the polysilicon layer to form a side wall of the polysilicon layer to adjacent the auxiliary pattern; removing the auxiliary pattern; depositing an insulating layer; chemical mechanical polishing to remove a predetermined thickness of the side wall and the insulating layer to thereby complete the gate electrode from the side wall; and removing the insulating layer.