Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.

Abstract: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.

Abstract: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract: A cap wafer, fabrication method, and a semiconductor chip are provided. The cap wafer includes a cap wafer substrate; a penetrated electrode formed to penetrate the cap wafer substrate; and an electrode pad connected with a lower portion of the penetrated electrode on a lower surface of the cap wafer substrate, wherein the penetrated electrode has an oblique section which gradually widens from an upper surface to the lower surface of the cap wafer substrate. The fabrication method includes forming an oblique-via hole on a lower surface of a cap wafer substrate, the oblique-via hole having an oblique section which gradually narrows in a direction moving away from the lower surface of the cap wafer substrate; and forming a penetrated electrode in the oblique-via hole. The semiconductor chip includes a base wafer; a cap wafer; a cavity; a penetrated electrode; and a pad bonding layer.

Abstract: In one embodiment, the invention may include a semiconductor package substrate with a plated-through hole (PTH) via. One or more conduits for transmitting signals can be located in the PTH via. The PTH via may shield the signals in the conduits from environmental noise (e.g., EMI). Other embodiments are described and claimed.

Abstract: A circuit board structure having an embedded semiconductor chip and a method for fabricating the same are disclosed. The circuit board structure includes: a carrier board formed with at least one through hole; a semiconductor chip received in the through hole of the carrier board, the semiconductor chip having an active surface and a non-active surface, wherein the active surface is provided with a plurality of electrode pads; a dielectric layer formed on surfaces of the carrier board and the semiconductor chip and formed with a plurality of openings for exposing the electrode pads of the semiconductor chip; and a composite circuit layer formed on the dielectric layer, including a thinned metal layer, conductive layer, and electroplated metal layer, and electrically connected to the electrode pads by conductive structures formed in the openings of the dielectric layer.

Abstract: The invention relates to a semiconductor device (1) comprising a semiconductor chip stack (2) and a plastic housing (3), and to methods for producing the semiconductor device (1). The semiconductor device (1) is constructed on a device carrier (4), on which a first semiconductor chip (5) is fixed by its rear side (6). At least one second semiconductor chip (8) is adhesively bonded by its rear side (9) on the top side (7) of the first semiconductor chip (5) by means of an adhesive layer (10). A second plastic composition (17) is arranged between a first plastic housing composition (11) of the plastic housing (3) and the edge sides (12, 13) of the adhesive layer and the edge sides (14, 15) of the second semiconductor chip (8) and also the top side (16) of the second semiconductor chip (8) in such a way that the first plastic housing composition (11) has no physical contact with the second semiconductor chip (8) and with the adhesive layer (10).

Abstract: A microelectronic package includes a substrate (110), a die (120) electrically connected to the substrate, and a heat dissipation device (130) coupled to the die. The heat dissipation device includes a capacitor (250, 310). In one embodiment the heat dissipation device is a microchannel having a base (131) and a cover plate (132, 300) over the base, and the capacitor is located within the cover plate.

Abstract: Disclosed are various embodiments of systems, devices and methods for controlling the thickness of a thermal interface layer in a semiconductor die package. In one embodiment, spherical inclusions of at least a first substantially uniform diameter are suspended in a thermal material, which is then dispensed or metered onto the top surface of a semiconductor die. A heat spreading lid is then placed atop the metered or dispensed mixture of thermal material and spherical inclusions, and a mechanical load applied thereto. The load squeezes the thermal material between the lid and the die until the spherical inclusions of the first diameter form a layer of like-diameter spheres having upper and lower portions which contact the lower surface of the lid and the upper surface of the die, respectively.

Abstract: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.

Abstract: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film. Then, an In alloy film is formed from the In alloy pellet by heating, melting, and then cooling the In alloy pellet. As a result, the semiconductor chip and a heat spreader are bonded via the metal film and the In alloy film.

Abstract: A semiconductor device with a structure having superior heat sink characteristics. A first heat sink member is located over a wiring board by using an adhesive material. A semiconductor element is stuck over the first heat sink member by using an adhesive material. The semiconductor element and electrodes located over the wiring board are connected by wires. A second heat sink member which covers the semiconductor element and the wires is joined to the first heat sink member by using a conductive adhesive material. The inside and outside of the second heat sink member are sealed by resin except a flat top thereof. By doing so, the semiconductor device is fabricated. Heat which is generated in the semiconductor element and which is transmitted to the first heat sink member is released from an edge portion of the first heat sink member.

Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.

Abstract: The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process. The first block dices are electrically connected to the second block dices. The first block dices and the second block dices are packaged into a system.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract: Semiconductor devices are provided including a semiconductor substrate and a first interlayer insulating layer on the semiconductor substrate. A contact pad is provided in the first interlayer insulating layer and a second insulating layer is provided on the first interlayer insulating layer. A contact hole is provided in the second interlayer insulating layer. The contact hole exposes the contact pad and a lower portion of the contact hole has a protrusion exposing the contact pad. The protrusion is provided on the second interlayer insulating layer. A contact spacer is provided on inside sidewalls of the contact hole and fills the protrusion. A contact plug is provided in the contact hole. Related methods are also provided herein.

Abstract: A semiconductor device has interconnects protected with an alloy film having a minimum thickness necessary for producing the effect of preventing diffusion of oxygen, copper, etc., formed more uniformly over an entire surface of a substrate with less dependency to the interconnect pattern of the substrate. The semiconductor device includes, embedded interconnects, formed by filling an interconnect material into interconnect recesses formed in an electric insulator on a substrate, and an alloy film, containing 1 to 9 atomic % of tungsten or molybdenum and 3 to 12 atomic % of phosphorus or boron, formed by electroless plating on at least part of the embedded interconnects.

Abstract: A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat

Abstract: An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel. The dielectric layer is disposed on the substrate. The carbon nanotube is disposed in the dielectric layer to electrically connect with the conductive barrier layer.

Abstract: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between the substrate and the second metal structure, so as to contact the second metal structure, the second metal structure being harder than the first metal structure.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.

Abstract: A semiconductor device manufacturing method includes forming a conductive layer pattern on a semiconductor substrate, forming a seed layer having a high silicon content ratio on the conductive layer pattern, and forming an interlayer dielectric to bury the conductive layer pattern on the seed layer.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.

Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.

Abstract: An integrated circuit semiconductor device comprises a substrate, a deep via within the substrate, a metal fill located within the deep via and defining an upper surface, and an interconnect wiring. The contact area electrically connects the metal fill to the interconnect wiring, the contact area being located laterally of the deep via such that the contact area does not contact the upper surface of the metal fill.

Abstract: A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on.

Abstract: A transistor structure and a control unit comprising the same transistor structure for use with the drive circuit of a liquid crystal display (LCD) are provided. The transistor structure comprises a first conductive layer, a second conductive layer, and a top gate to form a reinforced capacitance thereamong, thereby, significantly releasing the burden of the circuit layout due to the extra capacitance devices. That is, the capability of the capacitance can be improved without providing additional devices.

Abstract: A semiconductor device includes contact pads formed in a first interlayer insulating layer on a semiconductor substrate, contact pad protecting patterns covering edges of a surface of the contact pads, and conductive lines positioned on a second interlayer insulating layer covering the contact pad protecting patterns and selectively connected to the contact pads.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

Abstract: Disclosed a multi-chip module with solder corrosion prevention including one or more chips connected to a substrate by soldering, the substrate disposed on a printed circuit board. The multi-chip module also includes a quantity of molecular sieve desiccant, and a first cover to contain the one or more chips, the substrate, and the molecular sieve desiccant, the first cover having a seal to the printed circuit board.

Abstract: An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead tip and a lead body, forming a recess in the lead body from a lead body top surface, connecting an integrated circuit die and the external interconnect, and molding the external interconnect with the recess filled.

Abstract: With a semiconductor apparatus package of the present invention and a method of producing the semiconductor apparatus package, the semiconductor apparatus package includes a circuit board and a semiconductor device sealed with sealing resin. The circuit board has a groove in a section of a surface of the circuit board. The section is outside of the resin sealing section, and the surface includes the resin sealing section. The groove is at least partially filled with sealing resin having seeped from a resin sealing section. Thus, in the semiconductor apparatus package including the circuit board, which is exposed from the resin sealing section, and the semiconductor device sealed on the circuit board with the sealing resin, the spread of a thin resin film onto that exposed circuit board resulting from seepage of resin sealing the semiconductor device is prevented.

Abstract: A humidifier of the present invention includes a bundle of hollow porous tubes made of synthetic material disposed in a housing having a plurality of inlet and outlet ports. The humidifier of the present invention is used to control humidity in a fuel cell and is used in various industrial applications. A method of producing the humidifier is disclosed herein.

Abstract: Processes for obtaining an impact resistant, abrasion and/or scratch resistant photochromic article comprising a substrate having two main faces, comprising: preparing a curable coating composition comprising at least one unblocked polyisocyanate terminated polyurethane pre-polymer, at least one polyol, and at least one photochromic agent; depositing the curable coating composition onto at least part of a main face of the substrate; curing the coating composition for 10 minutes or less, at a temperature lower than or equal to 100° C. to form an impact resistant photochromic coating; forming an abrasion and/or scratch resistant coating on the impact resistant photochromic coating or forming a protective coating on the impact resistant photochromic coating and then forming an abrasion and/or scratch resistant coating on said protective coating. Articles obtainable by such processes, including but not limited to ophthalmic lenses. Curable coating compositions involved in such processes.

Abstract: Contact lens molds and methods of producing soft cast-molded contact lens products are provided. The methods include placing a soft hydrophilic contact lens-forming composition in a cavity formed between a first mold member and a second mold member, subjecting the composition in the cavity to conditions effective to form a contact lens product from the composition, and repeating the placing and subjecting steps a plurality of times, thereby producing a plurality of soft contact lens products. At least the first mold members, and advantageously all of the first and second mold members, are injection-molded with a nucleated thermoplastic polyolefin resin having a melt flow rate in a range of 10 g/10 min to about 40 g/10 min.

Abstract: The present invention provides a plastic lens which can simplify the installation, can enhance the forming accuracy and can exhibit extremely small optical irregularities. Molds having a planned combination are heated, using at least one pre-numerically controlled automatic chucking transport device and/or manually, the molds are constituted to be sequentially overlapped in accordance with the combination. First of all, an optical thermoplastic resin molten material having an extremely small agitation flow is placed on a forming surface of one lower mold. Subsequently, a forming surface of another upper mold is brought into contact with the resin molten material by inclining the posture of the upper mold, and both molds are made to approach each other to define a given distance therebetween so as to form a lens by pressing the resin molten material.

Abstract: The micro-molding equipment contains a preform molding equipment 10 taking a single-cavity of a preform material 3 corresponding to a small precision optical component to be molded with a runnerless mold, and a precision compression molding equipment 40 for after molding the preform material 3 by primary compression molding in a vacuum state, cooling the preform material to a temperature near a glass transition point, and then re-softening a surface layer of the preform material and molding the same by secondary compression molding to transfer the small precision optical component thereto.

Abstract: Within a cotton candy machine a delay-on-break delay timer is used to delay the de-energization of the spinner-head motor for a predetermined period of time after the heater elements are turned off. Thus, while the heater elements are cooling down, the motor and spinner head continue to rotate. Once the heater elements are cooled to the point where they cannot melt or burn the sugar, then the motor can be de-energized and the spinner head allowed to stop.

Abstract: A user-fabricated mouth guard wherein the user's teeth and gums are not directly exposed to the uncured mouth guard material. The uncured mouth guard material is pliant at room temperature and does not have to be heated to form and shape the mouth guard. The cured mouth guard call be pliant or rigid at room temperature. A kit and a method of forming the mouth guard are also disclosed.

Abstract: In a method for producing molding elements having a predetermined thickness profile, in which a filling tool of a filling device is filled with a molding material and the molding material is released in the direction of gravity from the filling tool into a pressing mold of a press, the molding material is held in the filling tool by means of suction, and its release into the pressing mold is effected by a reduction, particularly a deactivation, of the suction force.

Abstract: [Problem] Proper cooling of a molten sheet product by bringing the sheet into close contact with a movable cooling member, by properly charging over the whole width of the molten sheet product extruded on the movable cooling member. [Solving Means] A sheet production apparatus comprising an extruder 3 to extrude a thermoplastic resin having a melt specific resistance value of not less than 0.

Abstract: An expandable polystyrene composition in the form of beads is disclosed, comprising: (1) 100 parts by weight of a styrene polymer having in particular a weight-average molecular weight Mw ranging from 150 000 to 400 000 daltons, (2) from 3 to 20 parts by weight of a blowing agent, which is water or a mixture of water with at least one other blowing agent for example a hydrocarbon (3) from 0.1 to 12 parts by weight of at least one modified clay with an at least partially lipophilic nature. Also disclosed is a process for making the compositions.

Abstract: The present invention relates to an apparatus and process for injection molding polymer articles that reduces deposition of additives on the apparatus. Specifically, pressurizing of the mold cavity with a pressurized gas reduces the deposition of low molecular weight additives on the apparatus. Embodiments of the invention also include an apparatus for injection molding polymer articles comprising at least one pressurized gas inlet for introducing a pressurized gas into the mold cavity.