Abstract: An interface apparatus and a method of updating data for non-volatile memory are provided. The interface apparatus of the present invention is suitable for an embedded system having a universal-serial-bus (USB) interface and a non-volatile memory. The interface apparatus employs a command translator to directly translate the specific form command commanded by an external device, so that, the interface apparatus may well directly initialize and read/write data from/to the non-volatile memory of the embedded system, without being processed by the microprocessor inside the embedded system.

Abstract: By utilizing a cache memory's high-speed data access feature of a processor in an embedded system, when a data reading action and a data writing/erasing action occur in a same partition (read while write/erase, RWW/E in the same partition) of a NOR flash memory, the processor intentionally generates an instruction cache miss in the cache memory, and the processor loads the data to be read into the cache memory. The data loaded into the cache memory is read and the data in the partition to be written/erased is written/erased at the same time.

Abstract: A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

Abstract: A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

Abstract: A data storage device detachably connected to a host device, the data storage device including: a memory having a logical space composed of at least one logical unit; a logical space managing table for managing the logical space; and a controlling section configured to control a managing operation of the logical space managing table, and when the host device makes a request to divide the logical space, searching the logical space for unused logical blocks, dividing a logical space composed of the unused logical blocks from the logical space, and performing control to manage a plurality of the obtained logical spaces as different logical units, respectively.

Abstract: This magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. Said layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of said layers. Said layer of non-magnetic material is capable of inducing an antiferromagnetic coupling field between said layers made of a magnetic material, the direction and amplitude of this field making it possible to attenuate the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between said magnetic layers.

Abstract: A controller of an automated data storage library is configured to store information regarding operation of the library in a memory; to reserve at least one data storage cartridge; and to operate a data storage drive and the memory to transfer at least a portion of the information stored in the memory to the reserved data storage cartridge. The library controller is configured to maintain an externally available inventory of data storage cartridges of the library, e.g. for a host system, and excludes the reserved data storage cartridge from the inventory.

Abstract: A method, system, and computer program product forcost based analysis for data access in a database management system. In one approach, the method, system, and computer program productperforms identifying data to access, determining a first cost for direct I/O storage access and a second cost for cache access, performing a comparison between the first cost and the second cost, and accessing a first portion of identified data based upon the comparison.

Abstract: A desired cache size in a disk drive is established, and no reordering algorithm is performed on commands in the cache until the desired size is reached. An optimal subset size is also established. Then, an optimization algorithm is performed on all commands in the cache, with only the commands in the optimal subset being output for execution. The cache is refilled to the desired size, and the process is repeated.

Abstract: The present invention is a system for implementing a meta-disk aggregation model for storage controllers. The system includes a storage controller configured for communicatively coupling with a server. The system further includes a meta-disk drive group having a plurality of disk drives, the meta-disk drive group configured for being communicatively coupled with the storage controller, each of the plurality of disk drives including a drive interface connector. Additionally, each drive interface connector of the plurality of disk drives of the meta-disk drive group is configured for being communicatively coupled to each of the remaining drive interface connectors of the plurality of disk drives, thereby allowing the plurality of disk drives to communicate as a single device with the storage controller.

Abstract: A method for protecting private content stored in a portable memory device are provided, wherein the portable memory device comprises a micro-controller unit, a USB connector, a memory array, a decoder, a storage for storing various application programs, and a backup power supply, characterized in that the method comprises steps of generating a protection signal in response to an initiating action and transmitting the signal to the micro-controller unit; recoverably deleting original file systems from the memory array USB the micro-controller unit in response to the received protection signal, and storing the original file system into the storage as a backup for the recovery purpose.

Abstract: A method, system, and computer program product is disclosed for caching results in a client-side cache. Embodiments of a method, a system, and a computer program product are disclosed that associate a first snapshot of a database with a client that indicates a state of the database after a last database request by the client, and indicate any number of invalid cached results in the client cache for the client based upon the first snapshot. In some embodiments, the method further includes receiving a second snapshot that indicates a state of the database upon receipt of a database server request by the client, and updating the first snapshot with the second snapshot.

Abstract: One embodiment of the present invention is a cache memory arranged between a processor and a low-speed memory and performing a pipeline processing of a memory access made by the processor. In a first stage, the cache memory reads out a tag address from a tag memory. In a second stage, the cache memory performs a hit decision by a hit decision unit. When the hit decision result is a miss hit, the cache memory performs an update control of the tag memory and a behavior control of a bypass circuit for supplying a data held in a latch circuit to the hit decision unit by bypassing the tag memory in a third stage. The latch circuit is configured to hold a tag address included in a input address supplied from the processor.

Abstract: A method, system, and program for decoding cached compressed data. Compressed data is received and decoded. An error is detected while decoding a first location in the compressed data. A reentry data set is accessed having a pointer to a second location in the compressed data following the first location and decoding information that enables decoding to start from the second location. The second location in the compressed data is accessed and the decoding information in the accessed reentry data set is used to continue decoding the compressed data from the second location.

Abstract: A method and apparatus implement memory accesses to a memory using an open page mode with data prefetching. A central processor unit issues memory commands. A memory controller receiving the memory commands, identifies a data prefetching command. The memory controller checks whether a next sequential line for the identified prefetch command is within the page currently being accessed, and responsive to identifying the next sequential line being within the current page, the current command is processed and the current page left open.

Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

Abstract: A computing system is provided which includes a number of processing units, and a switching system coupled with each of the processing units. The switching system includes a memory. Each of the processing units is configured to access data from another of the processing units through the switching system. The switching system is configured to store a copy of the data passing therethrough into the memory as the data passes between the processing units though the switching system. Each of the processing units is also configured to access the copy of the data in the memory of the switching system.

Abstract: Methods and apparatus are provided for a linker to resolve references from shared memory to private memory in a multi-core system.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: An information processing apparatus is disclosed, in which the bothersome user operation to retrieve and select the program to be deleted and compressed from a recording medium to acquire the available capacity of the recording medium can be omitted. The program of the recording medium to be deleted or compressed is selected according to a preset reference, a method of processing the selected program is selected, and the program and the processing method thus selected are output to the user.

Abstract: A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to the target storage system; causing the host to access the volume on the drive to be migrated through an input/output port of the drive to be migrated as the external volume of the target storage system; blocking the other input/output port of the drive to be migrated while maintaining the access to the external volume of the target storage system; reconnecting the blocked input/output port with an interface in the target storage system; blocking the input/output port through which the external volume is being accessed, and connecting it with the interface in the target storage system; and implementing the drive to be migrated in the target storage system.

Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.

Abstract: One embodiment relates to a method of handling uncommitted pages in a remote file system. At least three lists are maintained at a client of the remote file system. Said at least three lists include a list of dirty pages, a list of uncommitted pages, and a list of clean pages. Other features and embodiments are also disclosed.

Abstract: Techniques for implementing a scalable DOM and a pluggable DOM are provided. A scalable DOM implementation manages a DOM tree in memory to free unreferenced nodes, avoid generating nodes unnecessarily, and avoid storing multiple versions of the same data on disk. A pluggable DOM implementation includes an abstract interface that is defined between the API layer and the data layer of a DOM implementation. An implementation of the abstract interface is defined for each data source that is plugged in to the pluggable DOM implementation and that stores XML data in a different format.

Abstract: A method for generating a consistent point in time copy of data, the method includes: selecting at least one selected data block to be copied from a source volume to a target volume in response to a request to generate a consistent point in time copy of multiple data blocks; waiting until the source volume is ready to send the at least one selected data block to a remote volume while queuing at least one data block modify request; de-queuing the at least one queued modify requests while copying the at least one selected data block from the source volume to the target volume; wherein the copying includes utilizing a first copying mechanism to copy a first selected data block if a request to modify the first selected block is de-queued before the first selected data block is copied to the target volume; else, the copying includes using a second copying mechanism that is slower than the first copying mechanism.

Abstract: In a configuration in which it is necessary to transfer data from a first storage system to a third storage system through a storage system between the storage systems, there is a problem that it is inevitable to give an excess logical volume to a second storage system between the storage systems. A remote copy system includes first storage system that sends and receives data to and from an information processing apparatus, a second storage system, and a third storage system. The second storage system virtually has a second storage area in which the data should be written and has a third storage area in which the data written in the second storage area and update information concerning the data are written. Data sent from the first storage system is not written in the second storage area but is written in the third storage area as data and update information. The data and the update information written in the third storage area are read out from the third storage system.

Abstract: A method for automatically detecting an attempted invalid access to a memory address in accordance with an exemplary embodiment is provided. The method includes reading a first data set having a software application name and a memory address stored therein utilizing the mainframe computer. The memory address indicates a portion of a memory that is not allowed to be changed. The method further includes detecting when a software application is attempting to access the memory address and setting a first bit in the memory to a first value in response to the detection utilizing the mainframe computer. The method further includes storing a name of the software application, the memory address, and contents of the portion of the memory specified by the memory address, in a second data set, when the first bit has the first value utilizing the mainframe computer. The method further includes displaying an error message on a display device when the first bit has the first value.

Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.

Abstract: A method for use of a diagnostic software tool that can allow software developers to track the number of times each memory block is enlarged, and highlight the most frequently enlarged memory blocks. In this regard, in better understanding the performance characteristics of memory reallocation a developer can use this method to identify and implement better coding techniques to improve code efficiency and reduce the processing time utilized for memory reallocations. In addition, graphs can be generated to indicate the time/CPU utilization dedicated to the memory reallocation process.

Abstract: Methods of operating a non-volatile memory device that includes a first data block that stores first data and a first log block that stores an updated version of at least some of the first data is provided in which valid portions of the first data in the first data block are copied to a free block that has no data to generate a second data block. The updated version of at least some of the first data from the first log block is copied to the second data block. The first log block is designated as a reusable log block without erasing the data therefrom in response to at least one predetermined condition being satisfied.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: Provided is a computer system, in which a storage system includes a first control module for logically dividing first resources of the storage system and operating them as independent virtual storage systems. A computer includes a second control module for logically dividing second resources of the computer and operating them as independent virtual machines. The computer system holds first information indicating a correlation among the virtual machine, the virtual storage system, and the first resources. The first control module specifies the first resource allocated to the virtual storage system whose power is cut based on the first information, and powers off the specified first resource. Thus, system power consumption can be reduced by managing power of the storage system shared by a plurality of virtual machines in a virtualization environment.

Abstract: A memory system is disclosed with a file system; a flash translation layer (FTL) receiving a logical address from the file system and translating it into a physical address, and a flash memory receiving the physical address. The FTL includes flag information and offset information, the flag information indicating page order for a memory block in the flash memory is a wrap-around order and the offset information defining a starting page for the memory block.

Abstract: The information processing apparatus includes a CPU, a memory connected to the CPU 2 via a bus, an external device configured to perform predetermined processing, an MMU, and a DMAC. The DMAC transfers input data from the memory based on a physical address of the memory set as a physical address of the input data, and output data to the memory based on a physical address of the memory set as a physical address of the output data. The external device obtains from the MMU a physical address corresponding to a virtual address of target data, and obtains from the MMU a physical address corresponding to a virtual address of result data. The external device sets the obtained physical addresses of the target data and the result data as physical addresses of the input data and the output data, respectively.

Abstract: Disclosed are a method and system for address translation with memory windows. The method comprises the steps of designating a memory region having a set of virtual addresses, each virtual address having an associated real address; and providing one or more translation tables for translating the virtual addresses to the real addresses; A memory region protection table entry (MRPTE) defines access rights for the memory region, and includes one or more pointers to the one or more translation tables. A memory window is bound to the memory region to provide access to a subset of the virtual addresses. A memory window protection table entry (MWPTE) defines access rights for the memory window, and includes one or more pointers to the one or more translation tables to translate the subset of virtual addresses to real addresses.

Abstract: The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.

Abstract: 1. A data storage system (1) comprises: —an optical disc (2) having a storage space (3) comprising blocks (4) of storage locations; —a disc drive (10), suitable for reading information from the disc, the drive being designed to automatically start reading a next block after having read a previous block; —a host (20), capable of cooperating with the drive; —the host being designed to send (5) commands to said drive, commanding said drive to read one or more sectors of data from said disc (2); —the host being designed to send a jump command JUMPm(X,Y;SAP) to said drive, for instructing said drive to jump to block Y after having read block X, the jump command JUMPm(X,Y;SAP) including a sequential access parameter SAP; —the drive being designed, in response to receiving a jump command JUMPm(X,Y<X;SAP˜0), to jump back to block Y after having read block X.

Abstract: A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N?2, M?2, K?2, and B?1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.

Abstract: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Abstract: A system and method are disclosed which may include providing a processor instruction pipeline having a main line and a branch line; executing at least one wait cycle for at least one wait instruction in said pipeline; and advancing at least selected instructions, that are initially located subsequent to at least one wait instruction in said pipeline, through the pipeline during the at least one wait cycle.

Abstract: Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states. Also described are applications for stabilization of operating systems and other hardware or software configurations, apparatus and methods for ensuring eventual invariance of software executed by a processor, and apparatus and methods for enforcing fixed software configurations.

Abstract: A reference address generator receives UV coordinate values from a shader, converts the value into a reference address for referring to a texture, and refers to a texture map or an instruction map stored in a texture memory based upon the reference address. The value referred to by the texture map is supplied to an interpolation unit, and the value referred to by the instruction map is written into an instruction buffer. The interpolation unit performs a texture mapping process so as to generate color values corresponding to the UV coordinate values of the pixels and supply the color values to the shader via a data path. An instruction decoder reads out an instruction code retained in the instruction buffer, decodes the instruction code, and supplies a control signal for executing the decoded instruction to the shader.

Abstract: A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering data, said reordering data comprising data relating to said computer program; and (iii) outputting said reordered diagnostic data. In general, the instructions streams are processed by a plurality of processing units arranged to process at least some of said instructions in parallel, said diagnostic data being received from said plurality of processing units.

Abstract: A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately executed and that each comprise different data processing code.

Abstract: A technique for creating memory page classification that improves memory dumping efficiency. In one example embodiment, this is accomplished by creating DPCs that substantially maps to operational hierarchy of kernel that includes modules/sub-systems that can allocate and manage the kernel. One or more DPCs associated with the kernel's modules/sub-systems that needs to dumped is then determined upon receiving a computer system panic condition. The memory pages associated with the one or more DPCs are then dumped to an external memory based on the determination.

Abstract: A method for recovering a content of a basic input output system (BIOS) of a computing system, includes the steps of: providing an externally electrical connection to said BIOS and said computing system; providing an operable recovery source for said BIOS and connectable with said computing system via said externally electrical connection; recording recovery information from said recovery source via said externally electrical connection; and switching said externally electrical connection of said recovery source to another electrical connection between said BIOS and said computing system so as to replace said content of said BIOS by said recovery information.

Abstract: In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting only configuration information of dynamic reconfiguration arithmetic cells needed to be changed. However, this results in an increase in area of the arithmetic circuit. According to the present invention, a shift register is the only hardware resource in the dynamic reconfiguration arithmetic block for changing the configuration information. The shift register is structured by connecting in series storage units corresponding one-to-one with each arithmetic cell. An output from the end terminal of the shift register and an output of the configuration information storage unit are input to the configuration information selector, and an output of the configuration information selector is connected to the front of the shift register. The cell address counter counts up from 0 and increments one at a time.