Patents Issued in April 24, 2008
  • Publication number: 20080094861
    Abstract: A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference voltage and a drain coupled to the inductor, and a second transistor having a source coupled to an output conductor to produce an output voltage and a drain coupled to the inductor. A feedback signal representative of a value of the output voltage is generated, and a switch control signal is produced in response to the input voltage and a second reference voltage. The second transistor is turned off in response to the switch control signal each time the inductor current has decayed to zero to prevent reverse current flow through the inductor. A regulating signal indicates whether or not the feedback voltage exceeds the second reference voltage, to regulate the output voltage in a pulse-frequency modulation mode.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 24, 2008
    Inventor: Binan Wang
  • Publication number: 20080094862
    Abstract: The present invention is an AC/DC (alternating current to direct current) converter. The converter contains two semi-stages. One is the boost-flyback semi-stage that has excellent self-PFC property when operating in DCM even though the boost output is close to the peak value of the line voltage. Moreover, it allows part input power transferred to load directly through the flyback path so the power conversion efficiency is improved. The other one is the D/DC semi-stage that provides another parallel power flow path and improves the regulation speed.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Applicant: High Power-Factor AC/DC Converter with Parallel Power Processing
    Inventors: Heng-Yi Li, Chin-Ching Tzeng
  • Publication number: 20080094863
    Abstract: Inverter-filter non-linearity blanking time and zero current clamping compensation is accomplished by comparing the average output current with the discontinuous current mode threshold values to determine when the average output current is entering a discontinuous current mode and introducing a compensation voltage to the inverter drive voltage in response to the average output current entering a discontinuous current mode to compensate for discontinuous current mode distortion of the inverter output voltage.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 24, 2008
    Inventor: Dorin O. Neacsu
  • Publication number: 20080094864
    Abstract: This invention is to reduce a voltage across a smoothing capacitor in a single-phase capacitorless inverter. A smoothing circuit (15) has a smoothing capacitor (C) connected between a pair of power supply lines (L1, L2). A diode (Ds) has its anode connected to one of the power supply lines (L1) and has its cathode connected to an end of a resistor (Rs), the other end of the resistor is connected to an end of a capacitor (Cs), the other end of the capacitor is connected to the other of the power supply lines (L2). In this way, the magnitude of a rectified voltage (Vdc) across the smoothing capacitor (C) can be reduced as compared with an absence of the series connection of diode (Ds), resistor (Rs) and capacitor (Cs).
    Type: Application
    Filed: August 25, 2005
    Publication date: April 24, 2008
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Morimitsu Sekimoto, Hiroyuki Yamai
  • Publication number: 20080094865
    Abstract: Charge storage devices (e.g., batteries or supercapacitors) need to be charged from time to time. In an apparatus, to protect a charge storage device as well as the supply used to charge it, the apparatus typically includes power loop control circuitry. One approach to implementing the power loop control employs a temperature sensor in combination with soft start circuitry in order to protect the circuitry from a rapidly increasing temperature when charge current increases. The soft start circuitry allows for controlled step-wise increase and regulation of the current. The approach preferably allows for selecting the number and resolution of such incremental steps. Various embodiments of the invention include devices and methods for controlling power and may take into account temperature in step-wise regulation of the charge current.
    Type: Application
    Filed: May 16, 2007
    Publication date: April 24, 2008
    Applicant: Advanced Analogic Technologies, Inc.
    Inventors: John So, David Yen Wai Wong
  • Publication number: 20080094866
    Abstract: A regenerative snubber circuit for a boost converter is provided which greatly reduces the switching losses of the IGBT in the converter. The circuit uses no additional magnetic components, has a simple control strategy, is relatively low-cost, and provides an increase in efficiency and decrease in size and mass of the converter.
    Type: Application
    Filed: July 6, 2007
    Publication date: April 24, 2008
    Inventors: Jennifer Bauman, Mehrdad Kazerani
  • Publication number: 20080094867
    Abstract: The subject matter of the invention is an inverter (3), more specifically for use in a photovoltaic plant (1) with a direct voltage input (connection terminals 4; 5) for connection to a generator (2) and an alternating voltage output (connection terminals 7; 8) for feeding into an energy supply network (6) as well as with a DC-AC converter (12) with semiconductor switch elements (15) and an intermediate circuit (11), at least one short-circuit switch element (18) being connected in parallel to the generator (2), so that the voltage will not exceed a maximum voltage value neither at the connection terminals (4; 5) of the generator (2) nor between the connection terminals (9; 10) of the inverter.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 24, 2008
    Applicant: SMA Technologie AG
    Inventors: Burkard Muller, Frank Greizer
  • Publication number: 20080094868
    Abstract: A reliable, end-to-end power supply solution for components of a telecommunications network provides either a primary source or a backup source of electrical power at various telecommunications sites for reliable operation of telecommunications equipment. One subsystem of the power supply solution includes one or more proton exchange membrane type fuel cells and an energy storage device for storing DC electrical power produced by the fuel cells. Another subsystem includes one or more microturbine generators, one or more rectifiers for converting AC electrical power produced by the microturbine generators to DC electrical power, and one or more proton exchange membrane type fuel cells for producing DC electrical power. The power supply solution ensures that voice and data traffic is reliably handled by a telecommunications network in situations where commercial electric utilities fail to supply power at certain points along the network.
    Type: Application
    Filed: December 6, 2006
    Publication date: April 24, 2008
    Applicant: SPRINT COMMUNICATIONS COMPANY L.P.
    Inventors: JERRY MEYERS, LARRY L. JOHNSON
  • Publication number: 20080094869
    Abstract: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
    Type: Application
    Filed: December 10, 2007
    Publication date: April 24, 2008
    Inventors: Kenichi OSADA, Takayuki KAWAHARA, Ken YAMAGUCHI, Yoshikazu SAITO, Naoki KITAI
  • Publication number: 20080094870
    Abstract: A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array. In the memory cell array, a memory cell length in the first direction is substantially n times the transistor pitch, wherein n is an integer.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 24, 2008
    Inventors: Kazuki Tsujimura, Hiroaki Okuyama
  • Publication number: 20080094871
    Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 24, 2008
    Inventor: WARD PARKINSON
  • Publication number: 20080094872
    Abstract: Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and drying the substrate, and exposing and developing the thin layer, an organic layer pattern prepared by the method, and an organic memory device comprising the pattern. According to example embodiments, a high-resolution micropattern may be formed without undergoing any expensive process, e.g., photoresist, leading to simplification of the preparation process and cost reduction.
    Type: Application
    Filed: March 9, 2007
    Publication date: April 24, 2008
    Inventors: Sang Kyun Lee, Won Jae Joo, Kwang Hee Lee, Tae Lim Choi, Myung Sup Jung
  • Publication number: 20080094873
    Abstract: A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Publication number: 20080094874
    Abstract: Disclosed herein is a multiple read-port nonvolatile memory cell structure, and related method of sensing a resistance state of memory cell, for high-speed and high-bandwidth applications. It provides about a 2× bandwidth gain over conventional cells during the read cycle in embodiments where two read ports are constructed. For example, where conventional arrays include only one read wordline and one read bitline for each memory cell in an array, an array constructed as disclosed herein includes at least two read wordlines and at least two read bitlines for each memory cell. It is still comparable in cell size with a typical 1T1RV cell because the cell pitch is limited by backend size and under-metal layer connection layout.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Publication number: 20080094875
    Abstract: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 24, 2008
    Applicant: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20080094876
    Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson
  • Publication number: 20080094877
    Abstract: A method of initializing dynamic random access memory (DRAM) comprises allocating one or more rows of a plurality of cells in the DRAM; signaling an initialization request to initialize the allocated one or more rows; and simultaneously initializing all cells in each of the one or more allocated rows upon accessing each of the one or more allocated rows.
    Type: Application
    Filed: October 20, 2006
    Publication date: April 24, 2008
    Applicant: Honeywell International Inc.
    Inventor: Eric R. Schneider
  • Publication number: 20080094878
    Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Application
    Filed: December 22, 2007
    Publication date: April 24, 2008
    Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan
  • Publication number: 20080094879
    Abstract: A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs control so that in writing data into the memory cell, a voltage at one of the two storage nodes holding a low logic level is raised without changing voltages at respective sources of the load transistors.
    Type: Application
    Filed: July 13, 2007
    Publication date: April 24, 2008
    Inventor: Akira Masuo
  • Publication number: 20080094880
    Abstract: A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, and a second non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. The first magnetic layer, the second magnetic layer and the third magnetic layer are coupled such that spontaneous magnetizations have a helical structure.
    Type: Application
    Filed: August 26, 2005
    Publication date: April 24, 2008
    Applicant: NEC CORPORATION
    Inventors: Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura
  • Publication number: 20080094881
    Abstract: A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment vector and the second magnetic region has a free second magnetic moment vector that is switchable between the same and opposite directions with respect to the fixed first magnetic moment vector. The second stacked structure is at least partly arranged in a lateral relationship with respect to the first stacked structure and includes a third magnetic region having a fixed third magnetic moment vector and the second magnetic region. The first and second structures are arranged between at least two electrodes in electrical contact therewith.
    Type: Application
    Filed: August 27, 2007
    Publication date: April 24, 2008
    Applicants: INFINEON TECHNOLOGIES AG, ALTIS SEMICONDUCTOR S.N.C., CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE PARIS-SUD
    Inventors: Jacques Miltat, Yoshinobu Nakatani, Ulrich Klostermann
  • Publication number: 20080094882
    Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Inventors: Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki
  • Publication number: 20080094883
    Abstract: To provide a magnetic memory capable of reducing the amount of write current, even when the element size is 0.7 ?m or less. Each of storage areas has a transistor for read/write control, which is connected electrically to either one of the fixed layer and the free layer of each magneto-resistance effect element, a wiring that is electrically connected to the other one of the fixed layer and the free layer of each magneto-resistance effect element, and a magnetic yoke that surrounds the wiring and provides a magnetic field to the free layer, and the number of the transistors within each storage area is one.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 24, 2008
    Applicant: TDK CORPORATION
    Inventor: Keiji Koga
  • Publication number: 20080094884
    Abstract: An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.
    Type: Application
    Filed: December 14, 2007
    Publication date: April 24, 2008
    Inventors: Hsu Yang, Po-Kang Wang, Xizeng Shi
  • Publication number: 20080094885
    Abstract: A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the second memory stack overlies a third memory layer stack. The first memory layer stack has a first conductive layer overlies a first programmable resistance random access memory layer. The second memory layer stack has a second conductive layer overlies a second programmable resistance random access memory layer. The second programmable resistance random access memory layer has a memory area that is larger than a memory area of the first programmable resistance random access memory layer.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 24, 2008
    Applicant: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20080094886
    Abstract: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.
    Type: Application
    Filed: February 12, 2007
    Publication date: April 24, 2008
    Inventors: Rajiv Yadav Ranjan, Petro Estakhri, Mahmud Assar, Parviz Keshtbod
  • Publication number: 20080094887
    Abstract: A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain wall in the magnetic layer. The magnetic layer is formed parallel to the substrate, and includes a plurality of prominences and a plurality of depressions alternately formed along a lengthwise direction thereof. The magnetic layer has a stepped form that secures a reliable movement of the magnetic domain wall in units of one bit.
    Type: Application
    Filed: March 28, 2007
    Publication date: April 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-jun Hwang, Sung-chul Lee
  • Publication number: 20080094888
    Abstract: A magnetic random access memory (MRAM) is disclosed. The MRAM includes a first electrode, an antiferromagnetic layer formed over the first electrode, a pinned layer formed over the antiferromagnetic layer, a barrier layer formed over the pinned layer, a composite free layer formed over the barrier layer, and a second electrode formed over the composite free layer. The composite free layer includes a first magnetic layer, a spacer layer and a second magnetic layer sequentially stacked over the barrier layer and the spacer layer allows parallel coupling between the first and second magnetic layers. A magnetic tunnel junction (MTJ) device suitable for a memory unit of a magnetic memory device is also provided.
    Type: Application
    Filed: February 16, 2007
    Publication date: April 24, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Chuan Chen, Yung-Hung Wang, Shan-Yi Yang, Kuei-Hung Shen
  • Publication number: 20080094889
    Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.
    Type: Application
    Filed: July 24, 2007
    Publication date: April 24, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Satoru KUROTSU
  • Publication number: 20080094890
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.
    Type: Application
    Filed: June 28, 2007
    Publication date: April 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Kuk Kim, Woo-Seop Jeong
  • Publication number: 20080094891
    Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Applicant: Macronix International Co., Ltd.
    Inventors: Wen-Chiao Ho, Chin-Hung Chang, Cheng-Chi Liu, Kuen-Long Chang, Chun-Hsiung Hung
  • Publication number: 20080094892
    Abstract: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 24, 2008
    Inventors: Luca G. Fasoli, Tyler Thorp
  • Publication number: 20080094893
    Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.
    Type: Application
    Filed: March 30, 2007
    Publication date: April 24, 2008
    Inventor: Jin-Hyeok Choi
  • Publication number: 20080094894
    Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells each configured to store M bits of data, where M is an integer greater than 1. In addition, the memory includes a selection circuit configured to select a first or second mode according to an instruction from outside of the nonvolatile semiconductor memory, and a program circuit configured to program M bits of data into each memory cell in the first mode, and N bits of data into each memory cell in the second mode, where N is an integer less than M. A selection pin may receive a voltage as the instruction from outside the memory indicating the first or second mode. Further, each of the memory cells may be assigned N different page addresses in the first mode and M different page addresses in the second mode.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiyuki HAYAKAWA
  • Publication number: 20080094895
    Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.
    Type: Application
    Filed: May 15, 2007
    Publication date: April 24, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Young Lee, Dong-Won Kim, Min-Sang Kim, Dong-Gun Park, Eun-Jung Yun
  • Publication number: 20080094896
    Abstract: The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Karl R. Erickson, John A. Fifield, Chandrasekara Kothandaraman, Phil C. Paone, William R. Tonti
  • Publication number: 20080094897
    Abstract: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing the data stored in the buffer memory to the at least one memory cell.
    Type: Application
    Filed: November 30, 2006
    Publication date: April 24, 2008
    Inventors: Tae-Jin Chung, Jeong-Un Choi
  • Publication number: 20080094898
    Abstract: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki Nakano, Toshimasa Namekawa, Hiroshi Ito, Osamu Wada, Atsushi Nakayama
  • Publication number: 20080094899
    Abstract: A non-volatile semiconductor memory device, allocates data contained in an ECC frame as a first data group to be stored in a first memory cell group composed of a plurality of first memory cells selected by a first word line and a second data group to be stored in a second memory cell group composed of a plurality of second memory cells selected by a second word line.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuaki Honma, Noboru Shibata, Shinji Saito
  • Publication number: 20080094900
    Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second word lines extending in a first direction and having the same row address, a first block including the first word line and having a first block address, a second block including the second word line and having a second block address, first and second signal lines extending in a second direction crossing the first direction, a first transfer transistor connected between the first word line and the first signal line, a second transfer transistor connected between the second word line and the second signal line, and a transfer voltage selector to output a transfer voltage to the first and second signal lines.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 24, 2008
    Inventors: Dai NAKAMURA, Koji Hosono
  • Publication number: 20080094901
    Abstract: The present invention provides a flash memory device that comprises a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in either one of the even page cells or the odd page cells.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 24, 2008
    Inventors: Ki-Tae Park, Yeong-Taek Lee, Ki-Nam Kim
  • Publication number: 20080094902
    Abstract: A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage in a read operation. A row selection circuit is coupled to the memory cell array through a string selection line, ground selection line and a plurality of word lines. The row selection circuit selects a word line which is coupled to the read memory cell among the plurality of word lines based on a row address signal and a read voltage in a read operation. A voltage generation circuit generates the string selection voltage and the read voltage.
    Type: Application
    Filed: November 30, 2006
    Publication date: April 24, 2008
    Inventor: Jin-Yub Lee
  • Publication number: 20080094903
    Abstract: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Maejima, Katsuaki Isobe
  • Publication number: 20080094904
    Abstract: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
    Type: Application
    Filed: September 12, 2007
    Publication date: April 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dae-Seok BYEON
  • Publication number: 20080094905
    Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
    Type: Application
    Filed: December 7, 2007
    Publication date: April 24, 2008
    Inventors: Koji Kishi, Hideaki Kurata, Satoshi Noda, Yusuke Jono
  • Publication number: 20080094906
    Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.
    Type: Application
    Filed: December 26, 2007
    Publication date: April 24, 2008
    Applicant: STMicroelectronics S.r.I.
    Inventors: Davide Cascone, Nicola Del Gatto, Emanuele Confalonieri, Massimiliano Mollichelli
  • Publication number: 20080094907
    Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 24, 2008
    Applicant: SanDisk IL Ltd.
    Inventor: Amir Ban
  • Publication number: 20080094908
    Abstract: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.
    Type: Application
    Filed: December 18, 2007
    Publication date: April 24, 2008
    Inventors: Nima Mokhlesi, Dengtao Zhao
  • Publication number: 20080094909
    Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.
    Type: Application
    Filed: December 18, 2007
    Publication date: April 24, 2008
    Inventors: Girolamo Gallo, Giulio Marotta
  • Publication number: 20080094910
    Abstract: A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.
    Type: Application
    Filed: December 27, 2006
    Publication date: April 24, 2008
    Inventor: Sang-Pil Sim