Patents Issued in May 20, 2008
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Patent number: 7375349Abstract: In a radiation-image conversion panel, a fluorescent layer containing a phosphor and a protective layer are formed on a support in this order. The protective layer has a water-vapor transmission rate of 1 g/m2/24 h or lower at 40° C. and a reflectance of 3% or lower at a wavelength of light emitted from the phosphor. In addition, the protective layer may be obtained by attaching a removable film to a thin transparent film so as to produce a laminated film, forming a vapor-barrier layer on an exposed surface of the thin transparent film by vacuum deposition so as to produce a moisture-resistant film, placing the moisture-resistant film on the fluorescent layer, and removing the removable film from the moisture-resistant film.Type: GrantFiled: November 19, 2004Date of Patent: May 20, 2008Assignee: FUJIFILM CorporationInventors: Hajime Kubota, Atsunori Takasu, Takeo Kido
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Patent number: 7375350Abstract: Embodiments include a method and apparatus for improving the reusability of a computed radiography (CR) plate by housing it in a cassette. The CR plate remains in the cassette during scanning. The embodiments of the method and apparatus improve the reusability of the CR plate.Type: GrantFiled: November 13, 2003Date of Patent: May 20, 2008Inventor: Stephen Neusbul
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Patent number: 7375351Abstract: Provided is a micro-column electron beam apparatus including: a base; an electron lens bracket on which an electron lens module can be fixed, mounted in a central portion of the base; an electron beam source tip module vertically disposed on the electron lens module; a pan spring plate stage module that is mounted over the base, supports the electron beam source tip module at a central portion thereof, and includes a three-coupling pan spring plate portion including first through third spring units that are coupled to the electron beam source tip module in three directions on a plane perpendicular to the vertical axis, which vertically passes the center of the electron beam source tip module, to elastically support the electron beam source tip module in three directions; a first piezoelectric actuator coupled to the pan spring plate stage module to move the electron beam source tip module along a first axis perpendicular to the vertical axis; and a second piezoelectric actuator coupled to the pan spring plateType: GrantFiled: October 24, 2005Date of Patent: May 20, 2008Assignee: Electronics and Telecommunications Research InstututeInventors: Sang Kuk Choi, Dae Jun Kim, Jin Woo Jeong, Dae Yong Kim
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Patent number: 7375352Abstract: In order to make it possible to improve throughput of AFM scratch processing, enable correction of small defects in clear defect correction with a high degree of precision, and enable correction in a shorter period of time in the event of overcutting by AFM scratch processing, throughput of AFM scratch processing is increased by maximizing high-resolution of the electron beam device and minimizing the time taken in observations using a device incorporating both an electro-optical system and an AFM head in a vacuum, correcting small clear defects with high precision by eliminating portions left over from AFM scratch processing after applying a clear defect correction film using an electron beam while providing light-blocking film raw material, and correction in a short time is made possible by eliminating portions remaining using AFM scratch processing after applying a clear defect correction film using an electron beam while providing light-blocking film raw material also in cases of overcutting in AFM scratcType: GrantFiled: May 25, 2005Date of Patent: May 20, 2008Assignee: SII NanoTechnology Inc.Inventors: Osamu Takaoka, Ryoji Hagiwara
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Patent number: 7375353Abstract: An attenuation adjustment device is disclosed that includes a plurality of members configured to cast penumbras in a radiation beam illuminating a patterning device in a lithography apparatus. Furthermore, an attenuation control device is provided to adjust the members in such a manner as to control the attenuation of the patterned radiation beam projected onto a target portion of a substrate across the cross-section of the patterned radiation beam. The attenuation control device includes a detector configured to provide an output indicative of the position of each member in dependence on detection of a beam of detecting radiation reaching the detector after attenuation by the member.Type: GrantFiled: September 13, 2005Date of Patent: May 20, 2008Assignee: ASML Netherlands B.V.Inventors: Hendrik Antony Johannes Neerhof, Hako Botma, Marius Ravensbergen
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Patent number: 7375354Abstract: The ion implanting method uses both reciprocatively scanning an ion beam in an X direction and reciprocatively mechanically driving a substrate in a Y direction orthogonal thereto. An implanting step of implanting ions separately for two implanted regions with different dose amounts of the substrate is executed plural times by changing at the center of the substrate a driving speed of the substrate. A rotating step of rotating the substrate around its center by a prescribed angle is executed once during each of the intervals between the respective implanting steps and while the ion beam is not applied to the substrate.Type: GrantFiled: March 15, 2004Date of Patent: May 20, 2008Assignee: Nissin Ion Equipment Co., Ltd.Inventors: Koji Iwasawa, Nobuo Nagai
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Patent number: 7375355Abstract: An ion implantation cluster tool for implanting ions into a workpiece is provided, wherein a plurality of beamline assemblies having a respective plurality of ion beamlines associated therewith are positioned about a common process chamber. Each of the plurality of ion beamline assemblies are selectively isolated from the common process chamber, and the plurality of beamline intersect at a processing region of the process chamber. A scanning apparatus positioned within the common process chamber is operable to selectively translate a workpiece holder in one or more directions through each of the plurality of ion beamlines within the processing region, and a common dosimetry apparatus within the common process chamber is operable to measure one or more properties of each of the plurality of ion beamlines. A load lock chamber is operably coupled to the common process chamber for exchange of workpieces between the common process chamber and an external environment.Type: GrantFiled: May 12, 2006Date of Patent: May 20, 2008Assignee: Axcelis Technologies, Inc.Inventors: Joseph Ferrara, Patrick R. Splinter, Michael A. Graf, Victor M. Benveniste
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Patent number: 7375356Abstract: An electron-beam exposure system includes: density-per-area map generating means configured to divide a certain area on which an electron beam is irradiated into meshes, to figure out a ratio of an area of patterns to be irradiated on each divided region to an area of the divided region, thus to generate a density-per-area map; and proximity-effect correcting means configured to correct exposure of the electron beam by referring to the density-per-area map.Type: GrantFiled: June 21, 2006Date of Patent: May 20, 2008Assignee: Advantest Corp.Inventor: Masaki Kurokawa
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Patent number: 7375357Abstract: The present invention provides a plurality of permanent magnets to enhance radiation dose delivery of a high energy particle beam. The direction of the magnetic field from the permanent magnets may be changed by moving the permanent magnets.Type: GrantFiled: August 23, 2005Date of Patent: May 20, 2008Assignee: Avi FaliksInventor: Leon Kaufman
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Patent number: 7375358Abstract: A radiation shield and method for reducing ambient radiation levels at a distance from a surface irradiated by penetrating radiation emanating from an instrument substantially along a propagation axis. The shield attaches to an end of the instrument proximate to an irradiated surface and has a surface of attenuating material disposed with a component extending outward from the propagation axis of penetrating radiation and substantially adjacent to the irradiated surface.Type: GrantFiled: April 27, 2005Date of Patent: May 20, 2008Assignee: Thermo NITON Analyzers LLCInventors: Kenneth P. Martin, Anthony Honnellio, Lee Grodzins
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Patent number: 7375359Abstract: An instrument and method for measuring the elemental composition of a test material. The instrument has a source of penetrating radiation for irradiating an irradiated region of the test material, a detector for detecting fluorescence emission by the test material and for generating a detector signal, and a controller for converting the detector signal into a spectrum characterizing the composition of the test material. A platen of attenuating material extends outward from adjacent to, and surrounding, the irradiated surface of the test material. In certain embodiments, the thickness of the attenuating platen is tapered with increasing radial distance from the central irradiated region of the test material.Type: GrantFiled: May 25, 2006Date of Patent: May 20, 2008Assignee: Thermo NITON Analyzers LLCInventor: Lee Grodzins
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Patent number: 7375360Abstract: There is disclosed a light device for arranging a thin film pattern sensor array where a sensor array used for inspecting a thin film pattern is made to be arranged without a separate correction pattern film in accordance with an inspection subject. In the light device for arranging the thin film pattern sensor array, a shutter controls a width of a light beam which progresses from a light emitting element array to a sensor array. A correction pattern sled is installed in any one of a fixed location of an upper part of the shutter and a surface of the shutter to be transferable.Type: GrantFiled: January 9, 2006Date of Patent: May 20, 2008Assignee: LG Electronics Inc.Inventor: Kyung Gu Kim
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Patent number: 7375361Abstract: The orientation of a machine 2 relative to a work-piece 10 is manually controlled by means of an alignment device 4. The device 4 includes a light source 24 rigidly attached to a foot 12 that is resiliently movably attached to the main body 18 of the device. The body 18 of the device 4 houses a light detector 26 for detecting a light beam from the light source 24, the position of the region on the detector 26 illuminated by the beam depending on the orientation of the machine 2 relative to the work-piece 10. The operator is provided with feedback on whether the machine 2 is correctly aligned with a target orientation (usually perpendicular to the surface) and concerning the direction of corrective movement required, if any.Type: GrantFiled: February 16, 2005Date of Patent: May 20, 2008Assignee: Airbus UK LimitedInventors: Brian John Turner, Timothy David Hall
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Patent number: 7375362Abstract: An optical test head comprises one or more optical input paths by which a beam of light is communicated from a light source to a workpiece and one or more optical output paths by which light reflected off of the workpiece is communicated to a detector. The input optical path and the output optical path can include one or more mirrors and one or more lenses. At least one of the optical paths includes a layer for trapping and/or absorbing stray light. One or more of the lenses includes an anti-reflective coating for reducing noise caused by unwanted light reflection off of the lenses. The optical paths include one or more masks reducing stray light. The one or more masks can have an adjustable aperture (e.g. an iris).Type: GrantFiled: April 22, 2005Date of Patent: May 20, 2008Assignee: WD Media, Inc.Inventors: David Treves, Thomas A. O'Dell
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Patent number: 7375363Abstract: After a main unit has captured an image of a subject, the main unit is detached from a support post fixedly mounted in a compartment of a vehicle through a mounting/dismounting mechanism, and stored in a storage case disposed in the compartment of the vehicle. The storage case, which can be closed by a lid, incorporates therein first and second thermal insulating members made of a thermal insulating material, and first and second damping members disposed respectively in the first and second thermal insulating members for absorbing vibrations from the vehicle.Type: GrantFiled: February 8, 2005Date of Patent: May 20, 2008Assignee: FUJIFILM CorporationInventors: Yuzuru Ohtsuka, Yasunori Ohta
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Patent number: 7375364Abstract: A recording sheet usage count evaluation method enabling, even when plural radiation imaging apparatuses and plural radiographic image reading apparatuses exist, accurate evaluation of cumulative working frequencies of recording sheets commonly used in those apparatuses. The method includes the steps of (a) receiving recording sheet identification information with image data from a radiographic image reading apparatus; (b) counting a usage count of each recording sheet on a basis of the recording sheet identification information received at step (a), weighting a count value in accordance with a set condition, and accumulating the weighted count value to store the accumulated count value in correspondence with the recording sheet identification information; and (c) calculating a total count value for each recording sheet by referring to count values stored in other medical image processing apparatuses and adding the count values to the count value stored at step (b).Type: GrantFiled: March 27, 2006Date of Patent: May 20, 2008Assignee: FUJIFILM CorporationInventors: Naoki Mochizuki, Yasunori Ohta
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Patent number: 7375365Abstract: A multilevel phase-change memory, manufacture method and operating method thereof are provided. The memory includes a first phase change layer, a second phase change layer, a first heating layer formed on one surface of the first phase change layer, a second heating layer formed between the first heating layer and the second phase change layer, a first top electrode formed on another surface of the first phase change layer, a second top electrode formed on the other surface of the second phase change layer, and a bottom electrode formed on the other surface of the first heating layer corresponding to the second heating layer. Further, a substrate is provided to form the aforementioned components. The substrate may also include a transistor. The disclosed device has a multi memory state, thereby increasing the memory density, reducing the memory area and lowering the power consumption.Type: GrantFiled: April 13, 2005Date of Patent: May 20, 2008Assignee: Industrial Technology Research InstituteInventor: Chih-Wen Hsiung
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Patent number: 7375366Abstract: A carbon nanotube has a carbon network film of polycrystalline structure divided into crystal regions along the axis of the tube, and the length along the tube axis of each crystal region preferably ranges from 3 to 6 nm. An electron source includes a carbon nanotube having a cylindrical shape and the end of which on the substrate side is closed and disposed in a fine hole. The end on the substrate side of the tube is firmly adhered to the substrate. The carbon nanotube is produced by a method in which carbon is deposited under the condition that no metal catalyst is present in the fine hole and produced by a method in which after the carbon deposition the end of the carbon deposition film is modified by etching the carbon deposition film using a plasma.Type: GrantFiled: February 22, 2001Date of Patent: May 20, 2008Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Ohki, Tsunaki Tsunesada, Masao Urayama, Takashi Kyotani, Keitarou Matsui, Akira Tomita
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Patent number: 7375367Abstract: A semiconductor light-emitting device fabricated in a nitride material system has an active region disposed over a substrate. The active region comprises a first aluminium-containing layer forming the lowermost layer of the active region, a second aluminium-containing layer forming the uppermost layer of the active region, and at least one InGaN quantum well layer disposed between the first aluminium-containing layer and the second aluminum-containing layer. The aluminium-containing layers provide improved carrier confinement in the active region, and so increase the output optical power of the device.Type: GrantFiled: October 27, 2004Date of Patent: May 20, 2008Assignee: Sharp Kabushiki KaishaInventors: Stewart Hooper, Valerie Bousquet, Katherine L. Johnson, Jonathan Heffernan
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Patent number: 7375368Abstract: This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be created by exposing layers of material in a superlattice and depositing material onto edges of the exposed layers.Type: GrantFiled: October 17, 2006Date of Patent: May 20, 2008Inventors: Pavel Kornilovich, Peter Mardilovich, Kevin Francis Peters, James Stasiak
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Patent number: 7375369Abstract: Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A spin-coatable liquid for formation of a nanotube film includes a liquid medium containing a controlled concentration of purified nanotubes, wherein the controlled concentration is sufficient to form a nanotube fabric or film of preselected density and uniformity, and wherein the spin-coatable liquid includes less than 1×1018 atoms/cm3 of metal impurities. The spin-coatable liquid is substantially free of particle impurities having a diameter of greater than about 500 nm.Type: GrantFiled: June 3, 2004Date of Patent: May 20, 2008Assignee: Nantero, Inc.Inventors: Rahul Sen, Ramesh Sivarajan, Thomas Rueckes, Brent M. Segal
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Patent number: 7375370Abstract: A device is provided having a first electrode, a second electrode, a first photoactive region having a characteristic absorption wavelength ?1 and a second photoactive region having a characteristic absorption wavelength ?2. The photoactive regions are disposed between the first and second electrodes, and further positioned on the same side of a reflective layer, such that the first photoactive region is closer to the reflective layer than the second photoactive region. The materials comprising the photoactive regions may be selected such that ?1 is at least about 10% different from ?2. The device may further comprise an exciton blocking layer disposed adjacent to and in direct contact with the organic acceptor material of each photoactive region, wherein the LUMO of each exciton blocking layer other than that closest to the cathode is not more than about 0.3 eV greater than the LUMO of the acceptor material.Type: GrantFiled: November 3, 2004Date of Patent: May 20, 2008Assignee: The Trustees of Princeton UniversityInventors: Stephen Forrest, Jiangeng Xue, Soichi Uchida, Barry P. Rand
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Patent number: 7375371Abstract: A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.Type: GrantFiled: February 1, 2006Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Giuseppe La Rosa, Kevin W. Kolvenbach, John Greg Massey, Ping-Chuan Wang, Kai Xiu
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Patent number: 7375372Abstract: A thin film transistor (TFT) and a manufacturing method thereof are provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at least covering the gate to serve as channel layer. Next, source/drain regions are formed over the channel layer.Type: GrantFiled: January 26, 2006Date of Patent: May 20, 2008Assignee: Au Optronics CorporationInventors: Fang-Chen Luo, Wan-Yi Liu, Chieh-Chou Hsu
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Patent number: 7375373Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.Type: GrantFiled: July 2, 2002Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Gab Lee, Bong-Joo Kang, Beom-Seok Cho, Chang-Oh Jeong
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Patent number: 7375374Abstract: A thin film transistor array substrate and method for repairing the same are provided. Repairing lines are formed when the data lines on the thin film transistor array substrate are defined. Furthermore, the protruding portions and branches of common lines overlap with the repairing lines and the data lines respectively. The repairing method includes performing a laser welding operation to connect the common line with the data line, the repairing line or a scan line as well as removing a portion of the lines by laser. Thus, the thin film transistor array substrate and repairing method thereof can repair line defects and increase the manufacturing yield.Type: GrantFiled: July 18, 2007Date of Patent: May 20, 2008Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Chin-Sheng Chen, Chih-Hung Liu, Chien-Hsing Hung, Kun-Yuan Huang
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Patent number: 7375375Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.Type: GrantFiled: June 28, 2007Date of Patent: May 20, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 7375376Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.Type: GrantFiled: December 5, 2006Date of Patent: May 20, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosue, Saishi Fujikawa
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Patent number: 7375377Abstract: A light-emitting diode chip (1), in which over a substrate (2), a series of epitaxial layers (3) with a radiation-emitting active structure (4) based on InGaN is disposed. Between the substrate (2) and the active structure (4), a buffer layer (20) is provided. The material or materials of the buffer layer (20) are selected such that their epitaxial surface (6) for the epitaxy of the active structure (4) is unstressed or slightly stressed at their epitaxial temperature. The active structure (4) has In-rich zones (5), disposed laterally side by side relative to the epitaxial plane, in which zones the In content is higher than in other regions of the active structure (4). A preferred method for producing the chip is disclosed.Type: GrantFiled: June 13, 2001Date of Patent: May 20, 2008Assignee: Osram Opto Semiconductors GmbHInventors: Johannes Baur, Georg Brüderl, Berthold Hahn, Volker Härle, Uwe Strauss
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Patent number: 7375378Abstract: A photovoltaic device comprising a photovoltaic cell is provided. The photovoltaic cell includes an emitter layer comprising a crystalline semiconductor material and a lightly doped crystalline substrate disposed adjacent the emitter layer. The lightly doped crystalline substrate and the emitter layer are oppositely doped. Further, the photovoltaic device includes a back surface passivated structure coupled to the photovoltaic cell. The structure includes a highly doped back surface field layer disposed adjacent the lightly doped crystalline substrate. The highly doped back surface field layer includes an amorphous or a microcrystalline semiconductor material, wherein the highly doped back surface field layer and the lightly doped crystalline substrate are similarly doped, and wherein a doping level of the highly doped back surface field layer is higher than a doping level of the lightly doped crystalline substrate.Type: GrantFiled: May 12, 2005Date of Patent: May 20, 2008Assignee: General Electric CompanyInventors: Venkatesan Manivannan, Abasifreke Udo Ebong, Jiunn-Ru Jeffrey Huang, Thomas Paul Feist, James Neil Johnson
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Patent number: 7375379Abstract: The invention provides a light-emitting device and a method of illumination. The light-emitting device includes one or more semiconductor layers, a reflective bottom surface, and a top surface coupled to semiconductor layer. The semiconductor layers include an active region where a primary light is generated. The relative position of the top surface, the reflective bottom surface and the active region is adjusted to substantially transmit the primary light through the sides of the light-emitting device.Type: GrantFiled: December 19, 2005Date of Patent: May 20, 2008Assignee: Philips Limileds Lighting Company, LLCInventors: Mark Pugh, Gerard Harbers, Robert Scott West
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Patent number: 7375380Abstract: A semiconductor light emitting device includes a semiconductor light emitting portion having a first contact layer of a first conductivity, a second contact layer of a second conductivity and an active layer sandwiched between the first and second contact layers. The device further includes a transparent electrode which substantially entirely covers a surface of the second contact layer in ohmic contact with the surface of the second contact layer and is transparent to a wavelength of light emitted from the semiconductor light emitting portion, and a metal reflection film which is opposed to substantially the entire surface of the transparent electrode and electrically connected to the transparent electrode, and reflects the light emitted from the semiconductor light emitting portion and passing through the transparent electrode toward the semiconductor light emitting portion.Type: GrantFiled: July 11, 2005Date of Patent: May 20, 2008Assignee: Rohm Co., Ltd.Inventors: Hirokazu Asahara, Mitsuhiko Sakai, Masayuki Sonobe, Toshio Nishida
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Patent number: 7375381Abstract: An LED illumination apparatus according to the present invention includes at least one connector and a lighting drive circuit. The connector is connected to an insertable and removable card-type LED illumination source, which includes multiple LEDs that have been mounted on one surface of a substrate. The lighting drive circuit is electrically connected to the card-type LED illumination source by way of the connector. The card-type LED illumination source preferably includes a metal base substrate and the multiple LEDs that have been mounted on one surface of the metal base substrate. The back surface of the metal base substrate, including no LEDs thereon, thermally contacts with a portion of the illumination apparatus. A feeder terminal to be electrically connected to the connector is provided on the surface of the metal base substrate on which the LEDs are provided.Type: GrantFiled: May 9, 2005Date of Patent: May 20, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Shimizu, Tadashi Yano, Tatsumi Setomoto, Nobuyuki Matsui, Tetsushi Tamura
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Patent number: 7375382Abstract: An optical light guide has a substantially rigid light transmissive body having an input window, a distal end, a front side, and a rear side. The light transmissive body has a substantially smooth exterior surface on the front side and a substantially clear and solid interior. The input window transmits light into the light transmissive body and extends substantially transverse to a longitudinal axis of a light emitting diode (LED) light source. The light transmissive body has a substantially constant thickness measured between the front side and the rear side. The light transmissive body extends away from the input window through an arc of from 60 to 120 degrees to an extension that forms an output region extending towards the distal end. The rear side, at least in said output region, is formed with a plurality of totally internally reflective steps directing intercepted light towards the front side.Type: GrantFiled: June 5, 2006Date of Patent: May 20, 2008Assignee: Osram Sylvania, Inc.Inventor: Thomas Tessnow
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Patent number: 7375383Abstract: A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.Type: GrantFiled: March 7, 2007Date of Patent: May 20, 2008Assignee: Nichia CorporationInventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
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Patent number: 7375384Abstract: The present invention discloses a side structure of a bare LED and a backlight module thereof, wherein the backlight module is preferably a light source of a display device such as an LCD device. The backlight module includes a flat plate covered with a thermally conductive dielectric material, a plurality of the side structures of the bare LEDs placed on the flat plate and in contact with the thermally conductive dielectric material, and a plurality of reflection parts also placed on the flat plate, each side structure of each bare LED includes a bare LED and two electrically conductive materials coupled to two bonding pads of the side structure of the bare LED respectively, and positioned on the flat plate therefor.Type: GrantFiled: May 8, 2007Date of Patent: May 20, 2008Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Shyi-Ching Liau, Tzong-Che Ho
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Patent number: 7375385Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: August 22, 2003Date of Patent: May 20, 2008Assignee: AmberWave Systems CorporationInventors: Richard Westhoff, Vicky Yang, Matthew Currie, Christopher Vineis, Christopher Leitz
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Patent number: 7375386Abstract: The invention relates to a heterobipolar transistor, comprising an emitter which includes a first semiconductor layer (8) made of a first semiconductor material and a second semiconductor layer (9) made of a second semiconductor material, a band gap value of the first semiconductor material being smaller than a band gap value of the second semiconductor material. A semiconductor intermediate layer (10) made of an intermediate layer semiconductor material is disposed between the first semiconductor layer (9) and the second semiconductor layer (8) and a band gap value of the intermediate layer semiconductor material is greater than the band gap value of the first semiconductor material and smaller than the band gap value or the second semiconductor material. A potential barrier forms at the interface between two semiconductor materials having different band gap values and a stream of electrons must tunnel through it.Type: GrantFiled: January 24, 2003Date of Patent: May 20, 2008Assignee: MergeOptics GmbHInventor: Axel Hülsmann
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Patent number: 7375387Abstract: The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.Type: GrantFiled: March 9, 2006Date of Patent: May 20, 2008Assignee: Infineon Technologies AGInventor: Josef Willer
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Patent number: 7375388Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.Type: GrantFiled: December 15, 2003Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Donald L. Yates, Joel A. Drewes
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Semiconductor device having a capacitor-under-bitline structure and method of manufacturing the same
Patent number: 7375389Abstract: Provided are semiconductor devices having a system-on-chip (SOC) configuration that combines both a capacitor-based cell-array memory region and one or more MOS core/peripheral circuit/logic regions on a single chip and a method for manufacturing such devices. The manufacturing process reduces the number of additional photolithographic processes required and modifies the relationship between the sizing of various layers and/or structures to reduce the fabrication cost and improve the reliability of the resulting devices. In particular, the capacitors for the memory region are formed in the same insulating layer as the first metal pattern for the core/peripheral circuit/logic regions of the devices, thereby producing capacitors and metal patterns of substantially the same height and thickness respectively. A landing structure may also be formed in the cell array region in combination with the first metal pattern for improving the contact process in the cell array region.Type: GrantFiled: February 19, 2004Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hee Oh, Duck-Hyung Lee -
Patent number: 7375390Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.Type: GrantFiled: January 10, 2007Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyeon Lee, Gi-Sung Yeo, Doo-Hoon Goo, Woo-Sung Han
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Patent number: 7375391Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.Type: GrantFiled: October 11, 2005Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Moon, Jae-Min Yu, Don-Woo Lee, Chul-Soon Kwon, In-Gu Yoon, Yong-Sun Lee, Jae-Hyun Park
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Patent number: 7375392Abstract: Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a hard mask 30 overlying the conductive layer 28. A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the hard mask 30 at a rate lower than the rate of deposition on the conductive layer 28. Thus, the liner 32 is substantially thinner on the hard mask 30 than on the conductive layer 28. A nitride spacer is formed over 34 the liner 32. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.Type: GrantFiled: March 30, 2006Date of Patent: May 20, 2008Assignee: Integrated Device Technology, Inc.Inventors: Chih-Hsiang Chen, Guo-Qiang Lo, Shih-Ked Lee
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Patent number: 7375393Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.Type: GrantFiled: January 27, 2005Date of Patent: May 20, 2008Assignee: National Semiconductor CorporationInventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashchenko
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Patent number: 7375394Abstract: The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal, multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.Type: GrantFiled: July 6, 2005Date of Patent: May 20, 2008Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 7375395Abstract: The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via the filling (6) of a body trench (5) to a highly doped substrate (2) via a conductive connection (15).Type: GrantFiled: September 22, 2005Date of Patent: May 20, 2008Assignee: Infineon Technologies Austria AGInventor: Jenö Tihanyi
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Patent number: 7375396Abstract: The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate insulating layer is formed of a filtering oxide layer having a thickness of 1 to 20 ?.Type: GrantFiled: December 23, 2004Date of Patent: May 20, 2008Assignee: Samsung SDI Co., Ltd.Inventors: Keun-Soo Lee, Byoung-Keon Park
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Patent number: 7375397Abstract: There is provided a semiconductor device in which the characteristic variations of a transistor and the degradation of a gate oxide layer are reduced during a WP process and a method for manufacturing the same. The semiconductor device includes a semiconductor chip having an SOI transistor. The SOI transistor includes a semiconductor layer comprising device isolating regions, a channel region, and diffusion regions that sandwich the channel region therebetween. The semiconductor layer is formed on a support substrate via a first insulating layer. A gate electrode is formed on the channel region of the semiconductor layer via a second insulating layer. The semiconductor chip has, on the first surface, a first electrode pad electrically connected to the SOI transistor and a second electrode pad electrically connected to the support substrate.Type: GrantFiled: May 3, 2006Date of Patent: May 20, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshinori Shizuno
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Patent number: 7375398Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.Type: GrantFiled: May 26, 2005Date of Patent: May 20, 2008Assignee: IMPINJ, Inc.Inventors: Bin Wang, Chih-Hsin Wang