Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract: A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip die (16) and electrically connected to the base carrier (12) with a plurality of insulated wires (20). A mold compound (36) is formed over the first and second dice and one surface of the base carrier.

Abstract: A leadless semiconductor package mainly includes a semiconductor device securely attached to an upper surface of a die pad by solder paste and a plurality of leads arranged about the periphery of the die pad. The thickness of the leads and the die pad are within a range of 10 to 20 mils. The semiconductor device is electrically coupled to one of the leads. A package body is formed over the semiconductor device and the leads in a manner that the lower surfaces of the die pad and the leads are exposed through the package body. Preferably, the first semiconductor device is electrically coupled to one of the leads by at least one heavy gauge aluminum wire. The present invention further provides a method of producing the semiconductor package described above.

Abstract: An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.

Abstract: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package.

Abstract: A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask are removed. A laser is applied to form a laser hole in the patterned mask to expose a portion of the conductive layer and the laser hole substantially corresponds to a channel region of the predetermined TFT area. The exposed conductive layer is etched to form source and drain electrodes on opposite sides of the channel region.

Abstract: The present method of forming a silicon oxide layer comprises providing two frequency excitation plasma CVD device which comprises a high frequency electrode, a susceptor electrode, and two matching box for impedance matching between the electrodes and a power supply, wherein one side electrode constituting a tuning condenser of a matching box toward the high frequency electrode is the high frequency electrode; placing a substrate on the susceptor electrode; applying high frequency electric power on the high frequency electrode and the susceptor electrode respectively; and forming a silicon oxide layer on the substrate by generating plasma with using a reaction gas of which main reaction gas is a mixing gas of monosilane and nitrous oxide.

Abstract: A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in t

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210) with a crystalline semiconductor layer (216). By forming first gate electrodes (151) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

Abstract: Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having the SiGe film formed thereon, selectively etching the SiGe film, embedding a dielectric material into a portion where the SiGe film is removed, forming a stepped profile on the silicon film by etching a predetermined portion of the silicon film such that the bit-line node portion is included in the stepped profile, and forming a gate on the silicon film having the stepped profile formed therein such that the gate overlaps the stepped profile. The dielectric pad prevents the bit-line junction from spreading downward upon operation of the gate, thereby enhancing a punch-through phenomenon.

Abstract: A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.

Abstract: A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.

Abstract: An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

Abstract: Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a polysilicon layer of a container formed in a substrate. An oxide cap may be formed on the top portion of the container.

Abstract: A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent cells. The doped region is formed by an implant in which the select gates of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.

Abstract: A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Nd in the JFET region of length Lacc and net active doping concentration Na in the P-body regions of length Lbody so that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1 is about 0.6?k1?1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.

Abstract: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment of the present invention, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

Abstract: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.

Abstract: A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

Abstract: In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover layer is patterned using a photolithographic mask so that the first region is uncovered and the second region remains covered by the first cover layer. The first region is uncovered, a second cover layer is applied to the uncovered first region, and the first cover layer is removed so that the second region is uncovered. The uncovered second region is then doped.

Abstract: To improve the refresh characteristics of a semiconductor device, a gate oxide layer comprising a first oxide layer and a second oxide layer are formed on the substrate. A portion of the second oxide layer is isotropically etched using a photoresist layer pattern. A gate is formed by sequentially forming a gate conductive layer and a hard mask layer on the second oxide layer, and sequentially etching the hard mask layer, the gate conductive layer, the second oxide layer and the first oxide layer. Due to isotropic etching of the second oxide layer, the portion of the gate oxide layer corresponding to the center portion of the channel gate is thinner than the other portion of the gate oxide layer correspond to an edge of the channel gate.

Abstract: A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second spacer is formed at the foot of the first spacer. A tilt-angle pre-amorphization implant (PAI) is conducted to form an amorphized layer next to the second spacer. A metal layer is then sputtered on the amorphized layer. The metal layer reacts with the amorphized layer to form a metal silicide layer thereto.

Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.

Abstract: A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the first ion diffusion region serving as an anode of the junction varactor; and a second ion diffusion region with a second conductivity type located in the ion well at the other side of the gate finger, the second ion diffusion region serving as a cathode of the junction varactor. In operation, the gate of the junction varactor is biased to a gate voltage VG that is not equal to 0 volt.

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract: Disclosed is a method for manufacturing a semiconductor device, comprising forming an insulating film above a semiconductor substrate having an element formed thereon, forming an anti-reflection layer that is impermeable to hydrogen on the insulating film, the anti-reflection layer comprising a layer formed of at least one material selected from the group consisting of silicon nitride, silicon oxynitride, chromium oxide, CrOxFy, CrAlxOy, AlSixOy, ZrSixOy, silicon oxycarbide, carbon, chromium nitride, titanium nitride, tantalum nitride, aluminum nitride, TiAlxNy, TaAlxNy, TiSixNy, AlSixNy (where x and y denote the component ratio), and silicon carbide, forming a resist pattern on the anti-reflection layer, forming a hole in the insulating film with the resist pattern used as a mask, burying a conductive material in the hole to form a plug, removing the resist pattern, and forming a ferroelectric capacitor above the anti-reflection layer.

Abstract: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane.

Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

Abstract: Provided are a bonding substrate whose defective bonding portion in a peripheral region of an active layer has been removed by a polishing applied thereto after a surface grinding, a manufacturing method of the same substrate and wafer periphery pressing jigs. After the surface grinding, a periphery removing polishing is applied from an active layer wafer side of a bonding wafer so that a peripheral region of the active layer may be removed and a central region thereof may be left un-removed. Consequently, a periphery grinding and a periphery etching according to the prior art can be eliminated. Furthermore, an etch pit on a circumferential face of a wafer which could be caused by the periphery etching and a contamination or a scratching in an SOI layer which could be caused by a silicon oxide film left un-ground-off can be prevented, thereby achieving high yield and low cost.

Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Abstract: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are laminated to form a stack of nitride semiconductor on the first face of the substrate 1. A first bonding layer including more than one metal layer is formed on the p-type nitride semiconductor layer 8. A supporting substrate having a first and second face has a thermal expansion coefficient that is larger than that of the nitride semiconductor and is equal or smaller than that of the substrate 1 for growing nitride semiconductor. A second bonding layer including more than one metal layer is formed on the first face of the supporting substrate. The first bonding layer 9 and the second bonding layer 11 are faced with each other and, then, pressed with heat to bond together.

Abstract: A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the dielectric layer and the semiconductor layer.

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Abstract: Terminating the ends of passive electronic components entails applying a laser-removable coating to one or both of the opposed major surfaces of a substrate. A UV laser beam having a spot size and an energy distribution sufficient to remove the laser-removable coating from multiple selected regions of at least one of the major surfaces to which the laser-removable coating was applied is directed for incidence on the substrate. Relative motion between the UV laser beam and substrate effects removal of sufficient amounts of laser-removable coating to expose the multiple selected regions. The substrate is then broken into multiple rowbars or individual components, each of which includes side margins. An electrically conductive material is applied to the side margins to form electrically conductive interconnects between portions of the side margins spatially aligned with the multiple selected regions.

Abstract: In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film.

Abstract: Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.

Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third opening are in communication with each other. A portion of the first opening, the second opening, and the third opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. A method of forming semiconductor components, semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract: A method for manufacturing a MOSFET equipped with a silicide layer over shallow source and drain junctions without leakage generation is provided. By restricting the temperature of manufacturing steps after the silicide formation below a critical temperature Tc, which is defined below as a function of a junction depth Dj from 20 nm to 60 nm, leakage generation is practically suppressed. Tc = a × Dj + b , ? where a = 6.11 ? ( 20 < Dj ? 26 ) = 1.60 ? ( 26 < Dj ? 60 ) , ? b = 290.74 ? ( 20 < Dj ? 26 ) = 408 ? ( 26 < Dj ? 60 ) , Dj is a junction depth (nm) measured from the lower surface of the silicide layer, and Tc is a critical temperature (° C.) during a heat treatment.

Abstract: A metal electroplating process of an electrically connecting pad structure of a circuit board and structure thereof are proposed. First, a circuit board with a patterned circuit layer formed on at least one surface thereof is provided, wherein the circuit layer defines a plurality of electrically connecting pads and electroplating lines connected to the electrically connecting pads. Then, a patterned resist layer is formed on the circuit layer of the circuit board with the electroplating lines being covered by the patterned resist layer and the electrically connecting pads being exposed from the patterned resist layer. Subsequently, an electroplating process is performed so as to form a metal protection layer on the electrically connecting pads exposed from the patterned resist layer. Then, the resist layer is removed and a solder mask layer is formed on the circuit board.

Abstract: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a plurality of etch stop layers (42, 44, 46) are formed, one each between adjacent etalon material layers (32, 34, 36, 38). A photoresist is patterned to create an opening (54) over the top etalon material layer (38) and an etch (56) is performed down to the top etch stop layer (46). An oxygen plasma (58) may be applied to convert the etch stop layer (46) within the opening (54) to silicon dioxide (57). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (82, 84, 86, 88). A second mirror (72) is then formed on each of the levels (82, 84, 86, 88).

Abstract: Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material.