Abstract: A light emitting device package capable of achieving an enhancement in light emission efficiency and a reduction in thermal resistance, and a method for manufacturing the same are disclosed. The method includes forming a mounting hole in a first substrate, forming through holes in a second substrate, forming a metal film in the through holes, forming at least one pair of metal layers on upper and lower surfaces of the second substrate such that the metal layers are electrically connected to the metal film, bonding the first substrate to the second substrate, and mounting at least one light emitting device in the mounting hole such that the light emitting device is electrically connected to the metal layers formed on the upper surface of the second substrate.

Abstract: A Trench MOSFET includes a trench region (16) provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate (1), a P-type semiconductor epitaxial layer (2), an N-type semiconductor body region (3), and a P-type semiconductor source diffusion (7). The substrate (1), the epitaxial layer (2), the body region (3), and the source diffusion (7) are adjacently formed in this order. A P-type semiconductor channel region (4) formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region (16). This facilitates carrier movement in the channel region 4, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.

Abstract: A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

Abstract: A back illuminated imaging device 1 comprises a plurality charge blocking regions 19 which are arranged on a front surface 12 side, embedded in CCD charge transferring paths 21, and in which a first thickness T1 measured from the front surface 12 of first portions 19a extending along the CCD charge transferring paths 21 is larger than a first thickness T2 of second portions 19b extending along channel stops 20.

Abstract: A method of manufacturing a photodiode sensor and an associated charge transfer transistor includes forming an insulation region on a substrate, forming the diode on a first side of the insulation region with the diode being self-aligned on the insulation region, and replacing the insulation region by a gate of the charge transfer transistor. The invention has particular utility in the manufacture of CMOS or CCD image sensors.

Abstract: A semiconductor device includes an active region formed on a semiconductor substrate, an element isolation region formed on the semiconductor substrate so as to surround the active region, and a gate electrode formed on the active region. A region that causes tensile stress so as to improve carrier mobility in the active region is provided in the element isolation region.

Abstract: A multiple, independent top gated field effect transistor having an improved electron injection and reduced gate induced barrier lowering effects, and a method that allows for the destruction of metallic carbon nanotubes positioned between the source and drain of a top multi-gate transistor are provided. The field effect transistor comprises at least one carbon nanotube (14) coupled between the first and second electrodes (16, 18) and a first gate material (24) formed over a portion of the at least one carbon nanotube (14) and spaced apart from the first and second electrodes (16, 18). A dielectric material (32) is conformally coated on the first and second electrodes (16, 18), the at least one carbon nanotube (14), and the first gate material (24). A second gate material (36) is conformally coated on the dielectric material (32).

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate insulating layer on a semiconductor substrate, forming a gate electrode on the gate insulating layer, forming spacers on sidewalls of the gate electrode, forming impurity regions in the semiconductor substrate using the gate electrode and the spacers as masks, forming a capping layer over the semiconductor substrate to cover the gate electrode and the impurity regions, the capping layer having a compressive stress, and implanting impurity ions to portions of the capping layer corresponding to the impurity regions, such that the portions of the capping layer have a local tensile stress.

Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes: forming a gate insulating layer on a semiconductor substrate having an isolation layer formed therein, forming a gate electrode on the gate insulating, implanting low-concentration impurity ions on the semiconductor substrate at a first side of the gate electrode to form a lightly doped drain (LDD) region, forming a low-concentration impurity region on the semiconductor substrate at a second side of the gate electrode, implanting impurities into the low-concentration impurity region to form a photodiode, and forming micro pits on a top surface of the photodiode using a wet etching process.

Abstract: A CMOS image sensor and method of fabricating the same are disclosed. The method comprises forming a plurality of polysilicon patterns on a silicon epitaxial layer which correspond to a plurality of photodiodes in a dummy pixel area, depositing a metal with a high melting point metal on the plurality of polysilicon patterns using a photoresist in an etching process, forming a silicide layer of the high melting point metal by removing the photoresist and then performing an ashing and rapid annealing process, sequentially forming a device protecting layer and a planarization layer on the silicon epitaxial layer and silicide layer, and forming a microlens on the planarization layer which corresponds to the silicide layer.

Abstract: A method of manufacturing an image sensor that may restrain the oxidization of a pad. A method of manufacturing an image sensor may include at least one of the following steps: Forming a photodiode structure including a pixel in an active region of a semiconductor substrate. Forming a conductive pad electrically connected the pixel in a peripheral region of the semiconductor substrate, where the peripheral region at least partially surrounds the active region. Forming a passivation layer with an opening exposing the pad on and/or over the photodiode structure. Covering the exposed pad with an etching prevention layer. Forming a color filter on and/or over the passivation layer corresponding to the pixel. Forming a microlens on and/or over the color filter. Removing the etching prevention layer from the pad.

Abstract: A vertical type CMOS image sensor and a method of manufacturing the same including a P+-type red photodiode formed in a semiconductor substrate, a first silicon epilayer formed over the semiconductor substrate and including a P+-type green photodiode formed therein, a second silicon epilayer formed over the first silicon epilayer and including a P+-type blue photodiode formed therein; a first P+-type plug formed in the first silicon epilayer and electrically connected to the P+-type red photodiode, and a second P+-type plug in the second silicon epilayer which is electrically connected to the P+-type green photodiode.

Abstract: According to the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of forming an insulating film on a silicon substrate, forming a first conductive film on the insulating film, forming an aluminum crystal layer on the first conductive film, forming a ferroelectric film containing Pb(ZrxTi1-x)O3 (where 0?x?1) on the aluminum crystal layer, forming a second conductive film on the ferroelectric film, and patterning the first conductive film, the ferroelectric film, and the second conductive film to form a capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode which are laminated sequentially.

Abstract: A memory device, comprising a semiconductor substrate with at least one storage cell, the storage cell comprising a storage element and a selection transistor, wherein the memory device further comprises a storage element contact assigned to the storage cell, the storage element contact extending from the selection transistor to the storage element along an axis that at least partially runs obliquely with respect to a direction perpendicular to the substrate surface.

Abstract: A method for fabricating a semiconductor device having a capacitor is provided. The method includes forming an isolation layer on a substrate on which a capacitor region and a transistor region are defined, forming a trench in the isolation layer, sequentially forming a first polysilicon layer, a dielectric layer, and a second polysilicon layer on an entire surface of the substrate including the trench, forming a capacitor in the trench by performing a chemical mechanical polishing process until an upper surface of the isolation layer is exposed, forming a first photoresist pattern to expose the transistor region, removing the second polysilicon layer and the dielectric layer using the first photoresist pattern as a mask, forming a second photoresist pattern in the transistor region, and forming a gate electrode by selectively removing the first polysilicon layer in the transistor region using the second photoresist pattern as a mask.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Abstract: An integrated MIS capacitor structure comprises a high quality factor shunt capacitor. The integrated MIS capacitor is configured with a large periphery and an external ground via to mitigate resistive losses in the bottom plate of the MIS shunt capacitor.

Abstract: A CMOS transistor comprises a substrate with a gate electrode arranged thereon between source and drain regions. A capacitor is provided on the gate electrode and a voltage applied to the gate electrode is dropped across a stack, including the gate electrode and the capacitor.

Abstract: MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise heavily doped semiconductor material of the first conductivity type (e.g., p+-type), and a Schottky junction formed between the gate and contact regions. The Schottky junction may be formed by spacing the contact regions away from the gate electrode and siliciding the substrate surface. The gate electrode may be formed from semiconductor material of a second conductivity type (e.g., n-type) opposite to the first conductivity type, thus changing the flat band voltage of the MOS varactor and shifting accumulation and depletion regime of the CV characteristic curve in one bias regime, such as the negative bias regime.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

Abstract: A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.

Abstract: Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.

Abstract: A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.

Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

Abstract: Data storage device, comprising: a stack of layers formed by an alternation of first layers with a conductivity of less than approximately 0.01 (?·cm)?1 and second layers with a conductivity greater than approximately 1 (?·cm)?1, a plurality of columns disposed in the stack of layers, and passing through each layer in this stack. Each of the columns is formed by at least one portion of semiconductor material surrounded by least one electrical charge storage layer electrically insulated from the portion of semiconductor material and from the stack; means of applying voltage to the terminals of the columns comprising a network of moving microspikes.

Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

Abstract: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the trenches. Individual charge storage devices are therefore field coupled with two control gates, one on either side.

Abstract: Provided are a nonvolatile memory device and a method of operating the same, which have increased operation reliability and which facilitate increased integration. The nonvolatile memory device may include a semiconductor substrate, and at least one charge storage layer may be provided on a semiconductor substrate. At least one control gate electrode may be provided on the at least one charge storage layer. At least one first auxiliary gate electrode may be disposed on one side of and apart from the at least one charge storage layer and isolated from the semiconductor substrate.

Abstract: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate, a gate insulating layer, and a control gate over the tunnel oxide layer. Then, a sidewall oxide layer is formed on a gate region. Next, a fluorine plasma ion implantation process is performed on the sidewall oxide layer. Then, a nitride layer is deposited on the sidewall oxide layer. Next, an etch process is performed to form spacer insulating layers.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.

Abstract: A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an impurity doped region formed at a second depth within the substrate and between the first and second gate stacks, the first depth being lower than the second depth.

Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at least one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

Abstract: A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.

Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.

Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.