Abstract: A semiconductor memory device according to the present invention has a storage unit that includes an interlayer insulation film, a lower electrode layer embedded in the interlayer insulation film, and a recording layer and an upper electrode layer provided on the interlayer insulation film. When a predetermined current is passed to the storage unit, the recording layer is heated by substantially exceeding a melting point, and a cavity is formed near the interface between the recording layer and the lower electrode layer. As a result, the recording layer is physically separated from the lower electrode layer, and no current flows through the storage unit. When the recording layer is physically separated from the lower electrode layer, these layers cannot be returned to the contact state again. Therefore, information can be stored irreversibly.

Abstract: A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a characteristic change element and a vertical type memory cell transistor connected in parallel to each other, a plurality of second memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in an X direction with respect to the first memory cell array, and a plurality of third memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in a Y direction with respect to the first memory cell array, wherein a gate voltage is applied to gates of the vertical type memory cell transistors of the first to third memory cell arrays in a same layer.

Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.

Abstract: Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.

Abstract: A light emitting device with an increased light extraction efficiency includes a two-dimensional periodic structure in a surface thereof and has two layers that together form an asymmetric refractive index distribution with respect to the active layer, which is in between the two layers. The light emitting device includes a substrate layer, a first layer, an active layer and a second layer that are stacked sequentially. The first layer includes at least one layer, including a semiconductor cladding layer of a first conductivity type. At least one layer of the first layer has a refractive index that is lower than a refractive index of the active layer and lower than a refractive index of a layer of the second layer that is adjacent to the active layer. Each constituent layer of the second layer has a refractive index that is lower than the refractive index of the active layer.

Abstract: The present invention relates to a III-nitride compound semiconductor light emitting device comprising an active layer with the multi-quantum wells interposed between an n-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z?1) layer and a p-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z<1) layer, wherein the active layer comprises an alternate stacking of a quantum-well layer made of InxGa1-xN(0.05<x<1) and a sandwich barrier layer, the sandwich barrier layer comprising a first outer barrier layer of InaGa1-aN(0<a<0.05), a middle barrier layer of AlyGa1-yN(0<y<1) formed on the first outer barrier layer and a second outer barrier layer of InbGa1-bN(0<b<0.05) formed on the middle barrier layer, thereby a high-efficiency/high-output light emitting device with high-current and high-temperature properties can be obtained, and it is possible to easily achieve a high-efficiency green light emission at a wavelength equal to or over 500 nm, and high-efficiency near UV light emission.

Abstract: The present invention provides a III-nitride compound semiconductor light emitting device comprising an active layer (30) which emits light and is interposed between a lower contact layer (20) made of n-GaN and an upper contact layer (40) made of p-GaN, in which a sequential stack of a lattice mismatch-reducing layer L3 made of InxGa1-xN, an electron supply layer L4 made of n-GaN or n-AlyGa1-yN and a crystal restoration layer L5 made of InzGa1-zN is interposed between the lower contact layer and the active layer, and further comprising an electron acceleration layer L1 made of n-GaN or undoped GaN and a heterojunction electron barrier-removing layer L2, thereby the lattice mismatch between the lower contact layer (20) and the active layer (30) can be reduced.

Abstract: A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.

Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.

Abstract: Disclosed herein is an electronic device of a three-terminal type including, a control electrode, first and second electrodes, and an active layer provided between the first and second electrodes so as to face the control electrode with an insulating layer interposed therebetween, the active layer being formed from an aggregate of a composite material formed from inorganic semiconductor fine particles covered with a protective layer, the protective layer including an alkyl chain having, at one end thereof, a functional group bonded to an inorganic semiconductor fine particle and further having an organic semiconductor molecule bonded to the other end thereof.

Abstract: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second dielectric layer are solvable and substantially without interface therebetween. A second electrode is formed on the hybrid multi-layers.

Abstract: Light-emitting elements having high emission efficiency and long lifetime can be provided. By forming light-emitting devices including the light-emitting elements, the light-emitting devices having low power consumption and long lifetime can be provided. A light-emitting device comprises a light-emitting element including a light-emitting layer between a first electrode and a second electrode. The light-emitting layer includes a first organic compound having a hole-transporting property, a second organic compound having an electron transporting property, and an organometallic complex. A central metal of the organometallic complex is an element belonging to one of Group 9 and Group 10, and a ligand of the organometallic complex is a ligand having a pyrazine skeleton.

Abstract: A method for hermetically sealing a device without performing a heat treatment step and the resulting hermetically sealed device are described herein. The method includes the steps of: (1) positioning the un-encapsulated device in a desired location with respect to a deposition device; and (2) using the deposition device to deposit a sealing material over at least a portion of the un-encapsulated device to form a hermetically sealed device without having to perform a post-deposition heat treating step. For instance, the sealing material can be a Sn2+-containing inorganic oxide material or a low liquidus temperature inorganic material.

Abstract: A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor.

Abstract: A semiconductor device having a test pattern for measuring epitaxial pattern shift is provided. The test pattern includes a semiconductor substrate having a first pattern formed therein; a first impurity region formed in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a second pattern formed therein, wherein the second pattern corresponds to the first pattern; and a second impurity region formed in the epitaxial layer, the second impurity region in electrical contact with the first impurity region.

Abstract: A semiconductor device wherein an electrode pad to be contacted a test probe for performing probe testing, a bonding area mark for defining a bonding area which performs wire boding on the electrode pad, and a probe area mark for defining a probe repair area for repairing or replacing the test probe for the electrode pad.

Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

Abstract: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is eliminated using the carbide precipitates, and the semiconductor element is formed using the doping atoms.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.

Abstract: The present invention is to reduce display unevenness in a display device caused by dispersion of energy density of a laser beam. It is difficult for a periodical pattern to be recognized as display unevenness in display image. The display device of the present invention can visually reduce the display unevenness in the display image by utilizing the visual advantage described above. The display device can be manufactured using a TFT array substrate in which electric characteristic of plural TFTs arranged in a line in the minor axis direction of an linear shaped laser beam periodically fluctuates depending on the place in which each TFT is formed.

Abstract: A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

Abstract: A display panel includes a first substrate, a second substrate and a spacer. The first substrate includes a gate line, a data line crossing the gate line to define a pixel area, and a storage electrode formed in the pixel area. The second substrate is coupled with the first substrate and includes a first black matrix corresponding to the storage electrode. The spacer is interposed between the first and second substrates to allow the first and second substrates are spaced apart from each other. Thus, an aperture ratio of the display panel may be improved and a manufacturing cost of the display panel may be reduced.

Abstract: A method forms a plurality of pillars, the pillars arranged such that positions of the pillars control flow of a liquid, the plurality of pillars forming a fluidic template, the method dispenses the liquid into the fluidic template such that the liquid assumes a shape corresponding to the fluidic template, and dries the liquid to form at least a portion of a patterned structure. Another method forms a multi-layer printed structure by forming a plurality of pillars, the pillars arranged such that positions of the pillars control flow of a liquid, the plurality of pillars forming a fluidic template, dispensing a first liquid into a first region containing the pillars such that liquid spreads only in the first region, dispensing a second liquid into a second region such that liquid spreads in the second region and partially into the first region, forming an overlap region, an extent of the overlap region controlled by the positions of the pillars.

Abstract: According to an embodiment, there is provided a thin film transistor substrate divided into a display area displaying the image and a non-display besides the display area, the thin film transistor substrate comprising: a common voltage line for MPS (mass production system) test and a grounding line for MPS (mass production system) test formed at the edge of the non-display area in parallel; an insulating layer covering the common voltage line for MPS (mass production system) test and the grounding line for MPS (mass production system) test; and an electrode layer formed on the insulating layer corresponded to the common voltage line for MPS (mass production system) test and the grounding line for MPS (mass production system) test. Thus, the present invention provides a thin film transistor substrate and a fabricating method thereof for minimizing defects due to static electricity.

Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

Abstract: The invention provides a connection structure including: a first electro-conductive film that is formed on a substrate; an insulation film that is formed on the first electro-conductive film, an end surface of the insulation film facing in a direction in which an end surface of the first electro-conductive film faces; and a second electro-conductive film that extends from the upper surface of the insulation film to reach the end surface of the first electro-conductive film across the end surface of the insulation film, the second electro-conductive film being electrically connected to the first electro-conductive film via the end surface of the first electro-conductive film.

Abstract: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive layer. The width change part is formed away from a region of at least one of the conductive layers that crosses a neighboring conductive layer. The present invention also provides a flat panel display device that includes the electronic device described above and manufactured in accordance with the principles of the present invention. The electronic device of the present invention may comprise a thin film transistor.

Abstract: Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming a first interlayer dielectric (ILD) layer on the p-type and n-type semiconductors, exposing top surfaces of the n-type and p-type semiconductors, forming a third silicide layer on one semiconductor on each of the first and second silicide layers, forming a second ILD layer on the third silicide layer, and etching the second and first ILD layers to form contact holes exposing top surfaces of the first and second silicide layers.

Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.

Abstract: A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x?3 and Y?4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

Abstract: In accordance with embodiments of the invention, strain is reduced in the light emitting layer of a III-nitride device by including a strain-relieved layer in the device. The surface on which the strain-relieved layer is grown is configured such that strain-relieved layer can expand laterally and at least partially relax. In some embodiments of the invention, the strain-relieved layer is grown over a textured semiconductor layer or a mask layer. In some embodiments of the invention, the strain-relieved layer is group of posts of semiconductor material.

Abstract: A photodiode array PD1 comprises an n-type semiconductor substrate one face of which is an incident surface of light to be detected; a plurality of pn junction-type photosensitive regions 3 as photodiodes formed on the side of a detecting surface that is opposite to the incident surface of the semiconductor substrate; and a carrier capturing portion 12 formed between adjacent photosensitive regions 3 from among the plurality of photosensitive regions 3 on the detecting surface side of the semiconductor substrate. The carrier capturing portion 12 has one or plurality of carrier capturing regions 13 respectively including pn-junctions, arranged at intervals. Thereby can be realized a semiconductor photodetector and a radiation detecting apparatus which can favorably restrain crosstalk from occurring.

Abstract: The present invention relates to light emitting diodes, LEDs. In particular the invention relates to a LED comprising a nanowire as an active component. The nanostructured LED according to the embodiments of the invention comprises a substrate and at an upstanding nanowire protruding from the substrate. A pn-junction giving an active region to produce light is present within the structure. The nanowire, or at least a part of the nanowire, forms a wave-guiding section directing at least a portion of the light produced in the active region in a direction given by the nanowire.

Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure having a N-sided polygonal cross-section where N is an integer equal to or larger than 6. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Abstract: In accordance with embodiments of the invention, a III-nitride structure includes a plurality of posts of semiconductor material corresponding to openings in a mask layer. Each post includes a light emitting layer. Each light emitting layer is disposed between an n-type region and a p-type region. A first light emitting layer disposed in a first post is configured to emit light at a different wavelength than a second light emitting layer disposed in a second post. In some embodiments, the wavelength emitted by each light emitting layer is controlled by controlling the diameter of the posts, such that a device that emits white light without phosphor conversion may be formed.

Abstract: The present invention provides a bonding structure of circuit substrates and an instant circuit inspection method thereof. The contact pad design of the bonding structure has an instant inspection ability of circuit connection in bonding two circuit substrates. In two bonded circuit substrates, the signal inputted at the circuit part passes the conductive particles to the first contact pad, and then passes the conductive particles again to the detecting part from the first contact pad. Therefore, measuring the output signal can inspect the reliability of the circuit connection of the bonded circuit substrates. If the output signal is the same as the input signal, the bonding structure between the first contact pad and the circuit part is validated, or, if not, the bonding structure is invalidated.

Abstract: The present invention is directed to edge-emitting light-emitting diode arrays, a process to prepare the edge-emitting light-emitting diode arrays, and process products prepared by the process.

Abstract: A lead frame for a transparent and mirrorless light emitting diode (LED). The LED is comprised of a plurality of III-nitride layers, including an active region that emits light, wherein all of the layers except for the active region are transparent for an emission wavelength of the light, such that the light is extracted effectively through all of the layers. A lead frame supports the III-nitride layers, wherein the III-nitride layers reside on a transparent plate in the lead frame, and the light emitted from the III-nitride layers is transmitted through the transparent plate. A metal mask may be formed on the transparent plate for electrically connecting the III-nitride layers to a lead frame.

Abstract: An optical communication semiconductor device including: a first light emitting layer composed of a semiconductor; and a second light emitting layer which is laid on or above the first light emitting layer and composed of a semiconductor capable of emitting light having a emission peak at a wavelength different from that of light emitted by the first light emitting layer.

Abstract: A light emitting device including a carrying element having two electric conductors connectable to a power source, a light emitting element disposed on the carrying element and electrically connected to the two electric conductors, and at least one correction element electrically connected to the light emitting element, wherein the light emitting element is adapted to provide a light source upon connection of the two electric conductors with the power source, and the at least one correction element allows the light emitting element to have functions of temperature compensation, voltage correction, or surge absorption.

Abstract: The present invention provides a semiconductor light emitting device and a method for manufacturing the same. The semiconductor device comprises (i) a semiconductor layer with convex portions in a shape selected from a cone and a truncated cone and (ii) electrodes, wherein in the case of the convex portions with the shape of the truncated cone, the convex portions has a height of from 0.05 to 5.0 ?m and a bottom base diameter of from 0.05 to 2.0 ?m; in case of the convex portions with the shape of the cone, the convex portions has a height of from 0.05 to 5.0 ?m and a base diameter of from 0.05 to 2.0 ?m. A method for manufacturing a semiconductor light emitting device comprising the steps of (a) growing a semiconductor layer on a substrate, (b) forming on the semiconductor layer a region having particles with an average particle diameter of 0.

Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.

Abstract: In a method of making a semiconductor light generating device, a GaN-based semiconductor portion is formed on a GaN or AlGaN substrate. The GaN-based semiconductor portion includes a light generating film. An electrode film is formed on the GaN-based semiconductor film. A conductive substrate is bonded to a surface of the electrode film using a conductive adhesive. After bonding the conductive substrate, the GaN or AlGaN substrate is separated from the GaN-based semiconductor portion to form the semiconductor light generating device.

Abstract: A nitride semiconductor device used chiefly as an LD and an LED element. In order to improve the output and to decrease Vf, the device is given either a three-layer structure in which a nitride semiconductor layer doped with n-type impurities serving as an n-type contact layer where an n-electrode is formed is sandwiched between undoped nitride semiconductor layers; or a superlattice structure of nitride. The n-type contact layer has a carrier concentration exceeding 3×1010 cm3, and the resistivity can be lowered below 8×10?3 ?cm.

Abstract: A ceramic body is disposed in a path of light emitted by a light source. The light source may include a semiconductor structure comprising a light emitting region disposed between an n-type region and a p-type region. The ceramic body includes a plurality of first grains configured to absorb light emitted by the light source and emit light of a different wavelength, and a plurality of second grains. For example, the first grains may be grains of luminescent material and the second grains may be grains of a luminescent material host matrix without activating dopant.

Abstract: A red phosphor with excellent luminescent characteristics, and a light emitting device that uses this phosphor are provided. The phosphor is a nitride phosphor that is activated by europium, and absorbs light from the near ultraviolet range to the blue range to emit red light. The nitride phosphor has the following general formula, MwAlxSiyBzN((2/3)w+x+(4/3)y+z):Eu2+ where M is at least one element selected from the group consisting of Mg, Ca, Sr and Ba. In the general formula, w, x, y and z fall within the following ranges. 0.056?w?9, x=1, 0.056?y?18, and 0.0005?z?0.5 In addition, the mean particle diameter of the nitride phosphor is preferably not less than 2 ?m and not more than 15 ?m.

Abstract: The light-radiating semiconductor component has a radiation-emitting semiconductor body and a luminescence conversion element. The semiconductor body emits radiation in the ultraviolet, blue and/or green spectral region and the luminescence conversion element converts a portion of the radiation into radiation of a longer wavelength. This makes it possible to produce light-emitting diodes which radiate polychromatic light, in particular white light, with only a single light-emitting semiconductor body. A particularly preferred luminescence conversion dye is YAG:Ce.

Abstract: A transparent light emitting diode (LED) includes a plurality of III-nitride layers, including an active region that emits light, wherein all of the layers except for the active region are transparent for an emission wavelength of the light, such that the light is extracted effectively through all of the layers and in multiple directions through the layers. Moreover, the surface of one or more of the III-nitride layers may be roughened, textured, patterned or shaped to enhance light extraction.

Abstract: A light-emitting apparatus includes a package including a support having a central section and a peripheral section around the central section. The central section is raised upwardly from the peripheral section, providing a pedestal for supporting a light-emitting device. A light-emitting device secured on an upper surface of the pedestal and has electrodes. Electrically conductive members are provided on a peripheral region of the package and electrically connected to the electrodes of the light-emitting device. A color conversion layer covers the light-emitting device. A light-transmitting member is formed in the package, sealing at least the light-emitting device together with the color conversion layer. The pedestal has its side surface at least partially exposed from the color conversion layer.

Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.