Abstract: A semiconductor memory device is effectively able to adjust operation time for on-die termination (ODT). The semiconductor memory device includes a latency control unit, a control signal generating unit, a trimming control unit, and a termination circuit. The latency control unit produces an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency. The control signal generating unit produces control signals to control a change of waveform of the ODT driving enable signal. The trimming control unit changes the waveform of the ODT driving enable signal in response to the control signals, thereby outputting a ODT driving signal. The termination circuit connects a termination resistance to an impedance adjusting node in response to the ODT driving signal.

Abstract: A plurality of transistor pairs of Pch and Nch transistors are connected in series between VDD and GND. An I/O terminal is connected to each connection point of the transistor pairs. Two transistor pairs constitute one transistor set, in which each of two Pch transistors and two Nch transistors have the same on-resistance. In input mode, one of the two transistor pairs in a first set is turned on, and a transistor pair of a second or later set is selectively turned on. In output mode, two Pch transistors or two Nch transistors of the first set are turned on, and a transistor of the second or later set is selectively turned on.

Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.

Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.

Abstract: Finite state machines are provided to run instances of user-defined routines within a computing system. The finite state machines and updates to the finite state machines are user-defined and are checked for compliance with one or more prescribed schemas by a finite state machine engine. Compliant finite state machine specifications are interpreted for the plurality of states and transitions that constitute the finite state machine. Requested instances of a finite state machine specification are initiated by the finite state machine engine, which creates proxies to monitor the current state of any given requested instance.

Abstract: A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

Abstract: A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.

Abstract: A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Abstract: In one embodiment, a zero crossing detector couples a plurality of comparators in parallel and operates at least a portion of the comparators at different time periods.

Abstract: An apparatus and method for automatically offsetting the linear deviation of a V/F converter, the offset adjust pin of which is connected to a fixed resistance, and the frequency output pin of which is connected to a microcontroller unit (MCU) via an opto-isolator, a standard V/F transfer function being pre-stored in the MCU, wherein standard frequencies F1 and F0 (i.e., two coordination points (V1, F1) and (V0, F0)) are output by the V/F converter, when V1 and V0 are input as standard voltages, and the MCU may detect an error status in the V/F converter, when the V/F converter obtains real output frequencies F1? and F0? from real input voltages V1 and V2, and standard coordination points (F1, K1) and (F0, K0) will be corrected to (F1?, K1) and (F0?, K0?), from which a transfer function of offsetting frequency down is obtained, when the MCU processes a frequency down procedure.

Abstract: A regenerative frequency divider device including a plurality of multipliers, each of which has a first input port, a second input port and an output port; a first combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the multipliers; and a second combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of multipliers. Further, a first output signal generated by the first combiner is coupled to the second input port of at least two of the multipliers; and a second output signal generated by the second combiner is coupled to the second input port of at least two of the multipliers such that a complex signal is fed back to the multipliers performing the down conversion process. The present invention divider CRD can achieve superior output noise floor of ?180 dBc/Hz at multi-GHz frequencies.

Abstract: Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

Abstract: Systems and methodologies are described that facilitate calibration of the loop bandwidth of a phase-locked loop (PLL). Calibration for the loop bandwidth of a PLL as described herein can be performed by optimizing the loop response of the PLL. Optimization of the loop response of the PLL can be achieved by modifying the value of a feedback counter of the PLL to induce a loop response at the PLL. The loop response of the PLL can be measured and compared to an ideal loop response. Based on this comparison, appropriate adjustments can be made to the PLL. Further, various techniques described herein facilitate calibration of a PLL by adjusting only parameters of a charge pump of the PLL without requiring individual control mechanisms for each element of the PLL, thereby improving PLL performance and manufacturing yield.

Abstract: A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the DLL being in a delay locked state; and an output enable signal generating unit for generating a plurality of output enable signals in response to the DLL clock and outputting a final output enable signal in response to the select signal.

Abstract: A DLL circuit includes a duty ratio correction unit that corrects the duty ratios of first and second delay clocks duty ratio to generate first and second correction clocks. A duty ratio detection unit detects the duty ratios of the first and second correction clocks, thereby generating first and second detection signals. A voltage comparison unit compares the levels of the first and second detection signals, thereby generating a first fine control signal. An operation mode setting unit generates a locking completion signal and a second fine control signal. A switching unit selectively transmits the first fine control signal or the second fine control signal to a delay control unit according to whether or not the locking completion signal is enabled.

Abstract: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.

Abstract: A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.

Abstract: A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corresponding n control pins; a current mirror circuit connected with the first output line to produce current mirror current from the current and output the current mirror current from a second output line; a first active element having a gate pin and an input pin, the gate pin is connected with the second output line, and the input pin is connected with the first voltage line; a second active element having a gate pin and an input pin, the gate pin is connected with the first output line, and the input pin is connected with the second voltage line; and an inverter circuit having third and fourth active elements connected in series between an output pin of the first active element and an output pin of the second active element.

Abstract: Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: There is a provided a dual mode clock generator that is applicable to a direct current-direct current converter of a power supply. The dual mode clock generator includes a frequency controller for controlling generation of charge and discharge; a current source unit for generating a charge, and generating a charge; a capacitor for charging a voltage according to the charge current generated by the current source unit; an oscillation controller for controlling switch-on or switch-off to charge and discharge the capacitor; a switch for controlling the charging and discharging of the capacitor through the ON or OFF control of the oscillation controller; and a current sink unit for generating a discharge current according to the second current in the first operation mode and generating a discharge current according to the third current and the fourth current in the second operation mode.

Abstract: A duty cycle correction circuit employing a sample and hold charge pumping method is disclosed. The duty cycle correction circuit includes a duty regulator which generates an output signal by regulating duty of an input signal in response to a regulation voltage, and a charge pump which generates the regulation voltage by inputting the output signal, wherein ripple of the regulation voltage is reduced by sampling the regulation voltage in a predetermined time interval.

Abstract: A signal generator and method for generating a plurality of signals of differing phase. The signal generator comprises a first single-phase frequency divider locked with a 90° phase shift that includes a first output port providing a first output signal and a first internal node providing a first internal signal, a second single-phase frequency divider locked with a 90° phase shift that includes a second output port providing a second output signal and a second internal node providing a second internal signal, and a first feedback circuit. The first feedback circuit coupled between either: first and second output ports or first and second internal nodes. The first feedback circuit configured to phase-lock first and second output signals 180° apart when the first feedback circuit is coupled between first and second outputs ports and phase-lock first and second internal signals 180° apart when the first feedback circuit is coupled between first and second internal nodes.

Abstract: A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.

Abstract: The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an outputs a response. The control circuit (12) causes a series of signals to be passed through the delay circuit (14), the series starting at a time that is time-continuously triggered by the start signal. Each successive signal in the series starts after a preceding signal has emerged from the delay circuit (12) and the series being terminated after a controlled number of more than one signal has been passed. The control circuit (12) supplies the response upon termination of the series. In one embodiment the series is realized by means of a handshake sequencing circuit (120) that generates a series of successive handshake transactions.

Abstract: A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

Abstract: A level shifter circuit that properly operates even when the power supply voltage is unstable. A level shifter circuit includes a first level shifter unit, a second level shifter unit, and a latch unit. In the first level shifter unit, a transistor is connected to a power supply line to generate drive voltage that is lower than a first power supply voltage. The first level shifter unit outputs complementary signals from the drive voltage. The output of the first level shifter unit is provided to the second level shifter unit. The second level shifter unit converts a complementary signal to a signal having a second power supply voltage. Based on this signal, a signal of the latch unit is switched.

Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bidirectional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.

Abstract: In an embodiment of the invention, power consumption savings are realized in an array design. Such an array design, for example and not limitation, can be used in integrated circuits, including microprocessors as memory arrays, and or instruction cache arrays. Power consumption savings are realized in the array design by utilizing multiple gating modes to allow an early gating signal, late resolving gating signals, and/or specific encodings of way select signals to gate all of the array or a portion of the array saving power when it is determined the array output is not needed.

Abstract: Headset connector systems and headset engaging connector systems are provided. Headset connector systems can include two or more headset connector contact regions. Headset engaging connector systems can include two or more headset engaging contact regions to provide at least one of power and data. The headset connector system or the headset engaging connector system can include switching circuitry electrically coupled to the respective contact regions. The switching circuitry can be operative to determine an interface orientation between the headset connector contact regions and the headset engaging contact regions. The switching circuitry can also be operative to selectively route received signals based on the determined interface orientation. At least a portion of the headset connector system or the headset engaging connector system can be magnetically attractive.

Abstract: A signal splitting apparatus which improves the noise figure (NF) characteristic when an input signal is split and transmitting the input signal to another device even when the set does not operate, a video apparatus including the signal splitting apparatus, and a signal splitting method thereof The signal splitting apparatus which splits and outputs an input signal fed to an input port to a plurality of output ports, includes a signal amplifying part which amplifies the input signal; a signal splitting part which splits the amplified input signal; and a switching part which selects either a first mode which provides the input signal to the signal amplifying part to split the input signal, or a second mode which provides the input signal to a specific one of the output ports.

Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A band gap reference circuit incorporating resistive trimming is disclosed. The band gap reference circuit includes an additional trimming resistor and a trimming unit which performs trimming by changing a resistance value of the trimming resistor.

Abstract: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT2 current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT2 and ICTAT2, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier.

Abstract: A method for tuning a tunable filter includes inputting a control signal to the tunable filter and tuning the configuration of the tunable filter according to the control signal. When the control signal is at any one of a plurality of predetermined states, a step size of a characteristic frequency of the tunable filter is positively correlated with the characteristic frequency of the tunable filter.

Abstract: A multi-mode power amplifier and an electronic device including the amplifier are described.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract: According to an aspect of the invention, there is provided an audio data processing apparatus including: a decoding unit configured to extract an encoding parameter from encoded audio data by decoding the encoded audio data; an acquisition unit configured to acquire a background noise signal; a correction gain calculating unit configured to calculate a correction gain for correcting frequency characteristics of the audio data by using the encoding parameter and the background noise signal; and a frequency characteristics correcting unit configured to correct the frequency characteristics of the audio data based on the correction gain.

Abstract: The present invention discloses a predistortion method based on vector envelope injection. Said method includes the following steps: radio frequency input signals are divided into two signal streams; one input signal stream generates two envelope injection signals whose amplitudes can be adjusted independently; the other signal stream is divided into further two radio frequency signal streams; said two radio frequency signal streams are amplified with the same amplitude; frequency mixing is performed for said two envelope injection signals and two radio frequency signal streams respectively to obtain two compensation signals; the amplified radio frequency signal and compensation signals are power synthesized in the same way, so as to obtain two compensation signals and amplified radio frequency signals of different directions. This present invention also provides a corresponding predistortion device.

Abstract: The circuit system contains an output control circuit, an output stage circuit, a current sensing circuit, and a delay circuit. The output stage circuit is driven by the output control circuit and monitored by the current sensing circuit. When the current sensing circuit determines that there is a short circuit or an abnormal current in the output stage circuit, the current sensing circuit delivers an output signal to disable the output control circuit, which in turn stops the output stage circuit. The output signal is also sent to the delay circuit which, after a period of time, provides a trigger signal to reset the current sensing circuit and to enable the output control circuit again. By providing a large enough delay time, the output stage circuit is able to sustain a very large peak current to prevent it from being damaged.

Abstract: A simple operational amplifier (OP amp) and an alternative circuit of a latch circuit constructed by a Bipolar Junction Transistor (BJT) or a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) are provided to obtain a higher output ability (higher input/output voltage and output circuit).

Abstract: Microwave coupling network comprising a passive resistive pi net and a coupling capacitor is coupled to a branching point. The branching point is coupling to respectively a plurality of common drain FET amplifier stages or respectively to common collector BJT amplifier stages, wherein respectively the source, or respectively the emitter, is coupled to at least one output port.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.

Abstract: A power amplifier includes a bipolar transistor and a self-adaptive bias network situated between an RF input and the base of the bipolar transistor. The self-adaptive bias network suppresses the low frequency even-order intermodulation components. The self-adaptive bias network stabilizes a DC bias voltage to provide a substantially constant base-emitter voltage and provides an increased DC base current with increased input power when the power amplifier is operating within the nonlinear region.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a current controlled, phase locked loop device having a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

Abstract: A frequency synthesizer, especially for use with a time-base generator of a fill-level meter employing the radar principle is designed to output a first frequency signal and a second frequency signal at mutually slightly different frequencies. The synthesizer incorporates a reference oscillator operating at a reference frequency and a control oscillator regulated at a control frequency. A first frequency divider with a division factor V1 is connected in line with the reference oscillator and a second frequency divider with the division factor V2 is connected in line with the control oscillator, which frequency dividers serve to output the first frequency signal and the second frequency signal, respectively. The result is a stable frequency synthesizer with a large phase-control bandwidth and consequently an extremely short transient response time as well as broad-band phase-noise suppression. A method for operating the synthesizer is also disclosed.

Abstract: A system and method for providing temperature compensation in a oscillator component (such as a crystal oscillator component) that includes a closely-located temperature sensing device. The crystal oscillator component in example systems and methods is exposed to a temperature profile during a calibration procedure. Temperature and frequency data are collected and applied to coefficient generating function according to a temperature compensation model to generate a set of coefficients that are used in the temperature compensation model in an application device. The generated coefficients are stored in a coefficient memory accessible to an application device during operation.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.