Abstract: The present invention is concerned with the preparation of novel nitrile hydratases. These latter are preferably obtained from nonculturable organisms by means of a PCR-based screening, in metagenome DNA libraries, using special degenerate primers.

Abstract: The present invention provides adenoviral vectors comprising cell status-specific transcriptional regulatory elements which confer cell status-specific transcriptional regulation on an adenoviral gene. A “cell status” is generally a reversible physiological and/or environmental state. The invention further provides compositions and host cells comprising the vectors, as well as methods of using the vectors.

Abstract: Methods and means are provided for modulating fiber length in fiber producing plants such as cotton by altering the fiber elongation phase. The fiber elongation phase may be increased or decreased by interfering with callose deposition in plasmodesmata at the base of the fiber cells.

Abstract: The present invention relates generally to kits, compositions and methods useful in the qualitative analysis of the presence of chemicals used and produced in the manufacture of illegal drugs. The compositions and methods may be useful for, among other things, qualitatively determining whether items of real or personal property or other chattels have been exposed to the manufacture of illegal drugs or whether such items have been contaminated by illegal drugs.

Abstract: A method for preparing a composition that includes selecting a pH of the composition; selecting a first buffer with a negative temperature coefficient; selecting a second buffer with a positive temperature coefficient; and forming the composition comprising the first buffer and the second buffer. The composition has an average temperature coefficient, ?pH/?T(Ta,Tb)?1×10?3 pH-unit/K and a ?pH(Ta,Tb)?0.31 pH-unit for Ta=4 K and Tb=313 K.

Abstract: The present invention relates to methods for diagnosing multiple sclerosis in a subject, the method, comprising determining the level of phosphorylation of a marker in a biological sample from the subject, wherein the marker is selected from ?1-antitrypsin (a1AT) and vitamin D binding protein (VDBP); and comparing the level of phosphorylation of the marker in the sample to a reference value.

Abstract: The present invention relates to a column packing and concentrating columns for the analysis of metallic elements, wherein the column packing is formed from swollen and cleaned macroporous adsorbent resins of high, medium or non-polarity via dynamic on-column treatment or static immersion treatment using treating solution I or treating solution II; said treating solution I is a mixed aqueous solution of 0.02˜0.06 g/L of 2-(5-bromo-2-pyridyl azo)-5-diethylamino phenol, 1.60˜1.90 g/L of Na2B4O7.10H2O, 6.0×10?3˜8.0×10?3 mol/L of HCl, and polyethylene glycol octyl phenyl ether with a volume percent of 0.3˜0.8%; said treating solution II is a mixed aqueous solution of 0.04˜0.10 g/L of 2-(5-bromo-2-pyridyl azo)-5-diethylamino phenol, 0.05˜0.08 mol/L of glycin, 0.05˜0.08 mol/L of NaOH, 0.010˜0.015 mol/L of NaCl, and polyethylene glycol octyl phenyl ether with a volume percent of 0.3˜0.8%.

Abstract: The invention provides biomarkers including ?-2-microglobulin, Cystatin C, hsCRP and glucose as well as methods for using the biomarkers for diagnosing and/or assessing the risk of peripheral artery disease in a subject. In some embodiments, the subject being tested may be suffering from or at risk of other circulatory diseases, including coronary artery disease. Hemoglobin A1c or other proxies for measuring glucose levels may be substituted for or measured in addition to glucose in the context of the present invention.

Abstract: A multiple analyte detection system includes a carrier having reagents disposed thereat, with each of the reagents capable of optically changing in response to exposure to a respective analyte. The system further includes a photodetector positioned to collectively detect light interacted with each of the reagents, a processor to determine a presence or an absence of each of the analytes in response to the light collectively-detected, and an indicator to provide an indication of the presence or the absence of each of the analytes. A method of detecting multiple analytes includes exposing reagents capable of optically changing in response to exposure to a respective analyte to a sample. The method further includes collectively detecting light interacted with each of the reagents, determining a presence or an absence of each of the analytes in response to the light collectively detected, and indicating the presence or the absence of each of the analytes determined.

Abstract: A system to detect and identify various aerosol agents, such as biological agents which have been aerosolized, is disclosed. The system generally includes a mechanism to collect a selected sample of atmosphere which may include the aerosol agent, a sub-system to detect the presence and type of agent, and a sub-system to communicate the type of agent detected.

Abstract: A lateral flow test strip for the definitive detection of human blood from forensic samples derived from crime scenes, sexual assault evidence kits, and other sources of forensic evidence.

Abstract: A magnetic microparticle-packing unit using centrifugal force, a microfluidic device including the same, and an immunoassay method using the microfluidic device are provided. The magnetic microparticle-packing unit includes a rotary body controllably rotating; a microfluidic channel which includes a curved portion in which the microfluidic channel first extends away from the rotation center of the rotary body and then turns toward the rotation center of the rotary body.

Abstract: An exemplary repairing method includes providing a substrate having a plurality of conducting lines; detecting a broken position of one of the conducting lines; switching on a nozzle; and forming a copper layer at the broken position on the substrate. The repairing method of the present invention employing a repairing device for performing a chemical vapor deposition (CVD) method to forming the copper layer at a position of the broken defect of one of the conducting lines.

Abstract: A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A method of producing an organic semiconductor device is provided in which a layer composed of an organic semiconductor having excellent crystallinity and orientation in a low-temperature region can be formed, and the device can be produced in the air.

Abstract: A method and a device for the mutual contacting of two wafer-type component composite configurations made of multiple identical components which are implemented coherently, in particular a semiconductor wafer (12) with a functional component wafer (14), to produce electronic assemblies on the wafer level, in which the component composite configurations are each situated on a receptacle unit (11; 13) and the contact pressure necessary for the contacting between contact metallizations of the component composite configurations to be connected to one another is generated in such a way that a vacuum is generated in a contact chamber which receives the component composite configurations and is delimited by the receptacle units, and the contacting of the contact metallizations is performed by a rear energy impingement of a component composite configuration.

Abstract: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.

Abstract: Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r1 of the sacrificial oxide film is higher than an etching rate r2 of the buried oxide layer during the etching.

Abstract: Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes forming a metal layer over both fins and annealing the FinFet device to form fully silicided gates over each fin of the FinFet device.

Abstract: The present invention discloses a method for fabricating a bottom-gate low-temperature polysilicon thin film transistor, wherein the bottom gate structure is used to form an amorphous silicon layer with varied thicknesses; the amorphous silicon layer in the step region on the border of the bottom gate structure is partially melted by an appropriate amount of laser energy; the partially-melted amorphous silicon layer in the step region functions as crystal seeds and makes crystal grains grow toward the channel region where the amorphous silicon layer is fully melted, and the crystal grains are thus controlled to grow along the lateral direction to form a lateral-grain growth low-temperature polysilicon thin film. The lateral grain growth can reduce the number of the grain boundaries carriers have to pass through. Thus, the present invention can promote the carrier mobility in the active region and the electric performance.

Abstract: There is provided a method for manufacturing a crystalline semiconductor film. An insulating film is formed over a substrate; an amorphous semiconductor film is formed over the insulating film; a cap film is formed over the amorphous semiconductor film; the amorphous semiconductor film is scanned and irradiated with a continuous wave laser beam or a laser beam with a repetition rate of greater than or equal to 10 MHz, through the cap film; and the amorphous semiconductor film is melted and crystallized At this time, an energy distribution in a length direction and a width direction in a laser beam spot is a Gaussian distribution, and the amorphous semiconductor film is scanned with the laser beam so as to be irradiated with the laser beam for a period of greater than or equal to 5 microseconds and less than or equal to 100 microseconds per region.

Abstract: A nonvolatile semiconductor memory element enabling to improve insulation performance of an insulator around a floating gate and to decrease the ratio of oxidized metal ultrafine particles in the floating gate, are provided. In a process for producing nonvolatile semiconductor memory element comprising a floating gate made of a hardly oxidizable material having a Gibbs' formation free energy for forming its oxide higher than that of Si in a range of from 0° C. to 1,200° C.

Abstract: Fabrication methods for a MOS device and a CMOS device are provided. A substrate is provided with a gate structure formed on the substrate, a lightly-doped drain (LDD) region formed near sides of the gate structure in the substrate and a spacer wall formed on sidewalls of the gate structure and covering a part of the LDD region. A protection layer is formed for covering the gate structure, the LDD region and the spacer wall. A part of the protection layer is removed. Another part of the protection layer on the gate structure and the spacer wall is reserved. A part of the surface of the substrate is exposed. The exposed surface of the substrate is removed for forming a trench. A pre-clean step, including an oxygen plasma process, is performed on the bottom of the trench. An epitaxy material layer is formed in the trench.

Abstract: A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.

Abstract: A method of fabricating a semiconductor device according to an example embodiment may include forming an isolation layer defining an active region in a semiconductor substrate, forming a silicon pattern and a sacrificial pattern on the active region, the sacrificial pattern including a semiconductor material different from the silicon pattern, forming a gate spacer on a sidewall of the silicon pattern and a sidewall of the sacrificial pattern, removing the sacrificial pattern to expose a top surface of the silicon pattern, and/or forming a gate silicide on the silicon pattern.

Abstract: A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

Abstract: Patterning effects on a substrate are reduced during radiation-based heating by filtering the radiation source or configuring the radiation source to produce radiation having different spectral characteristics. For the filtering, an optical filter may be used to truncate specific wavelengths of the radiation. The different configurations of the radiation source include a combination of one or more continuum radiation sources with one or more discrete spectrum sources, a combination of multiple discrete spectrum sources, or a combination of multiple continuum radiation sources. Furthermore, one or more of the radiation sources may be configured to have a substantially non-normal angle of incidence or polarized to reduce patterning effects on a substrate during radiation-based heating.

Abstract: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

Abstract: A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.

Abstract: Methods and systems for forming layered electronic devices on a flexible, elongated substrate are described. The layered electronic devices include at least one electronically or optically active layer. Deposition of one more layers of the electronic devices occurs as the flexible substrate is moved through one or more deposition stations. At each deposition station the substrate is aligned with an aperture mask having apertures arranged in a pattern. The aperture mask and the substrate are brought into proximity over a portion of a circumference of a rotating drum. A layer of the layered electronic devices is formed by deposition of material through the apertures of the aperture mask. At each deposition station, registration between at least two layers of the layered electronic devices is maintained.

Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

Abstract: A method of fabricating a continuous layer of a defect sensitive material on a silicon substrate includes preparing a silicon substrate; forming a nanostructure array directly on the silicon substrate; depositing a selective growth enhancing layer on the substrate; smoothing the selective growth enhancing layer; and growing a continuous layer of the defect sensitive material on the nanostructure array.

Abstract: A method of forming an epitaxial layer in a chamber is disclosed. The method includes positioning a Group IV semiconductor substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV nanoparticles and a solvent, wherein a porous compact is formed. The method also includes heating the porous compact to a temperature of between about 100° C. and about 1100° C., and for a time period of between about 5 minutes to about 60 minutes with a heating apparatus, wherein the epitaxial layer is formed.

Abstract: A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.

Abstract: A method of fabricating structures in an electronic device by forming and patterning a first film layer on a substrate into ridges with a photolithographic system. The ridges are formed from an image produced by a first simple geometry photomask where the first photomask has at least one first slot-like feature. The ridges are patterned into the structures which are essentially rectangular in shape and formed from an image produced by a second simple geometry photomask. The second photomask has at least one second slot-like feature arranged substantially orthogonal to the at least one first slot-like feature on the first photomask. The structures each have at least one dimension less than a limit-of-resolution of the photolithographic system where the dimension is measured in a plane substantially parallel to a face of the substrate.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: In one embodiment of a method of forming at least one through-substrate interconnect, a semiconductor substrate having first surface and an opposing second surface is provided. At least one opening is formed in the semiconductor substrate to extend from the first surface to an intermediate depth within the semiconductor substrate. The at least one opening is partially defined by a base. At least one metal-catalyst nanoparticle is provided on the base. Conductive material is deposited within the at least one opening under conditions in which the metal-catalyst nanoparticle promotes deposition of the conductive material. Material of the semiconductor substrate may be removed from the second surface to expose a portion of the conductive material filling the at least one opening. In another embodiment, instead of using the nanoparticle, the conductive material may be selected to selectively deposit on the base partially defining the at least one opening.

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract: A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.

Abstract: A vacuum processing apparatus including at least three transfer chambers that have transfer robot arms for transferring a substrate, one or more processing chambers connected to each of the transfer chambers; one or more substrate mounts disposed in the interior thereof; a single common vacuum chamber in which the transfer robot arms of the at least three transfer chambers are disposed in positions that allow the arms to reach the substrate mount, and which is used for handing off the substrate by the transfer robot arms between at least two transfer chambers and at least one substrate mount; and load-lock chambers connected to at least one transfer chamber.

Abstract: Cyclical methods of depositing a ruthenium film on a substrate are provided. In one process, each cycle includes supplying a ruthenium organometallic compound gas to the reactor; purging the reactor; supplying a ruthenium tetroxide (RuO4) gas to the reactor; and purging the reactor. In another process, each cycle includes simultaneously supplying RuO4 and a reducing agent gas; purging; and supplying a reducing agent gas. The methods provide a high deposition rate while providing good step coverage over structures having a high aspect ratio.

Abstract: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.

Abstract: A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH3 and HF and heated, to substantially uniformly remove the silicon oxide. A method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH3 and HF and heat is also disclosed, as is an intermediate semiconductor device structure that includes a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions.