Abstract: The present invention discloses a scalable high-speed cache system in a storage network. It gives a solution to the bottleneck problem that the speed of seeking on the hard disk is slow, and realizes the high speed respondence to the input/output of the server. The present invention includes a high-speed cache system in a storage network which is constituted with at least one high-speed cache module which is connected to the network, a storage network manager constitutes with at least one storage network management module. The said storage network management module is constituted with hardware platform unit and software platform unit. The said hardware platform unit uses an embedded system platform or a server platform. The said high-speed cache system in a storage network is managed by the storage network manager, and it can be shared by the server and the disk storage system which is connected to the storage network.

Abstract: The present invention discloses a data scanning system and a method thereof for a server. The method includes steps of defining an auditing period, scanning an accessed data in a default scanning mode from the server by a user, obtaining a credit data of the user, and executing a rearranging process for resetting a reset scanning mode for the user according to the credit data when the auditing period is expired, thereby the default scanning mode being adjustable according to the credit data of the user.

Abstract: A device previously configured as a registrar and that has established an independent ad-hoc network is automatically discovered by another device also previously configured as a registrar. To form an ad-hoc wireless network between these two devices, each device periodically enters a scanning mode to scan for and intercept beacons transmitted by the other device. Upon such interception, one of the devices becomes an enrollee in accordance with a predefined condition and in response to a user selected option. Subsequently, the enrollee modifies its beacons to include an attribute, such as the MAC address, associated with the other device. After intercepting the modified beacon, the remaining registrar prompts it user to decide whether to allow the enrollee to join the registrar's network. If the user responds affirmatively, a handshake is performed between the two devices and a subsequent attempt is made by the enrollee to join the registrar's network.

Abstract: A system and method for configuring client access to a network includes at a first port, accessing a first server on a first local area network associated with the first port. An authorized local area network other than the first local area network is determined to which an authorized connection can be properly made based on information in a client request. The first port is assigned to the authorized local area network. Communications are handled with a new client configuration in the authorized local area network.

Abstract: A host for a telecommunications system includes a container. The host includes an IPv4 stack disposed in the container. The host includes an IPv6 stack disposed in the container. The host includes a mapping layer disposed in the container in communication with the IPv4 stack and the IPv6 stack to map IPv4 addresses to IPv6 addresses. A telecommunications system includes an IPv6 transport network. The system includes an IPv4 transport network having IPv4 hosts. The system includes an host, in communication with the IPv6 transport network and the IPv4 transport network, having an IPv4 functionality layer for supporting IPv4 applications, and an IPv6 functionality layer for supporting IPv6 applications, and a mapping layer in communication with the IPv4 functionality layer in the IPv6 functionality layer for mapping IPv6 addresses and IPv4 addresses between the IPv4 hosts and IPv4 applications and the IPv6 transport network. A method for communicating.

Abstract: A method and apparatus for determining a communication protocol are provided. The apparatus for determining a communication protocol includes a protocol recording unit which records one or more applicable communication protocols, and a protocol parsing unit which parses a common communication protocol determined by another apparatus among the recorded communication protocols and provides the common communication protocol so as to communicate with the another apparatus.

Abstract: A method of tracking during an affiliate referral transaction without relying on cookies is provided. The method includes requesting a unique session identifier from a merchandiser. A hyperlink is then published on a website of an affiliate. Next, the unique session identifier is added to a sub-domain portion of a domain name of a merchandiser when the hyperlink is activated by a customer. The unique session identifier and the customer are passed to the merchandiser. The merchandiser uses the unique session identifier to track either or both the affiliate and the customer. Thereafter, information is transmitted between the affiliate and the merchandiser. Then, compensation from the merchandiser is received for referral of the customer to the merchandiser.

Abstract: A system and method are described for interfacing a wireless device with a plurality of web services including social networking web services.

Abstract: MPLS networks offering PW or VPLS services may be interconnected with Ethernet networks implemented according to 802.1ah or 802.1Qay. The MPLS network may be a core and offer services to the Ethernet access networks, or vise-versa. Additionally, a mixture of different types of access networks may be interconnected by an MPLS core or an Ethernet core. Both network interworking and service interworking are provided. OAM fault detection may be implemented via maintenance entities extending across the network or end to end depending on the combination of networks and services offered by the networks.

Abstract: A memory device and system for managing links to content or digital assets in an on-line, network or software application environment. The links and digital assets may be represented by unique identifiers and pointers or similar data. The memory device can take the form of a piece of jewelry, handheld game device, memory stick, toy or similar item. The memory device can include communication ports to provide connectivity to multiple devices including other memory devices, computers and similar electronic devices. The memory device can also include an input mechanism that allows a user to select an output of the memory device. The memory device can include a sensor or similar component that detects and receives non-digital input. The non-digital input can come from any source including sources embedded within pieces of jewelry, toys, electronic devices or similar items. The non-digital input can be received and stored as a digital value or used to modify an existing digital value.

Abstract: The present invention provides a machine system that enables the arbitration of IO accesses and band control based on the priority of virtual servers while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system including a CPU, a memory, and an IO interface includes a hypervisor that generates plural virtual servers, and an IO controller that controls the IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.

Abstract: A memory system and method of operation are disclosed. The system includes a memory device having multiple RAMs, and a memory controller having a plurality of controllers, each one of the plurality of controllers is configured to generate an address signal and a control signal controlling read/write operations in a corresponding one of the RAMs. The memory controller includes a single common control signal output port communicating control signals generated by the controllers, and a single common address signal output port communicating address signals generated by the controllers.

Abstract: An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display.

Abstract: A portable computer is provided. The portable computer includes a motherboard, a first display, a second display, a non-volatile memory device, and a microprocessor, wherein the motherboard includes an audio circuit. When the motherboard is shut down and the microprocessor receives a playing command, the microprocessor enables the audio circuit and plays specific multimedia stored in the non-volatile memory device through the audio circuit and the second display device according to the playing command.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: An interactive control system using a remote control signal in accordance with HDMI-CEX standards between a computer and an electric home appliance performs power supply control and screen display from a PC to a television, power supply control from the television to the PC, and application control on the PC. In the system, a personal computer (PC) is loaded with a controller capable of operating by a standby power supply. The remote control signal of a PC remote controller is input to an HDMI unit connector of a television through a photoreceiver controller of a PC, a USB/CEC power-on signal connector, a CEC unit connector, a signal line a, an HDMI unit connector, and a cable. The remote control signal of a TV remote controller is input to the cable, the HDMI unit connector, the CEC unit connector, a USB power supply connector, and a USB data processing unit.

Abstract: An electronic device controlled by control software stored in a volatile memory, wherein said software is retained in the memory and said electronic device is stopped after executing steps to initialize said software.

Abstract: A communications system and method are provided for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. Network device interfaces associated with different data channels can coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Abstract: In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.

Abstract: The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: A parallel bus architecture is disclosed. The parallel bus architecture includes: a first sub-system comprising at least a first master device and at least a first slave device, wherein the first master device can access the first slave directly; a second sub-system comprising at least a second master device and at least a second slave device, wherein the second master device can access the second slave directly; and an interconnect matrix, coupled to the first sub-system and the second sub-system, for transmitting a command from the first sub-system to the second sub-system and transmitting a command from the second sub-system to the first sub-system.

Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.

Abstract: An exemplary wireless network card includes a wireless network card controller, a bus interface having two input ports and one output port, and a card reader controller, wherein the wireless network card controller and the card reader controller are connected to the inputs port of the bus interface respectively, and the output port of the bus interface is connected to an electronic equipment. The electronic equipment can be linked to a net via the wireless network card controller, and also can receive data transmitted from the card reader read from a memory card.

Abstract: A computer comprises a mother board. A CPU, a chipset and a flash memory storage device are configured on the mother board. Wherein, the chipset is coupled to the CPU and coupled to the flash memory storage device through a USB bus, so that the CPU is able to access data stored on the flash memory storage device through the chipset.

Abstract: A packet communication device autonomously selects an appropriate operation mode according to a connection environment to an external device before a service of the device is started. When the device is connected to the external buses, connection interface units notify an external device discrimination unit of connection of the device. The external device discrimination unit issues a polling packet to the connected device, discriminates the connected external device on the basis of the response packet, and notifies an operation mode switching unit. The operation mode switching unit selects an operation mode conforming to a connection environment of the packet communication device to the external device and switches the operation mode of the device to the mode.

Abstract: A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data buses for communicating data signals between said memory controller and a respective one of said memory devices, each of said data buses providing a dedicated data signal path to a different one of said memory devices, address interface circuitry for connecting to a common address bus for communicating address signals to each of said memory devices on a shared address signal path, address signals which are directed to different ones of said memory devices being time division multiplexed together on said common address bus, and device selecting circuitry for generating one or more device selecting signals synchronised with said time division multiplexing of said common address bus to select that memory device to which address signals currently asser

Abstract: A multiprocessor system and method thereof are provided.

Abstract: The present invention discloses a mask-programmable memory with reserved space (RS-MPM). It is released in a sequence of versions. In the original version, its storage space comprises a reserved space, which does not store any meaningful information. In the later version, the reserved space stores new release. RS-MPM can be readily applied to three-dimensional memory (3D-M) and three-dimensional memory module (3D-MM).

Abstract: The present invention discloses a flash-memory storage device for implementing both ReadyBoost and ReadyDrive Windows PC accelerators, the device including: a single flash-memory module adapted to be configured as a ReadyBoost accelerator and as a ReadyDrive accelerator; and a controller for controlling the flash-memory module. Preferably, the device further includes: a mechanism for wear-leveling the flash-memory module. Preferably, the device further includes: a mechanism for repartitioning the flash-memory module. Most preferably, the mechanism is configured to erase the flash-memory module. A flash-memory storage device including: a flash-memory module having at least one partition, wherein at least one partition is adapted to be alternatively reversibly configured as a ReadyBoost accelerator and as a ReadyDrive accelerator; and a controller for controlling the flash-memory module. Preferably, the device further includes: a mechanism for wear-leveling the flash-memory module.

Abstract: Methods for enhancing the performance of a host system including the steps of: providing an operating system, running on the host system, that supports a ReadyDrive and ReadyBoost accelerator; and providing a flash-memory storage device, which supports both the accelerators, having a single flash-memory module. Preferably, the method further includes the steps of: monitoring a frequency of write commands by the host system to the device; and upon the frequency exceeding a predefined threshold, suspending operations of the accelerators until the frequency is below the threshold.

Abstract: A memory device includes a flash memory, a memory controller, and an MLC mode selector. The flash memory includes at least one memory cell configured to store multi-bit data therein. The MLC mode selector is configured to generate a mode selection signal indicating whether to store single-bit data or multi-bit data in the memory cell responsive to a user selection. The memory controller is configured to operate the flash memory in a single-level cell (SLC) program mode to store the single-bit data or a multi-level cell (MLC) program mode to store the multi-bit data based on the mode selection signal from the MLC mode selector. The memory device may be configured to store program mode information for the memory cell indicating whether the single-bit data or the multi-bit data is stored therein. Related systems and methods of operation are also discussed.

Abstract: Some embodiments of the present invention provide a memory system including a flash memory including a plurality of memory cells and a memory controller configured to receive data information from a host and to selectively store data in the flash memory in single-bit and multi-bit storage modes responsive to the data information. The memory controller may be configured to store respective pages in respective ones of the single-bit and multi-bit modes.

Abstract: An information processing apparatus has a common incremental write type file system allowing an incremental write type file access, including an incremental write type file write, to an incremental write type optical recording medium and a non-volatile semiconductor memory device.

Abstract: An purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A storage system includes a plurality of disk drives, and a disk controller for controlling the plurality of disk drives. The plurality of disk drives are configured from a plurality of virtual devices, to which logical devices are allocated. The disk controller apparatus comprises a channel adapter connected to the host computer, a disk adapter for accessing predetermined storage regions of the logical devices, cache memory arranged between the channel adapter and the disk adapter, a compression unit for carrying out compression processing on the data, and a power controller for controlling supplying of power to the plurality of disk drives. The disk controller forms logical devices after compression based on data compressed by the compression processing, and the logical devices after compression are allocated to the virtual devices.

Abstract: Logical data stores are placed on storages to minimize store request time. The stores are sorted. A store counter and a storage counter are each set to one. (A), (B), and (C) are repeated until the storage counter exceeds the number of storages within the array. (A) is setting a load for the storage specified by the storage counter to zero. (B) is performing (i), (ii), and (iii) while the load for the storage specified by the storage counter is less an average determined load over all the storages. (i) is allocating the store specified by the store counter to the storage specified by the storage counter; and, (ii) is incrementing the load for this storage by this storage's request arrival rate multiplied by an expected service time for the requests of this store. (iii) is incrementing the store counter by one. (C) is incrementing the storage counter by one.

Abstract: A redundant array of independent disks (RAID) module converted from a 2.5-inch specification to a 3.5-inch specification is characterized in that two 2.5-inch SATA hard disks are installed within a standard 3.5-inch SATA RAID module, so as to form a RAID having two hard disks or two stand-alone SATA hard disks for mounting the RAID module including two 2.5-inch hard disks within a 3.5-inch disk drive slot of a common computer housing, or any other devices that can receive a 3.5-inch disk drive.

Abstract: A disk array includes a drive management unit, which is a program for identifying kinds of disk devices and managing different disk devices separately, and a drive management table for storing information to be utilized by the drive management unit. The disk array further includes a program for managing accumulated time of disk devices. The program includes a drive lifetime setting portion for setting lifetimes of drives, a drive start/stop portion for intentionally starting/stopping ATA disk devices, and an operation time measurement portion for measuring accumulated operation time. Since it is necessary to be conscious of difference in reliability and performance among disk devices when forming a RAID, a drive kind notification unit, which is a program for notifying of the kind of a disk device when forming the RAID, is provided.

Abstract: Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

Abstract: An apparatus and method for managing stacks for efficient memory usage. The apparatus includes a fault cause analysis unit to recognize a page fault caused by a marking page; a control unit to set the marking page, to request compression of a first stack page depending on whether a page fault occurs, to release a mapping of a second stack page that becomes empty due to the compression, and to return the second stack page; a memory allocation unit to receive the second stack page and to allocate a new stack page to the control unit upon completion of the compression; and a compression unit to compresses the first stack page at the request of the control unit.

Abstract: Management of a Cache is provided by differentiating data base on attributes associated with the data and reducing storage bottlenecks. The Cache differentiates and manages data using a state machine with a plurality of states. the Cache may use data patterns and statistics to retain frequently used data in the cache longer. The Cache uses content or attributes to differentiate and retain data longer. Further, the Cache may provide status and statistics to a data flow manager that determines which data to cache and which data to pipe directly through, or to switch cache policies dynamically, thus avoiding some of the cache overhead. The Cache may also place clean and dirty data in separate states to enable more efficient Cache mirroring and flush.

Abstract: A storage processor is constructed on or within an interconnected circuit (IC) chip. The storage processor has a plurality of ports operable to send and/or receive messages to/from storage devices. An output indication circuit is associated with each output port. The indication circuit indicates that data is ready to be transmitted to a storage device from the particular output port. A crossover circuit is interposed between the ports. The crossover circuit has a memory that can store data. When data is received at a port, the storage processor can store the incoming data to the crossover circuit. A memory is also present on the chip. The memory holds data that relates incoming data to outgoing data. Thus, when data comes into the storage processor, the storage processor can determine a specific course of action for that data based upon the information stored in this memory. The chip also has a plurality of processing sub-units coupled to the crossover switch.

Abstract: Implementations related to detecting control data are presented herein. A detector searches for control data in a first set of pre-determined control data, wherein a respective subset of the first set is assigned to a respective logical port and the respective subset is excluded from the first set when searching for the control data received from the respective logical port.

Abstract: A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.

Abstract: A method for buffering data when reading an optical disc is disclosed in the present invention. The method includes providing a memory page with a plurality of memory spaces corresponding to a memory space matrix with M rows×N columns, reading data stored in the optical disc to generate a block to be decoded, selecting M rows×N columns of data from the block to be decoded as a sub-block to be decoded, and storing the M rows of data of the sub-block to be decoded into the M rows of memory spaces of the memory space matrix respectively.

Abstract: A method and/or a system of storage system management based on a backup and recovery solution embedded in the storage system is disclosed. A method of a storage system includes coordinating with a host system through a backup coordinator module embedded in the host system during at least one of a backup operation and/or a recovery operation associated with the host system, performing the at least one of the backup operation and/or the recovery operation associated with the host system using a backup and recovery module embedded in a controller firmware of the storage system. The method may include the backup and recovery module which interfaces with the host system through the backup coordinator module is agnostic to an operating system of the host system.

Abstract: A storage device system includes an information processing device, a first storage device equipped with a first storage volume, and a second storage device equipped with a second storage volume. The information processing device and the first storage device are communicatively connected to one another. Also, the first storage device and the second storage device are communicatively connected to one another. The information processing device is equipped with a first write request section that requests to write data in the first storage device according to a first communications protocol, and a second write request section that requests to write data in the second storage device according to a second communications protocol. The information processing device creates first data including a first instruction to be executed in the second storage device.

Abstract: A method, apparatus and computer program product for providing page-protection based memory access barrier traps is presented. A value for a user-mode bit (u-bit) is computed for each extant virtual page in an address space, the u-bit indicative that an object on the virtual page is being moved by a Garbage Collector process. An instruction is executed which causes an access protection fault. The state of the u-bit for the virtual page associated with the access protection fault is consulted when the access protection fault is encountered. Additionally, the access protection fault is translated into a user-trap (utrap) and the utrap is serviced when the u-bit is set.