Patents Issued in July 24, 2008
  • Publication number: 20080173867
    Abstract: A semiconductor device includes a substrate, a transparent oxide layer disposed on one surface side of the substrate, a gate disposed apart from the transparent oxide layer, and a gate insulating layer disposed between the transparent oxide layer and the gate. The transparent oxide layer includes a source, a drain, and a channel formed integrally between the source and the drain, and is made of a transparent oxide material as the main material. The gate provides an electric field to the channel. The gate insulating layer insulates the source and the drain from the gate. The average thickness of the channel is smaller than the average thickness of the source and the drain so that the source and the drain function as conductors and the channel functions as a semiconductor.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 24, 2008
    Applicants: SHINSHU UNIVERSITY, SEIKO EPSON CORPORATION
    Inventors: Musubu ICHIKAWA, Kiyoshi NAKAMURA, Taketomi KAMIKAWA
  • Publication number: 20080173868
    Abstract: A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.
    Type: Application
    Filed: March 15, 2007
    Publication date: July 24, 2008
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Young Woo Kwon
  • Publication number: 20080173869
    Abstract: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.
    Type: Application
    Filed: March 27, 2008
    Publication date: July 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander L. Martin, Eric P. Solecky
  • Publication number: 20080173870
    Abstract: A thin film transistor substrate having low resistivity and reduced contact resistance includes a gate wiring line formed on an insulating substrate, a data wiring line crossing the gate wiring line while being insulated from the gate wiring line, and a pixel electrode connected to a portion of the data wiring line and including a zinc oxide layer pattern doped with a dopant and an anti-oxidizing substance layer pattern.
    Type: Application
    Filed: October 30, 2007
    Publication date: July 24, 2008
    Inventors: Byeong-beom Kim, Chang-oh Jeong, Yang-ho Bae
  • Publication number: 20080173871
    Abstract: In a display device which includes MIS transistors having semiconductor layers thereof formed of an amorphous semiconductor and MIS transistors having semiconductor layers thereof including a polycrystalline semiconductor, the present invention can enhance crystallinity of the semiconductor layers formed of the polycrystalline semiconductor when the respective MIS transistors adopt the bottom gate structure.
    Type: Application
    Filed: November 13, 2007
    Publication date: July 24, 2008
    Inventors: Takeshi Noda, Takahiro Kamo, Hideaki Shimmoto
  • Publication number: 20080173872
    Abstract: A liquid crystal display device and a fabricating method thereof for simplifying a process and improving an aperture ratio are disclosed, including forming a first mask pattern group including a gate line, a gate electrode and a common line; forming a second mask pattern group including a semiconductor pattern and a source/drain pattern having a data line, a source electrode and a drain electrode overlapped thereon on the gate insulating film using a second mask; and forming a third mask pattern group including and a pixel electrode making an interface with the protective film in the pixel hole to be connected to the drain electrode, thereby forming a horizontal electric field with the common electrode, using a third mask.
    Type: Application
    Filed: February 5, 2008
    Publication date: July 24, 2008
    Inventor: Byung Chul Ahn
  • Publication number: 20080173873
    Abstract: The present invention provides a method for manufacturing a display device which can reliably form electrodes in a thin film transistor.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 24, 2008
    Inventors: Miyo Ishii, Junichi Uehara, Kunihiko Watanabe
  • Publication number: 20080173874
    Abstract: A hetero junction bipolar transistor (HBT) has a (In)(Al)GaAsSb/InGaAs base-collector structure. A discontinuous base-collector conduction band forms a built-in electric field to infuse electrons into a collector structure effectively, while a discontinuous base-collector valence band prevents holes from spreading into the collector structure at the same time. Thus, a current density is increased. In addition, the small offset voltage of the base-emitter and base-collector junctions reduce a power consumption.
    Type: Application
    Filed: June 7, 2007
    Publication date: July 24, 2008
    Applicant: National Central University
    Inventors: Sheng-Yu Wang, Jen-Inn Chyi, Shu-Han Chen
  • Publication number: 20080173875
    Abstract: Self-aligned fabrication of silicon carbide semiconductor devices is a desirable technique enabling reduction in the number of photolithographic steps, simplified alignment of different device regions, and reduced spacing between the device regions. This invention provides a method of fabricating silicon carbide (SiC) devices utilizing low temperature selective epitaxial growth which allows avoiding degradation of many masking materials attractive for selective epitaxial growth. Another aspect of this invention is a combination of the low temperature selective epitaxial growth of SiC and self-aligned processes.
    Type: Application
    Filed: April 13, 2007
    Publication date: July 24, 2008
    Inventors: Yaroslav Koshka, Galyna Melnychuk
  • Publication number: 20080173876
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on the same SiC semiconductor substrate, with the MOSFET structure above the SIT structure. The SIT structure includes a p+ gate region in an n-type drift layer on an n+ SiC semiconductor substrate, and an n+ first source region on the surface of the drift layer. The MOSFET structure includes a p-well region on the surface of the first source region, a second source region formed in the p-well region, and a MOS gate structure formed in a trench extending from the second source region to the first source region. The p+ gate region and a source electrode are conductively connected.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 24, 2008
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Katsunori Ueno
  • Publication number: 20080173877
    Abstract: Disclosed is a semiconductor apparatus having a channel region of a substrate irradiated with light via a transparent gate electrode and a transparent gate insulating film to decrease channel resistance.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 24, 2008
    Applicant: KABUSHIKI KAISHA Y.Y.L.
    Inventor: Sataro YAMAGUCHI
  • Publication number: 20080173878
    Abstract: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Inventors: Gunther Waitl, Herbert Brunner
  • Publication number: 20080173879
    Abstract: A galvanic optocoupler of the type monolithically integrated on a silicon substrate and having at least one luminous source and a photodetector interfaced by means of a galvanic insulation layer. The photodetector can be a phototransistor realized in the silicon substrate, and the galvanic insulation layer (40) is a passivation layer of this phototransistor. The luminous source, above the galvanic insulation layer includes an integrated LED having a first and second polysilicon layer with function of cathode and anode, respectively, these first and second layers enclosing at least one light emitter layer, in particular a silicon oxide layer enriched with silicon (SRO). An integration process of a galvanic optocoupler thus made, in particular in BCD3s technology is provided.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 24, 2008
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mariantonietta Monaco, Massimiliano Fiorito, Gianpiero Montalbano, Salvatore Coffa
  • Publication number: 20080173880
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Application
    Filed: December 20, 2007
    Publication date: July 24, 2008
    Applicant: Toyoda Gosei
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Publication number: 20080173881
    Abstract: An LED chip package structure using a ceramic material as a substrate includes a ceramic substrate, a conductive unit, a hollow ceramic casing, a plurality of LED chips, and a package colloid. The ceramic substrate has a main body, and a plurality of protrusions extended from three faces of the main body. The conductive unit has a plurality of conductive layers formed on the protrusions, respectively. The hollow casing is fixed on a top face of the main body to form a receiving space for exposing a top face of each conductive layer. The LED chips are received in the receiving space, and each LED chip has a positive electrode side and a negative electrode side respectively and electrically connected to different conductive layers. In addition, the packaging colloid is filled into the receiving space for covering the LED chips.
    Type: Application
    Filed: October 25, 2007
    Publication date: July 24, 2008
    Inventors: Bily Wang, Jonnie Chuang, Chia-Hung Chen
  • Publication number: 20080173882
    Abstract: A method of making a diode begins by depositing an AlxGa1?xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1?xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal,; and an ohmic contact is deposited on the n+ layer.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventors: Primit Parikh, Sten Heikman
  • Publication number: 20080173883
    Abstract: A light emitting diode lamp is disclosed that includes a resin package that defines a recess in the shape of a solid polygon or another three-dimensional solid. The recess includes a floor, two side walls along the respective longer sides of the floor, and two end walls along the respective shorter sides of the floor. The two side walls define an angle therebetween greater than 3°, and the two end walls define an angle therebetween greater than 40°. A light emitting diode chip is positioned on the rectangular floor of the package.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventors: Christopher P. Hussell, David T. Emerson, Michael J. Bergmann
  • Publication number: 20080173884
    Abstract: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Inventors: Ashay Chitnis, James Ibbetson, Arpan Chakraborty, Eric J. Tarsa, Bernd Keller, James Seruto, Yankun Fu
  • Publication number: 20080173885
    Abstract: A semiconductor light-emitting device includes: a semiconductor layer including a light-emitting region and having an emission surface on its surface; an insulating layer arranged on a surface of the semiconductor layer opposite to; a first metal layer deposited on a surface of the insulating layer opposite to a surface where the semiconductor layer is arranged; a contact portion buried in a part of the insulating layer, the contact portion electrically connecting the semiconductor layer and the first metal layer; and a second metal layer having higher reflectivity with respect to a light-emitting wavelength than the first metal layer, the second metal layer arranged on a surface of the first metal layer opposite to a surface where the insulating layer is arranged, wherein a metal of which the first metal layer is made has higher adhesion to the insulating layer than a metal of which the second layer is made.
    Type: Application
    Filed: February 19, 2007
    Publication date: July 24, 2008
    Inventor: Yuichi Kuromizu
  • Publication number: 20080173886
    Abstract: Solid state lighting devices containing quantum dots dispersed in polymeric or silicone acrylates and deposited over a light source. Solid state lighting devices with different populations of quantum dots either dispersed in matrix materials or not are also provided. Also provided are solid state lighting devices with non-absorbing light scattering dielectric particles dispersed in a matrix material containing quantum dots and deposited over a light source. Methods of manufacturing solid state lighting devices containing quantum dots are also provided.
    Type: Application
    Filed: May 11, 2007
    Publication date: July 24, 2008
    Applicant: EVIDENT TECHNOLOGIES, INC.
    Inventors: Kwang-Ohk CHEON, Jennifer GILLIES, David SOCHA, David DUNCAN, Michael LoCASIO
  • Publication number: 20080173887
    Abstract: A self-luminous device 1 is one embodiment which has an increased light extraction efficiency by optimizing the distribution of refractive index in semiconductor layers. The self-luminous device 1 includes a first layer (semiconductor layer 2), a light emitting layer 3 overlaying the first layer (semiconductor layer 2), and a second layer (semiconductor layer 4) overlaying the light emitting layer 3. The first layer (semiconductor layer 2) and the second layer (semiconductor layer 4) have different refractive indices so that the refractive indices of the two layers (semiconductor layers 2 and 4) are asymmetric with respect to the light emitting layer interposed therebetween. In the refractive index distribution of asymmetric layers (semiconductor layers), the refractive index of the second layer (semiconductor layer 4) is higher than that of the first layer (semiconductor layer 2).
    Type: Application
    Filed: September 28, 2007
    Publication date: July 24, 2008
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Toshihiko Baba, Kosuke Morito
  • Publication number: 20080173888
    Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 24, 2008
    Inventor: Yu-Nung Shen
  • Publication number: 20080173889
    Abstract: A light emitting diode (LED) chip package including: a package body; an LED chip mounted on the package body and emitting an excited light; a phosphor layer including a phosphor absorbing the excited light and emitting a wavelength conversion light obtained by converting a wavelength of the excited light and a phosphor resin mixed with the phosphor; and a reflector layer including a reflector formed between the LED chip and the phosphor layer, transmitting the excited light to the phosphor layer, and reflecting the wavelength conversion light from the phosphor layer, and a reflector resin mixed with the reflector.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 24, 2008
    Inventors: Sergiy Shylo, Mi Jeong Yun
  • Publication number: 20080173890
    Abstract: A multidirectional light-emitting diode comprises a frame, at least one light-emitting chip, at least two connection wires, and a transparent material for covering above-mentioned components, wherein the light-emitting chip is connected with the frame via the connection wires, and the light-emitting chip, the connection wires, and partial portion of the frame are covered by the transparent material so as to suspend the light-emitting chip for generating 360-degree omni-directional light beams.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventor: Wen-Kung Sung
  • Publication number: 20080173891
    Abstract: A LED includes a first substrate having a recess, a second substrate having a polarity opposing that of the first substrate, a LED chip die-bonded on the recess, a bonding wire interconnecting the LED chip and the second substrate, and a case formed around the first substrate, the second substrate, the LED chip, and the bonding wire The case includes a curve rough surface on a front portion. The curve rough surface is adapted to diverge light emitted by the LED chip such that light can be transmitted toward a wider area. Either ridges or grooves are formed on the curve rough surface. The curve rough surface is formed by either injection molding in the packaging process of the case or adhering after the injection molding process.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Inventor: Albert Stekelenburg
  • Publication number: 20080173892
    Abstract: A package structure including a carrier, a molding element and a chip is provided. A part of the carrier is enclosed by the molding element. The molding element has a top portion and a bottom portion opposite to the top portion, wherein the top portion has a cavity exposing a part of the carrier and the bottom portion has a first protrusion and two second protrusions located at both sides of the first protrusion. The chip is disposed in the cavity and electrically connected to the carrier.
    Type: Application
    Filed: March 8, 2007
    Publication date: July 24, 2008
    Applicant: LIGHTHOUSE TECHNOLOGY CO., LTD
    Inventor: Wei-An Chen
  • Publication number: 20080173893
    Abstract: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.
    Type: Application
    Filed: May 25, 2007
    Publication date: July 24, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuya Hamaguchi, Hideki Haruguchi, Tetsujiro Tsunoda
  • Publication number: 20080173894
    Abstract: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity type is formed in the first anode region. A first semiconductor region of the first conductivity type is formed in contact with the semiconductor substrate. A second semiconductor region of the second conductivity type is formed adjacent to the first semiconductor region and in contact with the cathode layer. An intermediate electrode is formed on the surfaces of the first semiconductor region and the contact region.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tomoki Inoue
  • Publication number: 20080173895
    Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Inventors: Jer-Shen Maa, Tingkai Li, Douglas J. Tweet, Gregory M. Stecker, Sheng Teng Hsu
  • Publication number: 20080173896
    Abstract: A dynamic random access memory cell including a bottom oxide layer, a first semiconductor layer, a second semiconductor layer, an insulation layer, a gate and a doping layer is provided. The bottom oxide layer is disposed on a substrate. The first semiconductor layer disposed on the bottom oxide layer has a first doping concentration. The second semiconductor layer disposed on the first semiconductor layer has a second doping concentration lower than the first doping concentration. The insulation layer disposed on the bottom oxide layer at least situates at the two sides of the first semiconductor layer. The height of the insulation layer is greater than that of the first semiconductor layer. The gate is disposed on the second semiconductor layer. The doping layer disposed correspondingly to the two sides of the gate substantially contacts the second semiconductor layer and the insulation layer.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ta-Wei Lin, Wen-Jer Tsai
  • Publication number: 20080173897
    Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 24, 2008
    Inventors: Jianjun Cao, Sadiki Jordan
  • Publication number: 20080173898
    Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 24, 2008
    Applicant: NICHIA CORPORATION
    Inventor: Yuji Ohmaki
  • Publication number: 20080173899
    Abstract: There is provided a technology which allows sufficient protection of internal circuits from electrostatic discharge even when internal-circuit power source pads and internal-circuit GND pads are formed on an internal circuit region. Internal-circuit power source pads and internal-circuit GND pads are placed in the core region of a semiconductor chip. Between the internal-circuit power source pads and the internal-circuit GND pads, the internal circuits are formed. Between the internal-circuit power source pads and the internal-circuit GND pads, electrostatic protection circuits for protecting the internal circuits from a surge current are further formed. Each of the electrostatic protection circuits is composed of a discharge circuit for causing the surge current to flow therein and a control circuit for controlling the discharge circuit. The present invention is characterized in that the discharge circuits are placed in the core region and the control circuits are placed in an I/O region.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 24, 2008
    Inventors: Koichiro TAKAKUWA, Kazuo Tanaka
  • Publication number: 20080173900
    Abstract: A thin film transistor array panel is provided, which includes a substrate including a display region, a chip region, and a pad region; a plurality of signal lines formed on the substrate for electrically connecting the pad region to the chip region and the display region, wherein the signal lines have pads as an end portion and the pads are formed in the pad region; an insulating layer covering the signal lines and having a plurality of contact holes exposing the portions of the signal lines; a plurality of contact assistants formed on the insulating layer and connected to the pads through the contact holes; and a plurality of connection member respectively connected to the contact assistants and formed on the insulating layer for selectively electrically connecting the signal lines, wherein the insulating layer has a boundary line formed by etching, and the boundary line is crenellated.
    Type: Application
    Filed: October 31, 2007
    Publication date: July 24, 2008
    Inventors: Joo-Sun Yoon, Yong-Ho Yang
  • Publication number: 20080173901
    Abstract: The present invention relates to a field effect transistor (FET) containing a channel extending perpendicularly across at least one V-shaped trench and along the interior surfaces thereof. In one aspect, a semiconductor device is provided that includes a semiconductor substrate having first and second device regions that are isolated from each other by an isolation region. The first device region has a planar surface with a first crystalline orientation, and the second device region has at least one V-shaped trench which has interior surfaces with a second, different crystalline orientation. A first FET is located at the first device region and contains a channel extending along the planar surface of the first device region. A second, complementary FET is located at the second device region and contains a channel extending perpendicularly across the at least one V-shaped trench and along the interior surfaces thereof.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 24, 2008
    Applicant: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Publication number: 20080173902
    Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 24, 2008
    Inventors: Jiro MATSUDA, Masanori Nagase, Shu Takahashi
  • Publication number: 20080173903
    Abstract: A solid-state image pickup element equipped with a film stack, a color filter, and a microlens on a semiconductor substrate equipped with a light receiving section, comprises a first film with a high refractive index and a second film with a low refractive index adjacently arranged on the semiconductor substrate in this order viewing from the semiconductor substrate side, each of which has at least one layer respectively. Thereby it makes possible to reduce the loss of incident light, and to achieve the enhancement in photoelectric conversion efficiency.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 24, 2008
    Applicant: FUJIFILM Corporation
    Inventors: Fumikazu Imai, Akihiro Anzai
  • Publication number: 20080173904
    Abstract: A CMOS image sensor with a bonding pad comprises a semiconductor substrate having a pixel region and a circuit region; a passivation layer having an opening over the semiconductor substrate; and a bonding pad in circuit region, the bonding pad without extending to an upper surface of the passivation layer.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chyi Liu, Shih-Chi Fu, Yuan-Hung Liu, Wei-Chih Chen, Chi-Hsin Lo
  • Publication number: 20080173905
    Abstract: A solid state imaging device comprises: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and a gate electrode that transfers the signal charge from the photoelectric converting portion to the charge transfer path, wherein the gate electrode comprises polysilicon having a different conductive type from that of a semiconductor region forming a charge storing portion of the charge transfer path.
    Type: Application
    Filed: December 7, 2007
    Publication date: July 24, 2008
    Inventors: Masanori NAGASE, Jiro Matsuda, Tsuneo Sasamoto, Toshiaki Hayakawa
  • Publication number: 20080173906
    Abstract: The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Thomas W. Dyer
  • Publication number: 20080173907
    Abstract: A field effect transistor of the present invention includes a pair of ohmic electrodes 2 and an n-type GaAs layer 1 formed between the pair of ohmic electrodes 2 and having recesses. Crank-shaped gate fingers 4 and 5 are formed within the recesses of the n-type GaAs layer 1 between the pair of ohmic electrodes 2, and each crank-shaped gate finger includes perpendicularly extending portions and parallelly extending portions relative to the [0, 1, 1] crystal orientation of the n-type GaAs layer 1. The portion of the n-type GaAs layer 1 between the gate fingers 4 and 5 continuously extends from the input ends of the gate electrodes to the terminal ends thereof. A non-active region 8 is formed around each perpendicularly extending portion of the gate fingers 4 and 5.
    Type: Application
    Filed: August 2, 2007
    Publication date: July 24, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takahiro Nakamoto
  • Publication number: 20080173908
    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
  • Publication number: 20080173909
    Abstract: An image sensor having a plurality of pixels; each pixel includes one or more photosensitive elements that collect charge in response to incident light; one or more transfer mechanisms that respectively transfer the charge from the one or more photosensitive elements; a charge-to-voltage conversion region having a capacitance, and the charge-to-voltage region receives the charge from the one or more photosensitive elements; a first reset transistor connected to the charge-to-voltage conversion region; a second reset transistor connected to the first reset transistor, which in combination with the first reset transistor, selectively sets the capacitance of the charge-to-voltage conversion regions from a plurality of capacitances.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventor: Christopher Parks
  • Publication number: 20080173910
    Abstract: An image sensor that can include a photodiode formed on one side of a substrate to receive light and then generate signal charges based on the light; and a transistor converting the signal charges into predetermined voltage and transmitting the voltage to an output terminal, whereby the transistor directly contact and surrounds the photodiode.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 24, 2008
    Inventor: Woo-Seok Hyun
  • Publication number: 20080173911
    Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 24, 2008
    Inventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa
  • Publication number: 20080173912
    Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.
    Type: Application
    Filed: November 16, 2007
    Publication date: July 24, 2008
    Inventors: Yoshinori KUMURA, Tohru Ozaki, Susumu Shuto, Yoshiro Shimojo, Iwao Kunishima
  • Publication number: 20080173913
    Abstract: In one aspect of the present invention, a semiconductor device may include a support member, a FinFET provided on the support member, which has a first fin, a source region provided in the first fin, a drain region provided in the first fin, and a gate electrode provided on the first fin via an gate insulating layer, and a capacitor provided on the support member, which has a second fin, a third fin and a dielectric layer provided between the second fin and the third fin.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji KOJIMA
  • Publication number: 20080173914
    Abstract: A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 24, 2008
    Inventors: Chiemi HASHIMOTO, Toshio Yamada
  • Publication number: 20080173915
    Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ming-Tsang Yang, Hao-Cheng Chang, Cheng-Ying Wu
  • Publication number: 20080173916
    Abstract: A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 24, 2008
    Inventor: Kiyohito NISHIHARA