Patents Issued in July 29, 2008
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Patent number: 7405102Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.Type: GrantFiled: June 9, 2006Date of Patent: July 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Tien Yu T. Lee, Craig S. Amrine, Victor A. Chiriac, Lizabeth Ann Keser, George R. Leal, Robert J. Wenzel
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Patent number: 7405103Abstract: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape and exposing bonding pads of the chip on the active surface respectively. Conductive material is deposited into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively. A multi-layered interconnection structure is formed on the tape on the opposite of the chip, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.Type: GrantFiled: December 27, 2005Date of Patent: July 29, 2008Assignee: VIA Technologies, Inc.Inventor: Wen-Yuan Chang
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Patent number: 7405104Abstract: A resin-encapsulated semiconductor device includes a semiconductor chip, a plurality of inner leads that are connected to a group of electrodes of the semiconductor chip, respectively, and an encapsulating resin that encapsulates a connection part located between the semiconductor chip and the inner leads. Each of the inner leads includes a protruded portion provided on a surface thereof on an outer side relative to the periphery of the semiconductor chip. The protruded portion protrudes in a thickness direction and is provided with a step portion formed in its side portion. The group of electrodes of the semiconductor chip is connected to surfaces of inner portions of the inner leads located on an inner side relative to their protruded portions, through electroconductive bumps, respectively. The encapsulating resin encapsulates the semiconductor chip and the electroconductive bumps and is formed to expose surfaces of the protruded portions.Type: GrantFiled: March 27, 2006Date of Patent: July 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Hiroshi Horiki, Toshiyuki Fukuda
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Patent number: 7405105Abstract: Provided is a stack package using an anisotropic conductive film (ACF) for reducing thermal stresses exerted on chip scale packages (CSPs) during the initial manufacture of stack packages from a plurality of CSPs and for facilitating the repair and/or rework of stack packages incorporating CSPs while reducing the likelihood of damage to the CSPs. In the stack package including a plurality of CSPs stacked using an ACF, each CSP will typically include a circuit board, a semiconductor chip mounted on and electrically connected to the circuit board, and solder balls or other conductive structures arranged the semiconductor chip on the peripheral regions of the circuit board. Also provided are methods for the initial production of such stack packages and supplemental methods for the repair and rework of such stack packages.Type: GrantFiled: September 28, 2007Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Han, Gil-Beag Kim, Sang-Young Kim, Yong-Jin Jung, Hyun-Ik Hwang
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Patent number: 7405106Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved.Type: GrantFiled: May 23, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: John J. Maloney, Robert M. Smith, Charles H. Wilson
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Patent number: 7405107Abstract: A semiconductor device has at least one semiconductor element, at least one radiator plate thermally connected with said semiconductor element, and a molded resin covering and sealing said semiconductor device and said radiator, wherein an outer main surface of the radiator plate and at least a part of the side surface adjoining the outer main surface are exposed from the molded resin.Type: GrantFiled: November 14, 2005Date of Patent: July 29, 2008Assignee: Denso CorporationInventors: Shusaku Nakazawa, Tsutomu Onoue, Hiroaki Mizuno, Hidehisa Nasu
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Patent number: 7405108Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.Type: GrantFiled: November 20, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Howard Hao Chen, Louis L. Hsu, Wolfgang Sauter
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Patent number: 7405109Abstract: A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.Type: GrantFiled: December 14, 2004Date of Patent: July 29, 2008Assignee: Avago Technologies General IP Pte LtdInventor: William S Burton
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Patent number: 7405110Abstract: The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form at least one implant region between and/or beneath the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies.Type: GrantFiled: July 31, 2006Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventor: Phong N. Nguyen
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Patent number: 7405111Abstract: The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured by reducing degasification of resist by reducing the area (resist area proportion, that is, the ratio of the area of resist to the whole area of a substrate) of resist pattern which is used depending on the conditions such as acceleration voltage or current density of a doping process.Type: GrantFiled: October 23, 2003Date of Patent: July 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hitomi Ushitani, Shou Nagao, Tomoyuki Iwabuchi
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Patent number: 7405112Abstract: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.Type: GrantFiled: June 15, 2006Date of Patent: July 29, 2008Assignee: Advanced Micro Devices, Inc.Inventor: Paul R. Besser
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Patent number: 7405113Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.Type: GrantFiled: August 1, 2007Date of Patent: July 29, 2008Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Chuan-Yi Wu, Chin-Chuan Lai, Yung-Chia Kuan, Wei-Jen Tai
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Patent number: 7405114Abstract: The present invention provides the laser irradiation apparatus that has a galvanometer mirror and an f-? lens optical system, can offset the change of the energy due to the transmittance change of the f-? lens, and can scan a laser beam while the change of the energy on a substrate is suppressed. Further, the laser beam energy that is incident on the lens is controlled in advance by combining the optical system changing the branching ratio of polarization of the laser beam and the optical system having dependence on direction of polarization of the laser beam and changed continuously according to the transmittance of the lens on which the laser beam is incident. The laser energy is controlled to offset the transmittance of the lens, and thereby energy fluctuation of the laser beam irradiation of a substrate can be prevented.Type: GrantFiled: October 15, 2003Date of Patent: July 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hirotada Oishi
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Patent number: 7405115Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: GrantFiled: November 2, 2004Date of Patent: July 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Patent number: 7405116Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.Type: GrantFiled: August 11, 2004Date of Patent: July 29, 2008Assignee: LSI CorporationInventors: Richard J. Carter, Wai Lo, Sey-Shing Sun, Hong Lin, Verne Hornback
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Patent number: 7405117Abstract: A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed.Type: GrantFiled: May 15, 2006Date of Patent: July 29, 2008Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Budong You
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Patent number: 7405118Abstract: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region.Type: GrantFiled: November 28, 2005Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventor: Satoshi Nakai
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Patent number: 7405119Abstract: A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.Type: GrantFiled: January 6, 2006Date of Patent: July 29, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzyh-Cheang Lee, Fu-Liang Yang, Jiunn-Ren Hwang, Tsung-Lin Lee
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Patent number: 7405120Abstract: Disclosed herein is a method of manufacturing a gate insulator and a thin film transistor (“TFT”) incorporating the gate insulator, including forming an oxygen-containing, conductive gate on a substrate; forming a gate insulator material layer on the substrate so as to cover the gate; and applying a heat treatment so as to diffuse oxygen from the oxygen-containing gate layer into the gate insulating material layer thereby forming the gate insulator.Type: GrantFiled: March 26, 2007Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-nyeon Lee, Ick-hwan Ko
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Patent number: 7405121Abstract: An interlayer insulating film (22) is formed on a semiconductor substrate. A conductive plug (25) is embedded in a via hole formed through the interlayer insulating film. An oxygen barrier conductive film (33) is formed on the interlayer insulating film and being inclusive of an area of the conductive plug as viewed in plan. A capacitor (35) laminating a lower electrode, a dielectric film and an upper electrode in this order is formed on the oxygen barrier film. An intermediate layer (34) is disposed at an interface between the oxygen barrier film and the lower electrode. The intermediate layer is made of alloy which contains at least one constituent element of the oxygen barrier film and at least one constituent element of the lower electrode.Type: GrantFiled: October 22, 2007Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventor: Wensheng Wang
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Patent number: 7405122Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.Type: GrantFiled: July 11, 2006Date of Patent: July 29, 2008Assignee: Industrial Technology Research InstituteInventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
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Patent number: 7405123Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.Type: GrantFiled: November 2, 2004Date of Patent: July 29, 2008Assignee: United Microelectronics Corp.Inventors: Jung-Ching Chen, Spring Chen, Chuang-Hsin Chueh
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Patent number: 7405124Abstract: A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.Type: GrantFiled: December 27, 2005Date of Patent: July 29, 2008Assignee: Powerchip Semiconductor Corp.Inventor: Ko-Hsing Chang
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Patent number: 7405125Abstract: Methods for forming a tunnel oxide structure device and methods for forming the structure are described. A structure comprising nitrogen is formed on a semiconductor substrate. The structure is oxidized. Nitrogen of the oxide structure is redistributed to form a region of concentrated nitrogen. Oxidizing the structure and redistributing the nitrogen is performed via radical oxidation. Nitrogen is added to the oxide structure. The region of concentrated nitrogen helps to regulate the depth of the added nitrogen.Type: GrantFiled: June 1, 2004Date of Patent: July 29, 2008Assignee: Macronix International Co., Ltd.Inventor: Szu-Yu Wang
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Patent number: 7405126Abstract: Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device includes a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval. A memory cell is formed on the surface of the substrate to connect the source region and the drain region, and has a plurality of nano-sized quantum dots filled with material for storing electrons. A control gate is formed on the memory cell and controls the number of electrons stored in the memory cell. It is possible to embody a highly efficient and highly integrated memory device by providing a memory device having nano-sized quantum dots and a method for manufacturing the same.Type: GrantFiled: July 18, 2007Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-bong Choi, Soo-doo Chae
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Patent number: 7405127Abstract: A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.Type: GrantFiled: April 28, 2006Date of Patent: July 29, 2008Assignee: Infineon Technologies AGInventor: Helmut Tews
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Patent number: 7405128Abstract: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.Type: GrantFiled: February 14, 2007Date of Patent: July 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Patent number: 7405129Abstract: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices.Type: GrantFiled: May 26, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Cherie R. Kagan, Christopher B. Murray, Robert L. Sandstrom, Dmitri V. Talapin
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Patent number: 7405130Abstract: A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.Type: GrantFiled: July 14, 2006Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventor: Takashi Saiki
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Patent number: 7405131Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.Type: GrantFiled: July 16, 2005Date of Patent: July 29, 2008Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)Inventors: Yung Fu Chong, Brian Joseph Greene
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Patent number: 7405132Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.Type: GrantFiled: October 3, 2005Date of Patent: July 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Arao, Atsuo Isobe, Toru Takayama
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Patent number: 7405133Abstract: A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.Type: GrantFiled: October 25, 2005Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Tomohiro Saito, Yoshihiro Uozumi
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Patent number: 7405134Abstract: Exemplary embodiments of the present invention provide a method of manufacturing a semiconductor device that can take a connection between layers without giving damage to a layer, which is underlying. The semiconductor device includes forming conductive members Ms and Md at a predetermined position of a semiconductor film, forming an insulating film on a whole surface of a substrate excluding the conductive members Ms and Md, and forming a conductive film that is connected to the semiconductor film with the conductive member Ms and Md.Type: GrantFiled: February 24, 2005Date of Patent: July 29, 2008Assignee: Seiko Epson CorporationInventors: Ichio Yudasaka, Hideki Tanaka
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Patent number: 7405135Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.Type: GrantFiled: May 17, 2006Date of Patent: July 29, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Patent number: 7405136Abstract: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.Type: GrantFiled: June 21, 2006Date of Patent: July 29, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Daniel Delprat, Eric Neyret, Oleg Kononchuk, Patrick Reynaud, Michael Stinco
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Patent number: 7405137Abstract: In a manufacturing method of a semiconductor device, a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing. A first cutting process is formed on one of the principal surfaces of the substrate to produce two cutting grooves between two neighboring ones of the plurality of semiconductor chips, each cutting groove being adjacent to one of the neighboring ones of the plurality of semiconductor chips. A second cutting process is performed on the other of the principal surfaces of the substrate to produce a cutting groove overlapping the two cutting grooves produced by the first cutting process.Type: GrantFiled: June 22, 2005Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Satoshi Terayama, Hirohisa Matsuki
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Patent number: 7405138Abstract: A semiconductor device capable mounting semiconductor elements having different functions without increasing the area of the semiconductor device, and its manufacturing method are presented. A part if wiring 104 is formed al so at the side surface of a semiconducter element 101, and bump electrodes 102 formed so as to be nearly on a same plane as the wiring 104 formed at the side surface of the semiconducter element 101, at least a part of ball electrodes 103 is formed so as to connect electrically to the wiring 104 at the side surface of the semiconductor element, the side surface of the semiconductor element is sealed with resin exposing the wiring 104, and the confronting surface of the circuit forming surface is sealed with resin.Type: GrantFiled: September 27, 2005Date of Patent: July 29, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
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Patent number: 7405139Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.Type: GrantFiled: August 3, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Jerome B. Lasky, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 7405140Abstract: A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patterned film area thereon. A Si film is non-selectively deposited onto the structure, the Si film comprising an epitaxial Si film deposited onto the epitaxial Si surface and a non-epitaxial Si film deposited onto an exposed surface of the patterned film. The non-epitaxial Si film is selectively dry etched away to form a patterned epitaxial Si film. The Si film may be a SiGe film.Type: GrantFiled: August 18, 2005Date of Patent: July 29, 2008Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Allen John Leith, Seungho Oh
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Patent number: 7405141Abstract: In a laser processing method and a laser processing apparatus which irradiate a processing target body with a laser beam pulse-oscillated from a laser beam source, a processing state is monitored by a photodetector, and the laser beam source is again subjected to oscillation control on the moment when erroneous laser irradiation is detected, thereby performing laser processing. Further, in a laser crystallization method and a laser crystallization apparatus using a pulse-oscillated excimer laser, a homogenizing optical system, an optical element and a half mirror are arranged in an optical path, light from the half mirror is detected by a photodetector, and a light intensity insufficient irradiation position is again irradiated with a laser beam to perform crystallization when the detection value does not fall within a range of a predetermined specified value.Type: GrantFiled: February 27, 2007Date of Patent: July 29, 2008Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Masayuki Jyumonji, Hiroyuki Ogawa, Masato Hiramatsu, Noritaka Akita, Tomoya Kato
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Patent number: 7405142Abstract: A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed.Type: GrantFiled: February 6, 2003Date of Patent: July 29, 2008Assignee: Sumco CorporationInventors: Ichiro Shiono, Masaharu Ninomiya, Hazumu Kougami
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Patent number: 7405143Abstract: The present invention produces a seed layer for the deposition of copper for metallizing integrated circuits. A diffusion barrier is deposited upon the wafer. In one embodiment of the invention, a metal oxide layer is then formed on the diffusion barrier. The oxidized metal is then reduced to a conductive lower oxidation state or to its elemental form. That metal is then used as the seed layer for the growth of copper. In another embodiment, the surface of the barrier layer is repeatedly oxidized and reduced in order to reduce incubation time for the growth of a seed layer. A ruthenium seed layer is then deposited over the treated barrier layer.Type: GrantFiled: March 25, 2004Date of Patent: July 29, 2008Assignee: ASM International N.V.Inventors: Miika Leinikka, Juhana J. T. Kostamo
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Patent number: 7405144Abstract: A method for manufacturing a probe card is provided. A first inactive layer, a first patterned photoresist layer and a first metal layer are sequentially formed on a substrate. The first metal layer has first through holes exposing a portion of the first patterned photoresist layer. A second inactive layer and a second patterned photoresist layer are sequentially formed thereon. The second patterned photoresist layer has second through holes exposing the first through holes. Pins are formed inside the first and the second through holes. A second metal layer is formed on the second patterned photoresist layer. One end of each pin is connected to the second metal layer. The pins and the second metal layer are taken out. A circuit carrier having third through holes is provided. The pins are inserted into the third through holes. The second metal layer is patterned to form pinheads.Type: GrantFiled: October 19, 2006Date of Patent: July 29, 2008Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventor: Jiun-Heng Wang
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Patent number: 7405145Abstract: An electrically and mechanically enhanced die-down tape substrate ball grid array (BGA) package substrate is described. An IC package includes a substrate that has a first surface. The first surface has a central opening. A stiffener/heat spreader has a first surface. The first surface of the stiffener has a central ground ring. The first surface of the stiffener is coupled to a second surface of the substrate. The central opening has an edge. The edge includes at least one of the following: (a) a protruding edge portion that extends across at least a portion of the central ground ring, (b) a recessed edge portion that exposes a portion of the central ground ring, or (c) a hole proximate to the edge, wherein the hole exposes a portion of the central ground ring.Type: GrantFiled: February 2, 2005Date of Patent: July 29, 2008Assignee: Broadcom CorporationInventors: Reza-ur Rahman Khan, Chong Hua Zhong
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Patent number: 7405146Abstract: An electroplating method by transmitting electric current from a ball side is provided. In the electroplating method, the circuit layer is firstly formed on the bump side of the IC board, and the electric current is transmitted to the portion of the circuit layer uncovered by the insulating layer formed on the bump side from the electroplated metal layer on the ball side to form the protective layer (the electroplated gold layer) on the portion of the circuit layer. In such a way, the electroplated gold layer cannot be formed under the insulating layer formed on the bump side (attached with the chip) because the electroplated gold layer is formed after the insulating layer has been formed, and thereby the fall-off of the insulating layer from the electroplated gold layer will not happen. Therefore, the reliability of the products is enhanced.Type: GrantFiled: January 24, 2006Date of Patent: July 29, 2008Assignee: Kinsus Interconnect Technology Corp.Inventor: Cheng-Kuo Ma
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Patent number: 7405147Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: GrantFiled: January 30, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7405148Abstract: A semiconductor device for being mounted on the display panel board of a display apparatus includes a substrate; a plurality of circuit units disposed on the substrate and including thin-film transistors, the circuit units having respective output terminals; at least one bus interconnect for supplying a voltage to the circuit units; and a power supply feed point for supplying a voltage from an external source to the bus interconnect. The pitch L (m) of the circuit units, the number N of the circuit units, and the resistance R (Q/m) per unit length of the at least one bus interconnect are related to each other as follows: R×N2×L?4×103.Type: GrantFiled: December 14, 2006Date of Patent: July 29, 2008Assignee: NEC CorporationInventor: Tamaki Toba
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Patent number: 7405149Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.Type: GrantFiled: May 24, 2002Date of Patent: July 29, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7405150Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: November 14, 2005Date of Patent: July 29, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7405151Abstract: A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 ?. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.Type: GrantFiled: May 30, 2006Date of Patent: July 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gin Jei Wang, Chao-Hsien Peng, Chii-Ming Wu, Chih-Wei Chang, Shau-Lin Shue