Abstract: The object of the invention is a software method of emulation of the EEPROM memory in another non-volatile memory, for example the Flash type memory. This method is applicable in systems, where in order to decrease costs of devices, using a non-volatile EEPROM memory, the existing memory is used, for example the Flash type memory for emulation of the EEPROM memory.

Abstract: An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a code generator that supplies control routines to the microprocessor during at least part of the in-circuit programming operations. The code generator allows the in-circuit programming code to be updated in real time.

Abstract: Provided are a method, system, and machine readable medium for using multiple non-volatile memory devices to store data in a computer system. Access to a first and second memory devices are managed. The first memory device has faster read access and slower write access relative to the second memory device and the second memory device has slower read access and faster write access relative to the first memory device. Write requests to the first memory device are cached in the second memory device.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: An information read/write device has a first processor for instructing a second processor to write information onto or read information from a recording medium. The recording medium has a random access memory module which allows both processors to read or write data to the memory module. The second processor controls a scanning module for the recording medium, a write signal processing module and a read signal processing module. The read/write device is easy-to-operate while using a minimum of electric power consumption with prevention against electromagnetic interference (EMI) making the invention suitable for use in hand-held devices.

Abstract: Broadly speaking, a method and an apparatus is provided for processing access commands directed to a striped configuration of disks. More specifically, the method and apparatus determines a physical block address corresponding to a logical address in a redundant array of independent disks level 0 (RAID 0) system. Bit-level operations are incorporated to determine a disk in the RAID 0 system and a block number on the disk that corresponds to a particular logical address. Since the bit-level operations replace traditionally required division and modulo operations, the method and apparatus provides for more efficient processing of access commands directed to the RAID 0 system.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.

Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.

Abstract: A system and method for improving the speed of packet switching in a routing platform that maps shared I/O memory into two address spaces. The first address space is mapped with the cache attribute and uses the cache write through attribute. Addresses in this address space are not equal to the physical address in the shared I/O memory and are translated to the physical addresses. Code executed by the CPU to switch packets utilizes the first address space to access packet data. The second address space is mapped with the non-cache attribute and addresses in this space are equal to the physical addresses in the shared I/O memory. The second address space is utilized by I/O devices when accessing shared I/O memory. Addresses of buffers for storing packet data in the shared I/O memory are converted from the first address space to the second address space when given to I/O devices.

Abstract: A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: There are provided a multisystem network, and a device and method for access to a data storage unit in order to allow processors in a plurality of devices to access the data storage unit. The data storage unit has a data storage area divided in a first area for a first device and a second area for a second device. The first and second devices are connected to the data storage unit via a connection circuit. A first processor in the first device can access directly the data storage unit. The connection circuit has provided therein an emulation register corresponding to a register which stores a command or control data used for the first processor in the first device to access the data storage unit. A second processor in the second device accesses the data storage unit via the emulation register and with intervention of the first processor.

Abstract: A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the second device writes in the memory. The buffer of the memory controller temporarily stores cached data and the write data to be written on write access to the memory by the second device, which enables maintenance of data coherency while avoiding a write access retry by the second device.

Abstract: An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.

Abstract: A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Abstract: A method for implementing the invention is carried out in a data-storage system having a data storage unit that includes at least two constituent data storage elements. Each of the constituent data storage elements is either in a first state or a second state. The method includes providing a data structure having an entry corresponding to the data storage unit. The entry includes status information indicating whether at least one constituent data storage element of the data storage unit is in the first state. These entries are updated as necessary following any changes in state of the constituent data storage element. Scanning the data storage units instead of the data storage elements provides a more efficient way to locate data storage elements in the first state, particularly where such data storage elements are rare.

Abstract: In one example, an apparatus is provided to store data in one or more data storage systems by selecting from among at least a first operating mode and a delta replication operating mode. The apparatus comprises a means for storing data pursuant to the first operating mode and a means for ascertaining a first status of a criterion pertaining to an activity performed by the one or more data storage systems while operating in the first operating mode. The apparatus further comprises a means for detecting a change in the criterion to a second status, and a means for storing data pursuant to the delta replication operating mode in response to the change.

Abstract: A semiconductor device 10 sets a pass-through flag to ON when the top address of a write-prohibited area is passed. When a request to write data to a write-restricted area WRA is received, the semiconductor memory device 10 determines whether or not the pass-through flag is set to ON, and if the pass-through flag is not set to ON, the semiconductor memory device 10 executes writing of the data to the write-restricted area. On the other hand, if the pass-through flag is set to ON, the semiconductor memory device 10 does not execute writing of the data to the write-restricted area.

Abstract: It is desirable that data stored in an old storage device is migrated to a new storage device without any interruption. According to a computer system of this invention, in a first data storage device, a second data storage area of a second data storage device is recognized as a virtualized data storage area of the first data storage device, a data copy relation between the first data storage area and the virtualized data storage area is established, the second data storage area is recognized from the computer based on the data copy relation, data is copied from the first data storage area to the virtualized data storage area based on the data copy relation, and after completion of a data copy operation, a connecting path is switched from the first data storage area to the second data storage area based on the data copy relation.

Abstract: A method, apparatus and program storage device for providing virtual disk service hints based storage. Virtual disk service hints are provided. The virtual disk service hints are analyzed to determine a configuration model to implement. The storage system is then configured according to the configuration model identified using the virtual disk service hint.

Abstract: The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.

Abstract: A method is presented for utilizing tape storage media segmentation to improve data access performance. A segmented tape storage medium within a tape cartridge having a first and second segment is utilized. A selection module allows a user to select a user-defined capacity of the tape storage medium that is less than the usable capacity of the tape storage medium. The user-defined capacity allows the user to prefer improved data access over tape storage capacity. Data, when written to the tape, is written only within the user-defined capacity. Data may be written exclusively on the first segment or written on both the first segment and second segment allowing data access to be improved. In addition, the user-defined capacity may correspond to the full capacity of the tape storage media.

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract: A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other nodes through an expansion port (or scalability port). The method also starts an access of a memory in response to the request for data and snoops a processor cache of each processor in each node. The method accordingly identifies the location of the data in either the processor cache or memory in the node having the processor issuing the request or in a processor cache or memory of another node. A method for requesting data between two directly coupled nodes in a router system is also disclosed. A method for requesting data between three or more nodes in an interconnect system is also disclosed. A method for resolving crossing cases in an interconnect system is also disclosed.

Abstract: An autonomic computing environment is provided by sequestering one of a plurality of processor resources, partitioning a memory, and hiding an input/output (I/O) device. One processor resource is sequestered such that the sequestered processor resource is not exposed to the remaining processor resources as a processor resource. A memory region is partitioned to provide a service processing portion such that the sequestered processor resource has access to all of the memory region and the remaining processor resources have access to at least a portion of the memory region but do not have access to the service processing portion. A first I/O device is hidden such that the sequestered processor resource has access to the first I/O device and the remaining processor resources do not have access to the first I/O device.

Abstract: Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual communication channels operate at individually controllable clock speeds. Data messages sent between nodes pass at the speed of the communication channels. These data messages are sent by a sending port that includes registers for storing data and registers for protocol signals that control the timing and movement of the data. Data crosses clock boundaries without data loss. At least some of the microprocessors include fork functions that output a data stream to more than one output port. Similarly, at least some of the microprocessors include join functions that can create a single data stream from inputs from more than one input port.

Abstract: There is provided a system having an execution core operable to execute internal instructions. A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions. A remapper is responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer. Thus one or more internal instructions from said corresponding internal instruction block can be supplied to execution core.

Abstract: A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.

Abstract: A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.

Abstract: A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

Abstract: Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each having an instruction address, to obtain an instruction width, registers for holding the loop setup instruction address and the loop bottom offset, and a loop bottom detector, responsive to a current instruction address, a current instruction width, the loop setup instruction address and the loop bottom offset, configured to determine if a next instruction is a loop bottom instruction.

Abstract: A method, system and article of manufacture to boot a computer system from a remote Basic Input/Output System (BIOS) image. A request for a local Basic Input/Output System (BIOS) image of a computer system is intercepted by a controller of the computer system. A remote BIOS image for the computer system is retrieved from a remote computer system communicatively coupled to the computer system via the controller. The remote BIOS image is executed by the computer system.

Abstract: Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first operand for a Boolean operation, the value of the operand is determined. This may include evaluating a GUID. When an operator and a second operand are encountered, a decision is made as to whether the second operand should be evaluated. The determination as to whether the second operand should be evaluated is made based upon the value of the first operand and the type of operator. If the second operand need not be evaluated, no evaluation is performed thereby saving time and memory space. The evaluation of the Boolean expression continues in this manner until the entire expression has been evaluated. If the Boolean expression is evaluated as true, the program module associated with the Boolean expression may be loaded.

Abstract: A system for protecting software against piracy while protecting a user's privacy enables enhancements to the protection software in a user device and extended protections against piracy. The protection system allows the user device to postpone validation of purchased tags stored in a tag table for installed software and to re-establish ownership of a tag table to recover from invalidation of a tag table identifier value resulting from revelation of a tag table identifier value. Continued use of the tag table is provided by the use of credits associated with a tag table. A protection center is protected against denial of service attacks by making calls to the protection center cost time or money to the attackers.

Abstract: A certification method realized by a certification server is applied to a networking system containing at least one local network connecting together terminals that constitute a same group to share a local session therebetween. When one terminal requests certification, the certification server sends an inter-group ID to the terminal while sending an authentication request to each of the other terminals of the same group. Then, the certification server determines to perform certification on the terminal based on results of authentication that is performed by each of the users of the other terminals in a face-to-face manner. Herein, the certification server can determine whether to certify the terminal based on secret information, which are disassembled and allocated to the terminals respectively. Thus, it is possible to reliably perform certification and authentication on terminals and users.

Abstract: A method of packet encryption and decryption that allows for pipelining. The first step is to identify the packets in a message to be encrypted. Then, a unique number is assigned to each packet. A value R is acquired. Then, a first register is initialized. An initialization vector IV is generated. Then, the first register is stepped a user-definable number of times. Then, a packet is selected. R and the unique number are combined. Then, a second register is initialized. A checksum is generated. Then, the packet is divided into blocks. A block is selected. Then, the checksum is combined with the block and designated the checksum. The block is encrypted. Then, the first and second registers are stepped. These steps are repeated for each block. Then, the checksum is encrypted. After the blocks are encrypted, the unique number, IV, the ciphertext of each block, and the encrypted checksum are transmitted. If there are any other packets to encrypt then the steps are repeated.

Abstract: A system for the secure transfer of data and data management on the Internet has a data encryption and transfer module operable in a user computing system, a data management module operable in a sewer computing system, the transfer of data between the user and the server computing systems being effected on the user computing system through use of the data encryption and transfer module, by moving the data to or from a first desktop window, associated with the user computing system, from or to a second desktop window, associated with the server computing system, each window being associated with a password, such that the step of moving the data from one window to the other causes the data to encrypted/re-encrypted from one associated password to the other.

Abstract: Techniques for efficiently authenticating multiple objects and clustering objects based on access patterns are provided. For example, in an illustrative aspect of the invention, a technique for generating and/or reading authentication information, wherein the authentication information provides evidence that a plurality of objects were one of generated and sent by an entity, comprises using one or more object access patterns indicative of whether at least two of the plurality of objects are accessed within a similar time period to group objects together to reduce an overhead for at least one of generating and reading the authentication information.

Abstract: A system on a chip (SOC) device is disclosed comprising external outputs, and external inputs. A first secure storage location is operably decoupled from all of the external outputs of the SOC device during a normal mode of operation. By being decoupled from all external outputs, representations of the data stored at the first secure device are prevented from being provided to the external outputs. The decryption engine is also included on the system on a chip, comprising a first data input, and a private key input coupled to a first portion of the first secure storage location, and an output coupled to a second secure location. The decryption engine is operable to determine decrypted data from data received at the first data input based upon a private key received at the private key input. The decryption engine is further operable to write the decrypted data only to the first secure memory location and the second secure location.

Abstract: Methods and apparatus, including computer program products, for presenting status of digital signatures. A digital document is received that defines a presentation structure and includes a digital signature. The digital document specifies a representation of the digital signature and a location in the presentation structure for the representation of the digital signature. A status is determined for the digital signature. A status representation is associated with the digital signature, where the status representation identifies the status determined for the digital signature. Without altering the representation of the digital signature, at least a portion of the digital document and the status representation of the digital signature are presented in a user interface, where the status representation is presented in the presentation structure at a location that depends upon the location of the digital signature.

Abstract: A key fragment generator accepts a key string, such as from a key string generator, and produces a plurality of key fragments that can be entered by a human with a lower likelihood of error than if the human attempted to enter the original key string. A key defragmenter accepts a plurality of entered key fragments, reconstitutes the original key string from the entered key fragments and, optionally, provides the reconstituted key string to a software package or other license manager. The key fragment generator can produce “friendly” key fragments that are easier for humans to read and enter than the arbitrary character strings that characterize typical key strings. The key fragment generator can produce “error-detectable” key fragments. If an error-detectable key fragment is entered incorrectly, the key defragmenter can generate an error message and permit a user to enter the key fragment again. The key fragment generator can produce “error-correctable” key fragments.

Abstract: A method, system and computer program product for ensuring a biometric template is associated with a live entity comprising an intelligent biometric scanner in processing communications with a computer system and a security token. The intelligent biometric scanner applies a data transformation to an inputted entity biometric sample and a biometric challenge supplied by a security token. The transformed biometric sample is processed by a computer system using the transformed biometric challenge resulting in an transformed entity biometric template which will not match an enrollment template stored inside the security token until the transformation is reversed by the intelligent biometric scanner. Embodiment of the invention are also disclosed which does not require the use of a challenge.

Abstract: Data generated by certain peripheral devices, such as a coin or bill validator, within a gaming device is encrypted using a randomly generated key transmitted to the peripheral device by a main control unit in the gaming device. The peripheral device sends the encrypted data to the main control unit along with the clear text data. The control unit performs a reverse algorithm to recover the data from the encrypted number. The control unit compares the recovered data to the clear text data. If there is a match, the control unit acts on the data, such as by booking the coin value to a credit meter.

Abstract: Systems and methods are provided for protecting electronic content from the time it is packaged through the time it is experienced by an end user. Protection against content misuse is accomplished using a combination of encryption, watermark screening, detection of invalid content processing software and hardware, and/or detection of invalid content flows. Encryption protects the secrecy of content while it is being transferred or stored. Watermark screening protects against the unauthorized use of content. Watermark screening is provided by invoking a filter module to examine content for the presence of a watermark before the content is delivered to output hardware or software. The filter module is operable to prevent delivery of the content to the output hardware or software if it detects a predefined protection mark. Invalid content processing software is detected by a monitoring mechanism that validates the software involved in processing protected electronic content.

Abstract: The invention relates to a memory card (2) which is arranged to be inserted in a memory card slot (4) of an electronic device (1), information being arranged to be stored in the memory (5) of the memory card (2). The information to be stored is at least partly arranged to be encrypted by means of a password, wherein this encrypted information is arranged to be stored in this encrypted format in the memory (5) of the memory card (2). The information to be read from the memory (5) of the memory card (2) is arranged to be retrieved at least partly in encrypted format from the memory (5) of the memory card (2), wherein the information to be retrieved is arranged to be decrypted by means of the password. The invention also relates to an electronic device (1) in which at least one memory card (2) is used for storing at least some information.

Abstract: Medium individual information formed an information recording medium is obtained, and a management key used for recording or regeneration on the information recording medium corresponding to the medium individual information is generated, and the predetermined information is encoded to create encode data by using the management key when recording predetermined information, the encode data recorded on the information recording medium is decoded to create decode data by using the transferred management key when regenerating the predetermined information.

Abstract: An apparatus, a method, and a computer program are provided for distinguishing relevant security threats. With conventional computer systems, distinguishing security threats from actual security threats is a complex and difficult task because of the general inability to quantify a “threat.” By the use of an intelligent conceptual clustering technique, threats can be accurately distinguished from benign behaviors. Thus, electronic commerce, and Information Technology systems generally, can be made safer without sacrificing efficiency.

Abstract: There is provided a controller that prevents any external power source from supplying its power if a host device and a monitoring device are not connected exactly through optical extension cables based on DVI standard, and that prevents a sequence for digital transmission of a video signal from being started if the external power source remains off. Only when the proper (DDC+5V) signal is generated from the host device and the external power source has been turned on, the (DDC+5V) signal is transmitted to the monitoring device, and when it is detected in the monitoring device that the transmitted signal is the proper (DDC+5V) signal, the (DDC+5V) signal is transmitted to the monitoring device.