Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

Abstract: An output system including an output data storage section storing output data, an output data saving section saving the output data to the storage section, an authentication information acquiring section acquiring authentication information, a usability determining section determining usability of the output data depending on acquired authentication information, a power control section controlling power to the network device, an output data transmitting section sending, to the network device, usable output data, and a power-save switchover section switching between an operating status and a power-save status. The power control section forwarding, to the power-save switchover section, a power-save cancel command for transition into the operating status after the output data is determined usable and before the transmitting section sends the output data.

Abstract: A portable information handling system is provided that monitors one or more sensed conditions to determine if the system is currently placed in an unusable state. If the system determines that it has been placed in an unusable state such as being placed in the dark or upside down, then a reduced power mode is entered. Significant power savings are thus achieved because the system consumes power at a substantially reduced rate when it is determined to be in an unusable state.

Abstract: In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.

Abstract: A power over Ethernet controller comprising: control circuitry; at least one temperature sensor operatively connected to the control circuitry; and a plurality of electronically controlled switches responsive to the control circuit, each of the electronically controlled switches enabling power to a respective port and having associated therewith inrush current limiting functionality, the control circuit being operative to input at least one temperature indication from the at least one temperature sensor; operate at least one of the plurality of electronically controlled switches thereby enabling power to a first port; and delay a time period dependent on the at least one temperature indication, whereby operation of a second of the plurality of electronically controlled switches to enable power to a second port is permitted only after the delayed time period.

Abstract: A control unit featuring clocked data transmission between a processor and at least one further circuit, the processor itself outputting the clock pulse. The processor monitors the clock pulse based on the output signals of at least two clock outputs.

Abstract: Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines.

Abstract: An embodiment of the invention is a technique for monitoring via a universal multipath driver (UMD) a first path to one of a plurality of virtual device objects. The virtual device objects are created by the UMD and correspond to a plurality of functional device objects. The functional device objects are created by a plurality of lower level drivers and correspond to a plurality of real physical devices having M device types including an external boot device. The UMD is a functional driver of each of the functional device objects. The lower level drivers control the real physical devices. The UMD detects a failure of the first path to a first virtual device object corresponding to a first real physical device and performs one of failover and failback for the first real physical device.

Abstract: A highly available transaction recovery service migration system in accordance with one embodiment of the present invention implements a server's Transaction Recovery Service (TRS) as a migratable service. In one embodiment of the present invention, the TRS is a server instance or software module implemented in JAVA. The TRS migrates to an available server that resides in the same cluster as the failed server. The migrated TRS obtains the TLOG of the failed server, reads the transaction log, and performs transaction recovery on behalf of the failed server. The migration may occur manually or automatically on a migratable services framework. The TRS of the failed server migrates back in a fail back operation once the failed primary server is restarted. Failback operation may occur whether recovery is completed or not. This expedites recovery and improves availability of the failed server thereby preserving the efficiency of the network and other servers.

Abstract: A RAID system includes a pair of RAID controllers adapted to operate in active-active mode, each controller including a cache memory and at least one SAS/SATA I/O chip connected to a plurality of hard disk drives. Each SAS/SATA I/O chip includes more SAS/SATA ports than required to carry data to the hard drives. The caches in the respective controllers are synchronized via the extra SAS/SATA ports in each controller.

Abstract: In one embodiment, a computer-implemented system for compiling a fuse assembly for a memory is disclosed. The claimed embodiment comprises: means for defining a memory group including at least one memory instance, each memory instance being characterized by its memory configuration data; means for determining number of fuses required for each memory instance based on its configuration data; means for automatically passing fuse information relating to the number of fuses to a fuse compiler; and means for generating, based on the fuse information, a fuse box assembly having a plurality of fuses organized into a set of fuse segments, each segment corresponding to a particular memory instance of the memory group.

Abstract: Disclosed is a data storage architecture that provides data regeneration following the failure of two storage domains and that provides conversion for RAID-6 to RAID-5 or RAID-0 without moving or copying any data. A storage grid comprising at least eight domains and twelve rows contains user data in a first contiguous portion and may contain row parity data in a second continuous portion and may contain vertical parity data in a third contiguous portion. In one embodiment data is arranged in row and vertical sets each comprising four data blocks such that each user data block is a member of one row set and is a member of one vertical set. In another embodiment sets comprise two blocks each.

Abstract: A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the SAN manager outputs a corresponding relationship between virtual and real volumes. Meanwhile, the failure notification messages received from the in-SAN devices are construed to detect and output an influence of the failure upon the access to a real or virtual volume. Furthermore, when receiving a plurality of failure notifications from the devices connected to the SAN, the plurality of failure notifications are outputted with an association based on the corresponding relationship between real and virtual volumes.

Abstract: In the case where there coexist general loads requiring backup only for a short duration and a specific load requiring backup for a longer duration, uninterruptible power with higher reliability is supplied to the specific load with the adoption of a simple configuration. A DC backup power supply system comprises an AC/DC converter for normally supplying DC power to loads in while (the general loads and the specific load, included), and a control circuit for supplying DC output backing up the loads in whole for relatively short time only from a battery at the time of a power outage, while supplying DC output backing up the specific load, such as a cache memory and so forth, for relatively long time. Thus, it is possible to implement an uninterruptible power supply system small in size and low in cost, provided with a function for proper use depending on a prevailing situation.

Abstract: A method is provided for saving system information immediately following a hardware or software failure that causes a processor to reset. After failure is imminent and before the processor allows the reset to occur, the processor is instructed to copy a fixed amount of the system stack SRAM, in addition to any processor registers that can be used to determine the reset cause, into a preserved area of SRAM. During the initialization sequence, the preserved area of SRAM is tested, but not overwritten. This allows all of the preserved SRAM data including previous stack contents and register settings at the time of the failure to be available for analysis.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, prohibit breakpoints from being set within a protected range. In an embodiment, a protected range may be an atomic operation synchronization code range, either based on instructions generated by a compiler or based on source statements that are compiler directives. When a command, such as an add breakpoint command is received, the address of the breakpoint is compared to the protected range, and if the address is within the protected range, the breakpoint is not set. In another embodiment, if the address is within the protected range, the breakpoint is set before the start or after the end of the protected range. In this way, the problems of endless loops may be obviated.

Abstract: A method, apparatus and computer program product for generating a test script for use by a test agent is presented. A first test script is generated in a first language. A determination is then made whether to generate an intermediate test script from the first test script. When the determination is made not to generate an intermediate test script then the first test script is converted into a second test script in a second language, and the first test script is also converted into a callback test script. When the determination is made to generate an intermediate test script then an intermediate test script is generated from the first test script. The intermediate test script is converted into a second test script in a second language, and the intermediate test script is converted into a callback test script. The second test script and the callback test script are compiled into a final test script.

Abstract: The present invention provides for a method and apparatus for comparison of network systems using live traffic in real-time. The inventive technique presents real-world workload in real-time with no external impact (i.e. no impact on the system under test), and it enables comparison against a production system for correctness verification. A preferred embodiment of the invention is a testing tool for the pseudo-live testing of CDN content staging servers, According to the invention, traffic between clients and the live production CDN servers is monitored by a simulator device, which then replicates this workload onto a system under test (SUT). The simulator detects divergences between the outputs from the SUT and live production servers, allowing detection of erroneous behavior. To the extent possible, the SUT is completely isolated from the outside world so that errors or crashes by this system do not affect either the CDN customers or the end users. Thus, the SUT does not interact with end users (i.e.

Abstract: A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.

Abstract: A system operates to receive status messages from banking machines (12) operating in a network (14). The messages are received by an event management system (20) operating at least one computer (54). The computer is in operative connection with a data store (52). The data store includes information representative of the banking machines in the network, status messages generated by the banking machines and actions to be taken including entities to be notified of conditions which cause status messages to be sent by the various banking machines. The event management system receives the messages and places them in a uniform standard message format for further processing by the system. A device status processing program (36) in the computer resolves an action to be taken responsive to the status message.

Abstract: Improved approaches for evaluating performance of data storage systems used with computers are disclosed. The performance evaluation of the data storage systems utilizes dynamic performance evaluation by use of data throughput as a diagnostic. The data storage systems include, for example, either disk drives or RAIDs. In one embodiment, the invention identifies a sustained performance rate for a disk drive or RAID.

Abstract: A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.

Abstract: A system and method that includes scoring logic for handling errors in a data storage environment by employing risk scoring. Architecture for handling errors with scoring logic is provided. A program product enabled for carrying out methodology described herein is also provided. An apparatus for handling errors using risk scoring is provided.

Abstract: A method and apparatus utilizes an exception handler to implement LOAD and STORE instructions for moving data between a peripheral device and CPU registers. TLB entries for peripheral devices are flagged invalid during initialization and an exception handler occurs when LOAD or STORE instructions are executed by the CPU. The exception handler programs a data mover to perform the LOAD or STORE instruction so that the CPU will not hang up in the event that the peripheral device does not respond thereby avoiding reset of the SOC by the watchdog timer. If the peripheral device does not respond before an exception handler timer expires an error is indicated by the exception handler.

Abstract: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.

Abstract: A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.

Abstract: A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain output multiplexer is coupled to the plurality of scan sub-chains for sequentially selecting only one of the scan sub-chains in response to a scan sub-chain control signal. A scan sub-chain controller generates the scan sub-chain control signal and gates a scan clock signal to only a scan clock input of the selected scan sub-chain.

Abstract: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

Abstract: To facilitate testing, some integrated circuits include built-in test circuits, called test-access ports (TAPs). The present inventor recognized that TAPs are sometimes used with automatic testers that have limitations, such as insufficient memory capacity, that make it difficult or costly to test some integrated circuits, such as microprocessors. Accordingly, this disclosure teaches, among other things, inputting test signals to a TAP of an integrated circuit using a first device, such as an automatic tester, and outputting state data related to the input test signals from the TAP using a second device.

Abstract: Techniques are provided for capturing external signals at output pins on a programmable logic integrated circuit (IC) during a boundary scan test. A JTAG sample signal is routed to an input/output block on a chip and active during a JTAG sampling phase. An input buffer coupled to an output pin is turned on during the JTAG sample phase. Logic gates enable the input buffer in response to the JTAG sample signal so that the input buffer can capture a signal on the pin. The input buffer is turned off after the JTAG sampling phase to conserve power. The output buffer coupled to the pin that receives the test signal is tristated to prevent contention during the JTAG sampling phase. The techniques of the present invention can be used to test board level interconnects in less time and are easy to implement.

Abstract: A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

Abstract: A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table to detect, diagnose and/or predict fault conditions and/or degraded performance. The method includes positioning a plurality of wafers in a processing chamber in the thermal processing system, performing a self test process, determining a real-time transient error from a measured transient response and a baseline transient response determined by a BIST rule stored in the BIST table, and comparing the transient error to operational limits and warning limits established by the BIST rule for the self test process.

Abstract: A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).

Abstract: A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobes should be generated; a strobe generating circuit for generating the plurality of strobes; and an adjusting module for adjusting a timing of the strobe generating circuit's generating each of the strobes on the basis of the signal for adjustment.

Abstract: A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead size.

Abstract: Provided are methods for encoding and decoding low-density parity-check (LDPC) codes and a method for forming an LDPC parity check matrix. The method for forming the LDPC parity check matrix, includes the steps of: preparing a plurality of parity check matrixes; and selecting a parity check matrix having maximum performance from the prepared parity check matrixes, wherein the parity check matrix has a degree distribution G(x) that meets an equation, G ? ( x ) = ? k = 2 d i - 1 ? a k ? x k + ? k = d i d max ? C ? ? k - ? ? x k ? ? or ? ? G ? ( x ) = ? ? k = 2 d max ? C ? ( k + ? ) - ? ? x k , where, ak is a parameter that corresponds to the probability that nodes of the graph have a degree k, C is a parameter that is determined by a normalization condition, G(1)=1, and ?, ? are parameters that is optimized through numerical calculations.

Abstract: The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. The decoding can be performed on signals whose various symbols have been mapped to multiple modulations (constellations and mappings) according to a rate control sequence. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding to generate the signal that is subsequently decoded. Either one or both of an encoder that generates the signal and a decoder that decodes the signal may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: A Reed-Solomon decoder includes a Chien search circuit to receive an error location polynomial function, performs Chien search, and finds an error location; a Forney algorithm circuit to receives an error pattern polynomial function and find an error pattern; and, a seed generator circuit to indicates a seed value corresponding to a codeword length for the input data. A Chien search is performed to obtain and outputs exponential terms related to variables for the polynomials, wherein the Chien search is performed in the same computational direction as an order for the input data.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a buffer manager which successively reads the digital data m bytes at a time from a temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the data m bytes at a time, as the m bytes are supplied from the buffer manager, and generates a PI sequence parity based on the data for one row extending in the main scan direction, and a PO parity unit which includes in operation units, each of which processes a corresponding byte of the data, as m bytes of the digital data are supplied from the buffer manager, and generates a PO sequence parity based on the data for one column extending in the sub-scan direction.

Abstract: The present invention is intended to provide multiple levels of digest streams for multimedia contents with small amount of additional storage using a multiple level digest segment information scheme. In the present invention, a multiple level digest segment information is contained in the content-based data area of the multimedia content by representing a level information of each digest segment by multiple levels in a content-based data area of a multimedia content, describing the digest level of the digest segment and the time range information of the digest segment in the digest segment information scheme, and outputting digest segments whose digest level is less than or equal to requested digest level by decoding, upon receipt of the digest level of the digest segment.

Abstract: A bookmark editor in an Internet web browser application allows a user to create symbolic links between bookmarks and bookmark folders. The bookmark editor may also detect when a bookmark already exists for a document and prompt the user to create a link rather than a new bookmark for the same document. The user may then keep a folder, subfolder, or bookmark and link to it via a symbolic link. When a bookmark is added to a folder or subfolder, the user does not need to duplicate that bookmark for a linked folder or subfolder.

Abstract: A method of synchronizing an audio and visual presentation in a multi-modal browser. A form having at least one field requiring user supplied information is provided to a multi-modal browser. Blank fields within the form are filled in by user who provides either verbal or tactile interaction, or a combination of verbal and tactile interaction. The browser moves to the next field requiring user provided input. Finally, the form exits after the user has supplied input for all required fields.

Abstract: A visual markup to voice markup transcoding system, method and machine readable storage. The basic method can include identifying at least one heading in visual markup; creating a corresponding menu item in voice markup; further creating a text block in the voice markup for text associated with the identified heading; and, linking the text block with the menu item in the voice markup. Additional headings can be identified in the visual markup; and, each of the creating, further creating and linking steps can be repeated for each identified additional heading. Notably, the visual markup can be formatted according to the hypertext markup language (HTML), and the voice markup is formatted according to the voice extensible markup language (VXML).