Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A dual gate drain extension field effect transistor assembly comprises a first FET device having a source, a gate and a drain extension region. The first FET device's gate is electrically coupled to a constant voltage source. A second FET device has a source, a drain, and a gate, and the second FET's drain is electrically to the first FET's source.

Abstract: There is provided a bias current generating apparatus capable of providing a bias current where a characteristic change is compensated, to one of an analog circuit and RF circuit where various characteristic changes occur according to a temperature, by generating bias currents having a plurality of temperature coefficients.

Abstract: A charge pump includes a first switch coupled between a first voltage source and a first node, second switch coupled between the first node and a second node, a third switch coupled between the second node and a third node, the third node is for outputting from the charge pump. A fourth switch is coupled between the output node and a fourth node, a fifth switch is coupled between the fourth node and a fifth node, and a sixth switch is coupled between the fifth node and ground. A seventh switch is coupled between ground and the first node and an eighth switch is coupled between a second voltage source and the fifth node. A first capacitor is coupled between the second node and a first voltage signal and a second capacitor is coupled between the fourth node and a second voltage signal.

Abstract: In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer gate and a capacitor to conduct an operation of boosting the power source voltage so as to be twice the power source voltage, and a connection switching terminal outputs the boosted voltage as a boost control voltage. In a charge pump circuit unit, a connection switching terminal selects the boost control voltage outputted from the charge pump circuit unit, and a logically-inverting buffer gate and a capacitor conduct an operation of boosting the inputted voltage so as to be 3×VDD. An internal voltage is generated by outputting the boosted voltage to an internal power line via a NMOS transistor.

Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit, said current sensor producing an output current related to said common mode current; said active filter comprising a first and second transistor, each having first and second main electrodes and a control electrode, and an amplifier circuit driving said transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled t

Abstract: An apparatus and method are provided for reducing noise in a capacitive sensor (200). One apparatus includes a gain stage (210) including an output, the gain stage configured to generate a first signal having a noise component and a second signal having a desired output component and the noise component, and a filtered-sampling stage (250) having an input coupled to the gain stage output, the filtered-sampling stage configured to sample the first signal, store the first signal, and subtract the first signal from the second signal to produce a desired output signal. A method includes generating a first signal having a first noise component of the gain stage (710), storing the first signal (725), generating a second signal comprising a desired output component and the first noise component (730), and subtracting the first signal from the second signal to produce a first output signal having the desired output component (750).

Abstract: The invention concerns an electronic circuit comprising a sigma-delta modulator and a power amplifier connected downstream thereof, wherein there is provided a feedback circuit (207) which is coupled between an output of the sigma-delta modulator and an input of the sigma-delta modulator and which includes an emulation of the signal path between the output of the sigma-delta modulator and the output of a power amplifier (107) connected downstream of said sigma-delta modulator.

Abstract: The invention is a power amplifier circuit for providing a signal acceptable for use in audio amplifiers or similar applications without requiring a stable power supply free from fluctuations. An alternating current power supply signal rectified to a direct current signal is processed by two voltage multipliers. A voltage divider establishes a unity gain level, and the variance from this voltage is squared by the first voltage multiplier. This squared voltage is then multiplied with a triangular wave signal to generate a modulated triangular wave signal. The modulated triangular wave signal and a signal to be amplified, typically an audio signal, are processed by an internal comparator to generate a pulse width modulated signal. This modulated signal is processed by a power transistor network and filter to provide an amplified signal to a load device.

Abstract: An amplifier includes a signal input, a first, second and third amplification path. A coupling element having a first and a second output terminal is coupled to respective input terminals of the first and second amplification paths, and is coupled with a third terminal to an input terminal of the third amplification path. In a first mode of operation the coupling element provides a signal at the first and second output terminals, wherein the signal at the second output terminal comprising a phase shift with respect to the signal at the first output terminal. In a second mode of operation, the coupling element provides a signal at the third output terminal, wherein the provided signal is received at the input terminal and reflected on the first and second output terminals.

Abstract: According to an exemplary embodiment, a multimode power amplifier configured to receive an RF input signal and provide an RF output signal in linear and saturated operating modes includes an output stage configured to receive a fixed supply voltage and to provide the RF output signal. The multimode power amplifier further includes at least one driver stage coupled to the output stage, where the at least one driver stage is configured to receive the RF input signal and an adjustable supply voltage. The adjustable supply voltage controls an RF output power of the RF output signal when the multimode power amplifier is in the saturated operating mode. The at least one driver and the output stage are each biased by a low impedance voltage in the linear and saturated operating modes. The adjustable supply voltage can be controlled by a fixed control voltage in the linear operating mode.

Abstract: The invention relates to a system and method for attenuating harmonics in output signals. In the system, an electronic circuit for reducing harmonics of an output signal from a power amplifier in a transmission circuit for a wireless communication device is provided. The circuit comprises: a printed circuit board (PCB); a power amplifier for generating an output signal; and a circuit implemented on the PCB connected to an output terminal of the power amplifier for the output signal. The circuit comprises a first filtering stage; a delay element; and a harmonic filter. The delay element is located between the harmonic filter and the output terminal and the delay element provides a timing delay in the output signal through at least one 0 ohm-rated component. Also, the harmonic filter is a low pass filter having a frequency cut-off point that attenuates first order harmonics of the output signal.

Abstract: The present disclosure relates generally to systems and methods for combining stepped drain bias control with digital predistortion for a power amplifier. In one example, the method includes receiving an input associated with a transmit power level of a transmitter in a wireless terminal and selecting a predefined drain bias setting for a power amplifier of the wireless terminal based on the input. A predefined predistortion setting for the power amplifier corresponding to the selected predefined drain bias setting is identified. A drain of the power amplifier is set to the selected predefined drain bias setting, and the identified predefined predistortion setting is applied to a signal prior to directing the signal to the power amplifier.

Abstract: A switching amplifier includes first and second output terminals that may be connected to a load. A pulse-width modulator receiving an input signal to obtain respective positive and negative values of the input signal. The modulator is connected to first and second switching circuits. The first switching circuit applies a plurality of pulses to the first output terminal that, in response to the positive samples, have a constant frequency and are pulse-width modulated, and, in response to the negative samples, have a varying frequency and a constant width. Similarly, the second switching circuit applies a plurality of pulses to the second output terminal that, in response to the negative samples, have a constant frequency and are pulse-width modulated, and, in response to the positive samples, have a varying frequency and a constant width. The varying phase of the constant width pulses disperses RF interference across a wider spectrum.

Abstract: There is provided a differential signal comparator which maintains the duty ratio of complementary input signals. The differential signal comparator includes differential amplifier circuits 1 and 2 receiving complementary input signals, a plurality of current amplifier circuits 3 to 6 for amplifying current output from the differential amplifier circuits and a current arithmetic operation circuit 7 for an arithmetic operation of an output from the plurality of current amplifier circuits 3 to 6 at the time of converting the differential signal between the complementary input signals into a voltage of CMOS level, wherein a capacitive load of an output of the differential amplifier circuit is constant independent of a level of the input signals. A voltage signal which is current-voltage converted to a complementary CMOS level signal is input into a differential comparator to obtain a single end CMOS level signal.

Abstract: Example embodiments relate to an output buffer having a differential input circuit configured to convert a differential voltage signal input through a positive input terminal and a negative input terminal into a differential current signal, and configured to output the differential current signal. The differential input circuit may include a plurality of PMOS transistors and a plurality of NMOS transistors. The output buffer may further include a slew rate matching circuit configured to compensate for a difference between components of a first parasitic capacitor formed around the plurality of PMOS transistors and components of a second parasitic capacitor formed around the plurality of NMOS transistors.

Abstract: A variable gain amplifier has a first amplifier circuit (106) having a first field-effect transistor and amplifying a signal input to a gate of the first field-effect transistor to output; a gate bias control circuit (102) controlling a gate bias of the first amplifier circuit to control a gain of the first amplifier circuit; and a variable matching circuit (103) controlling a capacitor connected to the gate of the first amplifier circuit to control the gain of the first amplifier circuit.

Abstract: A bias-controlled high power amplifier apparatus and method is provided. The apparatus includes a controller, a switching unit, and a power amplifier. The controller supplies a gate voltage of a power amplifier and after a delay for a predetermined time period, supplies a power source to a switching unit. The switching unit connects a drain terminal of the power amplifier with a Direct Current (DC) power source supply unit, receives a power source from the controller, and provides a drain voltage of the power amplifier to the drain terminal. The power amplifier receives the gate voltage and the drain voltage and amplifies a signal.

Abstract: Methods and apparatus to detect impedance at an amplifier output are described. In one example, a method of determining a relative value of an amplifier output load may include determining a current provided to the amplifier output load in response to an input signal; determining a current provided to a reference load in response to a signal based on the input signal; comparing the current provided to the amplifier output load to the current provided to the reference load; and indicating a relationship between the amplifier output load and the reference load based on the current provided to the amplifier output load and the current provided to the reference load.

Abstract: Provided herein is a power amplifier having a multiple stage power amplifier section and an output matching network section. The multiple stage power amplifier section can include multiple power amplifier stages with interstage matching circuits located therebetween. The output matching network can be configured to match the multiple stage power amplifier section at multiple different frequencies or frequency bands. The power amplifier device is capable of selective operation within one of multiple different frequencies or frequency bands.

Abstract: A radio frequency (RF) generator for applying RF power to a plasma chamber includes a DC power supply (B+). A radio frequency switch generates the RF power at a center frequency f0. A low-pass dissipative terminated network connects between the DC power supply (B+) and the switch and includes operates at a first cutoff frequency. The switch outputs a signal to an output network which improves the fidelity of the system. The output network generates an output signal fed to a high-pass subharmonic load isolation filter that passes RF power above a predetermined frequency. A low-pass harmonic load isolation filter may be inserted between the output network and the high-pass subharmonic load isolation filter, and a high-pass terminated network may connect to the output of the output network. The high-pass terminated network dissipates RF power above a predetermined frequency.

Abstract: A frequency synthesizer, especially for use with a time-base generator of a fill-level meter employing the radar principle is designed to output a first frequency signal and a second frequency signal at mutually slightly different frequencies. The synthesizer incorporates a reference oscillator operating at a reference frequency and a control oscillator regulated at a control frequency. A first frequency divider with a division factor V1 is connected in line with the reference oscillator and a second frequency divider with the division factor V2 is connected in line with the control oscillator, which frequency dividers serve to output the first frequency signal and the second frequency signal, respectively. The result is a stable frequency synthesizer with a large phase-control bandwidth and consequently an extremely short transient response time as well as broad-band phase-noise suppression. A method for operating the synthesizer is also disclosed.

Abstract: An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signal. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Abstract: The present invention is related to a delay unit, and more particularly to a delay unit with respect to delay an input signal. The delay unit comprises a ring oscillator and a counter. The ring oscillator receives an input signal and generates a clock signal. The counter connects to the ring oscillator for receiving the clock signal and generating a delay signal. The delay signal feeds back to the ring oscillator to stop the ring oscillator, and the power consumed in the delay unit can be reduced. The ring oscillator comprises a plurality of inverters and the counter comprises a plurality of flip-flops, and the delay unit can generate an accurately and/or large delay time by changing the number of the inverters and/or the flip-flops.

Abstract: An oscillator, includes: an amplifier circuit including a semiconductor element having a first constant potential as reference potential for a power supply voltage; a variable capacitance element; a piezoelectric resonator; and a capacitance circuit constituting a closed circuit with the piezoelectric resonator. The amplifier circuit and the variable capacitance element are connected in series to provide a series circuit. The capacitance circuit connects the capacitance elements in a plurality of numbers in series. A connecting midpoint of the series connection is connected to a circuit for the first constant potential. Two connecting midpoints other than the midpoint of the closed circuit is used as connecting points to connect the series circuit and the closed circuit in parallel.

Abstract: An oscillator includes a first oscillating portion that outputs a first oscillation signal having a first oscillation frequency through a first intermediate node to an output terminal, a mounting portion that includes an insulating layer and that mounts the first oscillating portion, a first line provided in the insulating layer and coupled between the first intermediate node and ground, a second line provided in the insulating layer and coupled between the first intermediate node and a power supply terminal, and a third line provided in the insulating layer and coupled between the first intermediate node and the output terminal.

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract: A method for manufacturing a piezoelectric oscillator includes the steps of: forming a first semiconductor layer above a substrate; forming a second semiconductor layer above the first semiconductor layer; forming a first opening section that exposes the substrate by removing the second semiconductor layer and the first semiconductor layer in an area for forming a support section; forming the support section in the first opening section; forming a driving section that generates flexing vibration in an oscillation section above the second semiconductor layer; patterning the second semiconductor layer to form the oscillation section having the supporting section as a base end and another end provided so as not to contact the supporting section, and a second opening section that exposes the first semiconductor layer; and removing the first semiconductor layer through a portion exposed at the second opening section by an etching method, thereby forming a cavity section at least below the oscillation section, wher

Abstract: Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.

Abstract: In some embodiments of the present invention, the buried silicon oxide technology is employed in the fabrication of fluid channels, particularly nanochannels. For example, a fluid channel can be made in a buried silicon oxide layer by etching the buried oxide layer with a method that selectively removes silicon oxide but not silicon. Thus, one dimension of the resulting fluid channel is limited by the thickness of the buried oxide layer. It is possible to manufacture a very thin buried oxide layer with great precision, thus a nanochannel can be fabricated in a controlled manner. Moreover, in addition to buried oxide, any pairs of substances with a high etch ratio with respect to each other can be used in the same way. Further provided are the fluid channels, apparatuses, devices and systems comprising the fluid channels, and uses thereof.

Abstract: A phase shifter includes a first signal path in which a first unit is disposed to advance a phase of a signal; a second signal path in which a second unit with no shunt capacitor is disposed to change the phase of the signal such that the changed phase is delayed than the advanced phase by the first unit; and a switch section configured to switch between the first signal path and said second signal path. The first unit comprises a filter, and the second unit is a transmission line.

Abstract: A full range phase shifter circuit includes a power divider, a hybrid coupler, a differential phase shifter, a power combiner and switched attenuators. The power divider, hybrid coupler, differential phase shifter and power combiner comprise lumped elements and can be integrated in semiconductor processes, decreasing the circuit size of the full range phase shifter.

Abstract: A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal.

Abstract: A layered low-pass filter includes: a first coil and a second coil that are connected in series and that are located between an input terminal and an output terminal in terms of circuit configuration; and a capacitor located between a ground and a node between the first and second coils in terms of circuit configuration. In terms circuit configuration, the first coil is located closer to the input terminal than is the second coil. Each of the first and second coils has an input and an output. The layered low-pass filter further includes: a first conducting path formed using at least one through hole and used for connecting the capacitor to the output of the first coil; and a second conducting path formed using at least one through hole and used for connecting the capacitor to the input of the second coil.

Abstract: A dual mode piezoelectric filter includes a piezoelectric material layer composed of a piezoelectric thin film of the high-cut type formed on a substrate, a first electrode and a second electrode formed on one of the major surfaces of the piezoelectric material layer with a gap provided therebetween, a third electrode formed on the other major surface of the piezoelectric material layer opposite to the first electrode, the second electrode, and the gap, and an interelectrode mass load element formed in the gap or at a position opposite to the gap on a surface of the piezoelectric material layer. The relationships (p1×h1)?(pa×ha) and (p2×h2)?(pa×ha) are satisfied, where h1 is the thickness and p1 is the density of the first electrode, h2 is the thickness and p2 is the density of the second electrode, and ha is the thickness and pa is the density of the interelectrode mass load element. A filter characteristic with a smooth passband and low losses is obtained.

Abstract: The present invention provides a central frequency adjustment device and adjustable inductor layout; wherein, the central frequency adjustment device is applied in an inductor/capacitor tank (LC tank) for adjusting the central frequency of the LC tank. The device comprises a first inductor with a first end and a second end; a second inductor with one end coupled with the second end of the first inductor; and, a first trimmable wire connected to the first inductor in parallel and to the second inductor in series, which adjusts the central frequency by cutting off the first trimmable wire.

Abstract: A circuit breaker for overcurrent protection and earth leakage protection includes a main housing, a circuit board, a zero-phase current transformer, an earth leakage detection circuit, a trip coil, a sensitivity current-switch, an action time switch, and an earth leakage test switch. The earth leakage detection circuit, the sensitivity current-switch, the action time switch, and the earth leakage test switch are mounted on the circuit board and installed in the main housing.

Abstract: An electronic trip unit for a circuit breaker is disclosed. The electronic trip unit has a processing circuit, and a real time clock circuit that is operational in the absence of current in the circuit breaker. The processing circuit is responsive to input signals representative of a current in the circuit breaker, and the real time clock circuit is in signal communication with the processing circuit. In response to an off event at the circuit breaker following a current flow condition thereat, the real time clock circuit is configured to generate time information relating to the circuit breaker being off as a result of the off event for use by the processing circuit.

Abstract: A polarized electromagnetic relay including an electromagnet assembly, a contact section insulated from the electromagnet assembly, and a force transfer member disposed between the electromagnetic assembly and the contact section. The electromagnet assembly includes an electromagnet, an armature driven by the electromagnet, and a permanent magnet carried on the armature. The armature includes first and second electrically conductive plate elements holding the permanent magnet therebetween in a direction of magnetization of the permanent magnet and disposed to orient the direction of magnetization in parallel with the center axis of the coil. The armature is arranged linearly movably in a direction parallel with the center axis in a state where a part of the first electrically conductive plate element is inserted into a space between the outer peripheral region of the iron core head portion and the distal end region of the yoke major portion.

Abstract: An electromagnetic relay is provided which enables a coating process with a coating agent even after being mounted on a printed circuit board having undergone reflow heating by preventing invasion of water while maintaining air permeability. A main body making up the electromagnetic relay includes an electrical contact portion, electromagnetic driving portion and molded resin base and is covered with the molded resin cover. One or more through holes are formed by applying laser beam from a rear side of the molded resin cover. A spot diameter of each through hole on a surface of an outside of the molded resin cover is 0.1 ?m to 10 ?m. Instead of the molded resin cover, through-holes each having a size of 0.1 ?m to 10 ?m may be formed by applying the laser beam to the molded resin base.

Abstract: The disclosure relates to an electrical installation device, e.g., a circuit-breaker, motor protecting switch, and similar, comprising a housing that is formed from shell-type housing parts, an electromagnetic trigger, a thermal trigger, a breaker mechanism with a latching point, a slide which transmits the movements of the thermal trigger and the magnetic trigger to the breaker mechanism in order to unlatch the same, and a striker that is connected to the armature of the electromagnetic trigger and acts upon a movable contact piece of a contact point in case of a short-circuit so as to open the contact point. The shell-type housing parts, the slide, and the striker are made of plastic. At least the slide is formed from radiation-crosslinked thermoplastic to which an additive has been added as a crosslinking promoter before the radiation process.

Abstract: The invention refers to a double acting electromagnetic actor, in particular for hydraulic and pneumatic applications, with a coil, an armature arranged in the coil with at least two permanent magnets magnetised in axial direction, and a central disc between the permanent magnets, wherein between the armature and the coil in axial direction stronger or easily magnetisable areas are formed, and between these a weakly or non-magnetisable area is formed. The invention is characterised in that the armature is arranged, in particular supported, in a pole tube provided in the coil.

Abstract: A magnetic circuit is provided which includes: a bottom yoke; a center pole disposed at the center of the front of the bottom yoke; a main magnet having a ring shape and disposed at the front of the bottom yoke; a top plate having a ring shape and disposed at the front of the main magnet; a repulsion magnet disposed at the rear of the bottom yoke; and a yoke cover disposed to cover the rear and side of the repulsion magnet, wherein the yoke cover has an outer diameter dimensioned equal to or smaller than the outer diameter of the main magnet, whereby the magnetic flux density at the air gap g can be enhanced. Thus, the magnetic circuit described above achieves an excellent magnetic efficiency.

Abstract: High-current, compact, flexible conductors containing high temperature superconducting (HTS) tapes and methods for making the same are described. The HTS tapes are arranged into a stack, a plurality of stacks are arranged to form a superstructure, and the superstructure is twisted about the cable axis to obtain a HTS cable. The HTS cables of the invention can be utilized in numerous applications such as cables employed to generate magnetic fields for degaussing and high current electric power transmission or distribution applications.

Abstract: One or more pairs of magnet assemblages (14 and 16) are provided with magnetized segments (21-30) arranged in a Halbach-like array. The magnet assemblages (14 and 16) define a gap (18) through which magnetic data storage media (12) pass in a direction (20) across the segments (21-30). The magnetized sides (36) of the magnet assemblages (14 and 16) face each other thereby creating strong magnetic fields which degauss the magnetic data storage media (12) passing through the gap (18).

Abstract: An inductive element formed of planar windings in different conductive levels, the windings being formed in a number of levels smaller by one unit than the number of windings, two of the windings being interdigited in a same level.

Abstract: A transformer includes a primary winding coil, a plurality of conductive pieces, a bobbin and a magnetic core assembly. The bobbin includes a plurality of hollow partition plates and a wall portion. The wall portion is arranged between every two adjacent hollow partition plates to form a channel and a winding section for being wound the primary winding coil thereon. The hollow partition plates have respective receiving portions for accommodating the conductive pieces therein. The magnetic core assembly is partially embedded within the channel.

Abstract: Disclosed herein are various embodiments of coil transducers and galvanic isolators configured to provide high voltage isolation and high voltage breakdown performance characteristics in small packages. A coil transducer is provided across which data or power signals may be transmitted and received by primary and secondary coils disposed on opposing sides thereof without high voltage breakdowns occurring therebetween. At least portions of the coil transducer are formed of an electrically insulating, non-metallic, non-semiconductor, low dielectric loss material. The coil transducer may be formed in a small package using, by way of example, printed circuit board, CMOS-compatible and other fabrication and packaging processes.

Abstract: An inverter power module for use in an electric/electronic device includes a driving circuit board, a power transformer mounted on the driving circuit board, an inverter transformer mounted on the driving circuit board, and a blocking unit to block a magnetic flux that is generated from the inverter transformer from being emitted to the outside. With this, the magnetic flux that is generated from the inverter transformer is blocked from being emitted to the outside, thereby allowing an EMI noise, a heating problem, a noise of the system circuit, etc. to be minimized.

Abstract: A protective sleeve for a fuse connection includes an insulative sleeve body having first and second body portions adapted to provide a water-resistant seal at opposite ends of the fuse connection and a substantially transparent window disposed between the first and second body portions. The window permits a visual indicator of the fuse of the fuse connection to be visible therethrough.