Abstract: A method for testing an integrated circuit device includes subjecting the integrated circuit device to an applied magnetic field during the application of one or more test signals, the applied magnetic field inducing magnetostriction effects in one or more materials comprising the integrated circuit device; and determining the existence of any defects within the integrated circuit device attributable to the applied magnetic field.

Abstract: An electronics testing assembly includes a housing, a tester assembly, and an activation assembly. The housing is sized to retain the activation assembly and at least one electronics testing device. The tester enclosure is configured to house a plurality of tester connector interfaces that are mounted to a first connector plate. The activation assembly includes an actuator assembly and a plurality of activation connector interfaces mounted to a second connector plate. The actuator assembly is configured to move the second connector plate between a lowered vertical position and a raised vertical position within the housing while maintaining a fixed orientation of the tester enclosure relative to the housing. In the lowered vertical position the activation connector interfaces are spaced apart from the tester connector interfaces, and in the raised vertical position the activation connector interfaces are engaged with the tester connector interfaces to create an electrical connection.

Abstract: Non-invasive THz spectroscopic apparatus and methods are provided for detecting and/or identifying constituents such as variations in a structural entity where chemical or biological entities can reside. Position dependent scattering of THz radiation is employed to image voids and defects in the internal structure of samples, enabling the determination of contamination, spoilage or readiness of products such as wine in sealed containers.

Abstract: A detector circuit having an integration capacitor coupled to an amplifier via a switch matrix and a comparator coupled to the amplifier, the integration capacitor operable in two or more phases, the switch matrix is configured to phase switch the integration capacitor, the comparator triggers the phase switch when the output voltage of the amplifier passes the threshold voltage of the comparator.

Abstract: The present invention is a detection device, system and method for detecting an external electromagnetic event such as lightning or a high intensity radiated field. In an exemplary embodiment, the detection device includes a free space capacitive sensor and a protected amplifier circuit coupled with the free space capacitive sensor. The free space capacitive sensor and the protected amplifier circuit are configured to respond to a voltage waveform produced by an external electromagnetic event. The free space capacitive sensor serves as a single input capable of detecting the external electromagnetic event and the coupling of the free space capacitive sensor to the protected amplifier circuit allows subsystems in communication with the sensor and amplifier circuit to generate a coordinated response to the detected external electromagnetic event.

Abstract: A foreign object detection sensor applied to an electric sliding door apparatus is provided. The sensor includes a contact detecting section, a change detecting section, and a determination section. The contact detection section has a pressure sensitive portion which is capable of elastically changing in form through contact with a foreign object. The contact detecting section outputs a contact detection signal. The change detecting section measures the time required for the oscillation signal for a predetermined number of cycles to be outputted within a measurement period, which is set shorter than the response time it takes from when the object makes contact with the pressure sensitive portion to when the contact detecting section outputs the contact detection signal in the case where the movable body is in the closing operation at a predetermined maximum moving speed.

Abstract: An electrical resistance measurement method and a component inspection process to which the electrical resistance measurement method is applied. In the first step, a measuring object, for example, one pair of zinc-plated steel plates on which surfaces films are formed is prepared. Then, an elastic electroconductive material is sandwiched by the pair of zinc-plated steel plates and a spacer which regulates a space between the zinc-plated steel plates. Next, in the second step, an electrical resistance is measured in a state in which the pair zinc-plated steel plates sandwich the elastic electroconductive material.

Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.

Abstract: An apparatus for testing electric components supported on a test plate for transport along a travel path through a test station includes an electrical contactor at the station for contacting the plate surface and at least one electronic component transported to the station by the plate for testing. An adjustable force applicator supplies contact pressure to the contactor to apply a substantially constant force over a large working travel range. The applicator can include an air cylinder having a force applying pin applying force to a position located between a working point of the contactor and the pivot point such that the applied force variation is reduced as a result of a lever reduction ratio between the working point and the pin position.

Abstract: A method of manufacturing a substrate for a probe card assembly comprises preparing an interconnection layer, preparing a resin layer and preparing a base layer. The method comprises attaching the resin layer to the interconnection layer by a first thermal process at a first temperature. The method comprises attaching the resin layer attached to the interconnection layer to the base layer by a second thermal process at a second temperature higher than the first temperature.

Abstract: A method and an apparatus are provided which make it possible, when testing chips arranged on a wafer, to be able to test optionally both additional components arranged on horizontal boundary lines and on vertical boundary lines. The additional components arranged on horizontal boundary lines are tested in a first position of the wafer. For testing the additional components arranged on vertical boundary lines, the wafer is rotated about its vertical axis through 90° relative to the first position into a second position. The apparatus comprises a housing and, in the housing, at least one test probe for making contact with an electronic component, a chuck for moving the wafer and a rotatably mounted additional plate operatively connected to the chuck.

Abstract: A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract: A probe is provided for testing the electrical characteristics of a device. The probe includes a housing, a plurality of cables, a circuit board located within the housing, and a field-replaceable probe tip. The probe tip includes an array of contacts. Each of the plurality of cables is connected to a corresponding contact. The probe includes a retractable shroud that retracts as the probe is connected to the device. The contacts have bifurcated tips.

Abstract: A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.

Abstract: Provided is a cooling apparatus for a semiconductor device. The apparatus includes: a main body capable of moving vertically to face the semiconductor device that is mounted on a test unit in order to perform an electrical test; a heat exchange unit combined with the main body and contacting a top surface of the semiconductor device to absorb heat generated by the semiconductor device; and a lift unit combined with the main body and for moving the main body vertically. The heat exchange unit is combined with the main body to be capable of rotating according to an angle by which the semiconductor device is tilted when the heat exchange unit contacts the semiconductor device.

Abstract: A contact probe and a socket for testing semiconductor chips are provided with a simple structure, so that they can be easily manufactured, and can reduce a signal path not only to improve test reliability but also remarkably reduce the dimensions of test equipment. The contact probe comprises: a nonconductive elastic plate having main through-holes corresponding to contact terminals of a test target; plungers coupled on upper sides of the main through-holes, each having a plunger head that is elastically supported by the elastic plate and a plunger body that extends downwards from the center of the plunger head; and contact pins coupled on lower sides of the main through-holes, each having a receiving hole contacting the plunger body of each plunger at a center thereof.

Abstract: There is provided a device identifying method for identifying an electronic device including therein an actual operation circuit and a test circuit having a plurality of test elements provided therein, where the actual operation circuit operates during an actual operation of the electronic device and the test circuit operates during a test of the electronic device.

Abstract: There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range. Accordingly, the validity of the signal outputted from the device can be measured without any expensive external measuring device. Also, when the test must be done before the packaging stage, the test can be simply performed, thereby reducing the test cost greatly.

Abstract: The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a self-centering nest for testing of microprocessor chip modules. The self-centering nest includes two slideable jaws disposed on a base diagonally opposite each other. Each jaw includes a jaw pin that is receptive in a carrier, such that when the jaw pins are received in the carrier, the jaws are in an open position. The self-centering nest includes a transfer mechanism for urging a microprocessor chip module from the carrier into the self-centering nest. The self-centering nest includes a plurality of springs, each spring having a first end connected to the first slideable jaw and a second end connected to the second slideable jaw. The springs cause the jaws to move toward each other capturing and centering the microprocessor chip module when the jaws are pulled away from the carrier releasing the jaw pins.

Abstract: A method for providing transistor threshold voltage compensation in an FPGA integrated circuit with a plurality of programmable circuit blocks includes measuring the effective transistor threshold voltage values of each programmable circuit block and adjusting the effective transistor threshold voltage values of each programmable circuit block to compensate for the difference between the measured effective transistor threshold voltage value and the target effective transistor threshold voltage value.

Abstract: An interface circuit includes a driver circuit (12) made up of a combination of a plurality of transistors, a calibration circuit (14) for performing selection of on and off of one or more of the plurality of transistors for adjusting on-resistance thereof, and a terminating resistor (13) that is connected to an output side of the driver circuit (12). One or more of the transistors are turned on based on an output of the calibration circuit (14), so that a combination resistance value of the on-resistance and the terminating resistor matches characteristic impedance of the transmission line. The driver circuit (12), the calibration circuit (14) and the terminating resistor (13) are formed on the same semiconductor integrated circuit SK, and the calibration circuit (14) detects process variation and temperature variation of the transistor and the resistor formed on the semiconductor integrated circuit (SK).

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurably routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Abstract: This invention efficiently suppresses the power noise of an LSI. A semiconductor device includes first and second interconnection layers. The first interconnection layer has a source voltage supply line of a first potential positioned to extend along logic cells in a first direction. The second interconnection layer lies on an upper layer than the first interconnection layer and has plural source voltage supply lines of a second potential arranged adjacent to each other to form a group and positioned to extend in a second direction which is different from the first direction of interconnection. An interconnection line of the second potential is positioned on an upper layer than the first interconnection layer and interconnects at least two of the plurality of source voltage supply lines of the second potential.

Abstract: An expandable decoding circuit includes a latch unit, a latch result selecting unit, and at least one decoding circuit. The latch unit latches raw data and outputs the latch values and the latch inverse-values of the raw data. The latch result selecting unit composes the latch values and the latch inverse-values according to the target decoding value of the decoding unit to generate a pre-decoding value. The latch result selecting unit outputs the pre-decoding value to the corresponding decoding unit. The decoding circuit determines whether a decoding signal is outputted or not according to the pre-decoding value. Thereby, when a new function needs to be added to the deciding circuit, the present invention does not change the original decoding circuit and implements the decoding unit for the new function.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: A hysteresis circuit applied to a comparator and an amplifier circuit thereof are provided. A hysteresis circuit is disposed on a positive feedback path of the comparator, such that the comparator resists noise interferences, and the hysteresis circuit has a feature of not affecting the feedback voltage signal, thereby making the hysteresis range of the comparator be more precise.

Abstract: A precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode, it precharges the total load capacitor. When the sample-and-hold circuit is in the hold mode, the influence to the sampled signal is further reduced due to the precharging. The requirements of swing rate, output voltage swing, gain-bandwidth product for the opamps can therefore be reduced, hence being applicable to the realization of the design of advanced fabrication technologies of low supply voltages.

Abstract: An ignition coil includes a coil portion and an igniter. The coil portion has a primary coil, a secondary coil, and a coil case. The primary coil and the secondary coil are disposed in the coil case. The igniter is disposed on one end side of the coil portion. The igniter includes a metallic frame connected to a voltage source at a constant potential, and a semiconductor integrated chip disposed on the metallic frame. The semiconductor integrated chip has a control circuit for controlling a switching element. The control circuit is formed by a dielectric isolation method. A surface of the semiconductor integrated chip on a silicon substrate-side is opposed to the metallic frame.

Abstract: The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a predetermined frequency resolution. A spur generated from the voltage controller oscillator according to the variation of k is measured while the value k is varied. When the spur takes place at a certain value of k where a frequency is lower than a predetermined reference frequency, the fractional division ratio is reset as k/(q+1) or k/(q?1) for the certain value of k. The reset fractional division ratio is provided to the divider.

Abstract: A CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes.

Abstract: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals. A detection signal is generated every time the master triangular wave signal reaches predetermined threshold levels. In response to the detection signal, a capacitor associated with one slave triangular signal is promptly discharged to bring the slave triangular signal to the lower limit voltage, whereby the respective slave triangular wave signals are synchronized to be offset in phase relative to the master triangular wave signal by respective predetermined phase angles.

Abstract: A triangular waveform generator includes a square waveform clock circuit and an active integrator. The active integrator receives input from the square waveform clock circuit and generates a triangular waveform output. An active feedback network is operatively added to the active integrator to reduce the audio band noise content in the triangular waveform output. The feedback network acts as a DC balance without significant sacrifice in the linearity of the triangular waveform output.

Abstract: A phase locked loop (PLL) with phase rotation spreading includes a phase detector, a charge pump, a filter, a voltage controlled oscillator (VCO) and a selector. The phase detector receives a reference clock signal and a feedback clock signal to thereby produce an error signal. The charge pump converts the error signal into a current signal. The filter converts the current signal into a voltage signal. The VCO produces N clock signals with a same frequency in accordance with the voltage signal, where the N clock signals have phases ?0 to ?N?1 respectively, and ?j indicates a lead of over ?j+1, for j=0, 1, . . . , N?2. The selector selects one from the N clock signals in accordance with a predetermined sequence to thereby produce a target clock signal, and finely adjusts a frequency of the target clock signal for a spreading operation.

Abstract: A phase locked circuit includes a locked loop circuit having a phase comparator, a voltage controlled oscillator, and a variable frequency divider which divides a clock signal fvco output from the voltage controlled oscillator by n and outputs it. Additionally, the phase locked circuit includes a band pass filter part which is coupled to an output side of the voltage controlled oscillator via a switching part. A frequency division ratio setting signal to be input into the variable frequency divider is input as a switching signal into the switching part so as to switch a frequency of the clock signal fvco output from the voltage controlled oscillator. As synchronizing with switching of the frequency, the switching part switches a plurality of band pass filters provided to the band pass filter part and couples to the voltage controlled oscillator.

Abstract: The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus for adjusting a lockout time in a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock and generates adjusted and encoded vectors, both indicating a first time period. A select vector is employed to select a delayed version of the reference clock that lags the reference clock by a second time period, which is slightly less than a number of reference clock cycles. The select vector is reduced in value to generate the adjusted vector. The receivers are coupled to the delay-locked loop. Each of the one or more receivers receives the encoded vector and a corresponding strobe, and locks out reception of the corresponding strobe for the first time period following transition of the corresponding strobe. The encoded vector is employed to determine the first time period by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate the lockout time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

Abstract: A low-speed general-purpose inspection apparatus is used to automatically adjust a variable delay circuit and compensate for a delay variation in order to enable an inspection and to achieve a reduction in cost and an improvement in an inspection quality.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their floating body is set to a potential by means of an appropriate connection, in order to locally reduce their contribution to the overall phase noise of said circuit. It also provides a reduced phase noise master-slave circuit. This circuit includes floating body SOI type transistors, characterised in that the potential of said floating body of the transistors that (60, 61) contribute to said phase noise is set by means of an appropriate connection (64, 65).

Abstract: A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal.

Abstract: A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Abstract: A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.

Abstract: A mixer using a small signal differential model includes a load circuit, a switch quad, and a transconductor. The switch quad further including a first current path and a second current path is coupled to the load circuit. The connecting node of the switch quad and the load circuit is a differential-output terminal. The transconductor further includes a first resistor, a first operational amplifier, a second operational amplifier, a first current mirror, and a second current mirror. The resistor is coupled between two first input terminals of the first operational amplifier and the second operational amplifier. A current control terminal of the first current mirror is coupled to the first input terminal of the first operational amplifier, and a current mirroring terminal of the first current mirror is coupled to the first current path.

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

Abstract: A driving circuit for an emitter-switching configuration of transistors having first and second control terminals connected to the driving circuit, forms a controlled emitter-switching device having in turn respective collector, source and gate terminals. The driving circuit comprises a driving block coupled between the collector terminal and the source terminal of the controlled emitter-switching device and connected to the first control terminal of the emitter-switching configuration.