Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A communication network comprises a communication bus and at least two line cards. Each of the line cards are coupled to the communication bus The line cards comprise a processor and a configuration memory coupled to the processor. The communication occurring on the communication bus is predetermined, but can be reconfigured during real time operation by events or by the addition or subtraction of line cards. The configuration memory comprising an array of configuration tables, each configuration table storing a listing of processes to run and data to be transmitted or received by the process. A current configuration table is selected from the array of configuration tables upon the occurrence of a predefined event.

Abstract: A small-sized and low-cost transmission apparatus and a transmission method (having a high responsivity) capable of transmitting an interrupt signal with a small number of input/output terminals (without a dedicated line for interrupt signals) are provided. A first transmission apparatus of the present invention comprises a central processing unit for carrying out an interrupt process in response to an interrupt signal; an input/output section having at least one data line for transmitting data signals between a second transmission apparatus and the first transmission apparatus and for transmitting an interrupt signal from the second transmission apparatus to the first transmission apparatus; and an interrupt signal detecting section for detecting an interrupt signal from among signals transmitted from the second transmission apparatus via the data line.

Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

Abstract: Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

Abstract: A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element having a second bus, and a common bus for connecting the first bus and the second bus. A bus switch positioned between the first element and the second element for disconnecting at least one of the first bus and the second bus from the common bus in response to a control signal from the bus switch controller for reducing digital noise of the common bus.

Abstract: A system couples fieldbus data from a fieldbus line to a network line. The system includes a data format converter that converts the data to USB data. A coupler that includes a first insulating barrier is coupled in cascade with the converter. A host receives the USB data. The host has a data server interface and a network connection. The data server interface presents the data to the network line. A regulator couples power between the host and the fieldbus line with the regulator including a second insulating barrier. Data and power are isolatingly coupled between the fieldbus line and the network line.

Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.

Abstract: An embodiment of the present invention enables the virtualizing of virtual memory in a virtual machine environment within a virtual machine monitor (VMM). Memory required for direct memory access (DMA) for device drivers, for example, is pinned by the VMM and prevented from being swapped out. The VMM may dynamically allocated memory resources to various virtual machines running in the platform. Other embodiments may be described and claimed.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged tracks eligible for removal from the cache that were destaged before the storage device is verified in response to verifying that the storage device is successfully completing the writing of data.

Abstract: An access control method receives an access command, and permitting access to a cache segment accessed by the access command if no access range overlap occurs, even when a contention exists between a cache segment and an arbitrary cache segment that is already being accessed. The cache memory is segmented into the cache segments.

Abstract: Provided are a method, system, and program for migrating data between storage volumes. A source map is provided indicating blocks of data striped across a first plurality of storage units and a destination map is provided indicating blocks of data striped across a second plurality of storage units, wherein data is migrated from stripes indicated in the source map to corresponding stripes indicated in the destination map. In response to determining that the source stripe and the destination stripe occupy a same physical location on the storage units, the data from a source stripe is written to a copy area and writing the data from the copy area to a corresponding destination stripe.

Abstract: A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and high-speed operation is enabled. The mirror management table is created with allocating the mirror area of the cache memory of the other controller, and acquisition of a mirror page of the cache memory of the other controller is executed referring to the mirror management table without an exchange of mirror page acquisition messages between the controllers.

Abstract: A method for concurrent garbage collection and mutator execution in a computer system includes scanning a first cache line for a non-local bit. The non-local bit is associated with a root object. A done bit associated with the first cache line is set. A second cache line to find a first object that is referenced by the root object is located. A mark bit and the done bit associated with the second cache line are set. The first and second cache lines are scanned for unset done bits. If an unset done bit is detected in either the first or the second cache line, then the cache line associated with the unset done bit is rescanned to determine whether there are any modified object references.

Abstract: A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, data gathering, and validation. In the normal mode, the instruction merely performs the function specified in the software runtime environment. An instruction in unexecuted mode, upon the next execution, is placed in data gathering mode. When an instruction in the data gathering mode is encountered, the mechanism of the present invention collects data to discover potential fixed storage access patterns. When an instruction is in validation mode, the mechanism of the present invention validates the presumed fixed storage access patterns.

Abstract: Techniques are provided for performing transaction-aware caching of metadata in an electronic file system. A mechanism is described for providing transaction-aware caching that uses a cache hierarchy, where the cache hierarchy includes uncommitted caches associated with sessions in an application and a committed cache that is shared among the sessions in that application. Techniques are described for caching document metadata, access control metadata and folder path metadata. Also described is a technique for using negative cache entries to avoid unnecessary communications with a server when applications repeatedly request non-existent data.

Abstract: A technique for synchronizing data caches. Data is maintained in the data caches as records. The records are associated with buckets which represent collections of one or more records. The buckets are collectively maintained in a synchronization set which represents a state of a data cache. A local entity synchronizes its data cache with a remote entity by sending its synchronization set to the remote entity in a synchronization request message. The remote entity compares information contained in the local entity's synchronization set with its own to determine if the two are consistent. If not, the remote entity notes inconsistencies in a response message that is then forwarded to the local entity. The local entity processes the response message including using it to update its data cache to be consistent with the remote entity's data cache.

Abstract: A shared memory access function providing unit of each of a plurality of host computers of a network device receives an access shared memory request from an application and issues the access shared memory request to an FC switch. An access shared memory request identifying unit of the FC switch determines whether the request from the host computer is an access shared memory request, and if the request is an access shared memory request, a shared memory control unit controls the access to a shared data memory unit based on the access shared memory request.

Abstract: One embodiment of the present invention provides a system that facilitates concurrent non-transactional operations in a transactional memory system. During operation, the system receives a load instruction related to a local transaction. Next, the system determines if an entry for the memory location requested by the load instruction already exists in the transaction buffer. If not, the system allocates an entry for the memory location in the transaction buffer, reads data for the load instruction from the cache, and stores the data in the transaction buffer. Finally, the system returns the data to the processor to complete the load instruction. In this way, if a remote non-transactional store instruction is received during the transaction, the remote non-transactional store proceeds and does not cause the local transaction to abort.

Abstract: Bus address, function and system information in relation to bus requests are maintained in a centralized location (702). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations needing access to the centralized data are simultaneously connected to the data through the use of the pointer control (610), rather than requiring the data to be sequentially transmitted to the bus transaction operations as required.

Abstract: A state engine system is disclosed. The system includes: a CPU and a memory operatively connected to the CPU, the memory including a program adapted to be executed by the CPU and the CPU and memory cooperatively adapted for managing a plurality of objects stored in a database, whose behavior can be modeled by means of a state diagram reacting on external events which occur in a non-deterministic order. The system additionally includes code segment embodied on a computer-readable medium configured and adapted for creating, storing and maintaining state diagram templates in a database. The database includes all states available for the object, the possible state transitions, the events which cause state transitions, and the actions which occur upon state transitions. There is at least one event causing each state transition, and the actions which occur upon a state transition are dependent upon the event that caused the transition.

Abstract: Each storage unit is provided with a table for storing a corresponding unit ID and count value. The controller receives a formatting instruction specifying a first unit ID, and updates the count value on a table corresponding to the first unit ID. The controller receives a write command specifying a second unit ID, acquires a count value corresponding to the second unit ID from the table, and attaches the count value to the data, and writes the data to the storage unit. When a read command specifying the second unit ID is received, the controller reads the data from the storage unit, acquires the count value corresponding to the second unit ID from the table, compares this count value and the count value attached to the read data, sends the read data to the transmission source of the command if these values match, and does not send the data to the transmission source of the command if these values do not match.

Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

Abstract: A system and method for synchronizing remote copies within a multiple storage network apparatus, incorporates the steps of receiving a plurality of timestamps, comparing the timestamps with a plurality of timestamps stored in a remote copy table, updating a synchronize time value stored by a synchronized time parameter, and receiving a synchronized time stamp, wherein the value associated with the received timestamp is ulterior to the value of the synchronized time stored by the synchronized time parameter. Further, a system and method for synchronizing secondary storage subsystems, incorporates the steps of collecting a plurality of synchronous timestamps from a plurality of secondary storage subsystems, comparing the plurality of collected synchronous timestamps with a synchronize time parameter, updating a remote copy time table, issuing a remote copy queue request, receiving status information about a secondary storage subsystem starting host, and synchronizing the secondary storage subsystem.

Abstract: A storage system secures system redundancy through a simple configuration. A primary storage control device and first secondary storage control device are connected by a synchronous method, and the primary storage control device and a second secondary storage control device are connected by an asynchronous method. The primary storage control device sets control numbers for update data, and saves journal data. The primary storage control device transmits the update data to the first secondary storage control device. The first secondary storage control device writes update data to a first secondary volume, and uses a plurality of bitmap tables to manage differences. If the primary storage control device stops operation, the first secondary storage control device becomes the new primary storage control device. Differential copying is performed from the first secondary storage control device to the second secondary storage control device.

Abstract: A backup method for a computer system that affords fast verification of source data written to backup media includes reading a portion of the source data from a source storage volume and generating a hash of the source data. The source data is written to the backup media as backup data, and the hash generated from the source data is written to the backup media and associated with the backup data corresponding to the source data from which the hash was generated. Verification of the backup data can be subsequently performed by reading the backup data from the backup media, generating a hash from the backup data read, and comparing that hash with the hash originally stored on the backup media. This enables the backup data to be verified as corresponding to the original source data without the necessity of rereading the source data from the source volume, and enables faster, more accurate off line verification subsequent to the backup process.

Abstract: A technique for managing data within a data storage system involves performing data storage operations on behalf of a set of hosts (i.e., one or more hosts) using a volatile-memory storage cache and a set of magnetic disk drives while the data storage system is being powered by a primary power source (e.g., a main power feed). The technique further involves receiving a power failure signal (e.g., from a sensor) indicating that the data storage system is now being powered by a backup power source rather than by the primary power source (e.g., due to a loss of the main power feed, due to a failure of a power converter, etc.), and moving data from the volatile-memory storage cache of the data storage system to a flash-based memory vault of the data storage system in response to the power failure signal.

Abstract: Under a hetero-environment in which different sorts of disk-systems are mixed with each other, a data guaranteeing operation can be carried out. When a cache controller of a local disk system receives a data writing request from a host computer, the cache controller stores data into a local disk provided in a disk device group. The data received from the host computer is also transmitted to a remote disk system and is stored in a remote disk. The data stored in the remote disk is immediately read, and the data written in the remote disk is compared with the data written in the local disk. As a result, since a data guarantee operation on the remote side is processed by the local disk system instead of the remote disk system, a data guaranteeing operation when a remote copying operation is performed can be carried out even in the storage system under a hetero-environment.

Abstract: A method, system, computer system, and computer-readable medium for maintaining up-to-date, consistent copies of primary data without the need to replicate modified data when the data were modified as a result of an operation that is not an application-driven write operation captured during replication. Selected storage management operations are performed on the primary and secondary data stores at points in time when the data are the same to ensure that the data stored within the data stores remain consistent. These selected storage management operations include operations that produce modified data stored in the primary data store, where a portion of the modified data are not replicated to a secondary node. Other types of storage management operations are selected to be performed on both the primary and secondary data stores, where the operations do not directly change data in the primary data store, but may affect data stored in the primary data store.

Abstract: A system, device, and method for managing file security attributes in a computer file storage system generates a set of Windows file security attributes from a set of UNIX file security attributes. The set of Windows file security attributes includes a UNIX-specific SID for a UNIX name that could not be translated into a Windows name. The set of Windows file security attributes also includes a set of Windows file permissions derived from a set of UNIX file permissions.

Abstract: A method for migrating data between heterogeneous data storage devices within a storage area network is disclosed. A first virtualizer presents stored data as a first virtual disk, and then communicates a managed disk representation of the first virtual disk to a second virtualizer. After receiving the managed disk representation, the second virtualizer virtualizes the stored data from the managed disk representation as a second virtual disk. At such point, the stored data can be progressively migrated from the first virtualizer to the second virtualizer.

Abstract: Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time.

Abstract: A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.

Abstract: A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.

Abstract: A method and system for computing disk space used by a directory and its descendants that may proceed while input and output are occurring that involve the directory and any of its descendants. A calculation of the total amount of disk space consumed by a set of objects is commenced. While performing the calculation, changes to the objects are monitored. If a change to one or more of the objects affects the disk space consumed by the objects, the calculation is changed so that the total reflects the change to the one or more objects.

Abstract: A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.

Abstract: A database system providing methodology for extended memory support is described. In one embodiment, for example, a method is described for extended memory support in a database system having a primary cache, the method comprises steps of: creating a secondary cache in memory available to the database system; mapping a virtual address range to at least a portion of the secondary cache; when the primary cache is full, replacing pages from the primary cache using the secondary cache; in response to a request for a particular page, searching for the particular page in the secondary cache if the particular page is not found in the primary cache; if the particular page is found in the secondary cache, determining a virtual address in the secondary cache where the particular page resides based on the mapping; and swapping the particular page found in the secondary cache with a page in the primary cache, so as to replace a page in the primary cache with the particular page from the secondary cache.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Abstract: The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch.

Abstract: A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution.

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract: A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.

Abstract: A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

Abstract: The present invention relates to an apparatus and a method for updating firmware of an embedded controller (EC) constituted in portable machinery. Embodiments of the present invention can set identification information for maintaining a system power-on state before performing operations of updating the firmware of the embedded controller. In the ROM area of the embedded controller, a new firmware file is updated and recorded. Then, the new firmware file can be updated and recorded in the RAM area of the embedded controller after system re-start or while maintaining the system power and without system re-start responsive to the identification information.

Abstract: The present invention relates to a method of realizing automatic executing and starting host computer by using semiconductor storage device. By judging the characteristics of the operating system of the host computer, the method determines the type of the operating system of the host computer or the status of the host computer, determines the time condition of invoking the automatic executing function or starting host computer function, and triggering the invoking of relevant functions according to determined time or conditions to realize, without any assistance of users, that semiconductor storage device leads the operating system of the host computer to finish the staring host computer function and to finish the automatic executing function by triggering the automatic executing means of the host computer when the host computer has been starting up and prepares for automatic execution.