Patents Issued in September 25, 2008
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Publication number: 20080231269Abstract: A real-time system changes a combination of coil elements and channel assignations for each echo by using a pulse sequence, and collects data without performing phase encoding. A host system then calculates a correlation value of data reconstructed for each channel and reference data. When the correlation value is smaller than a predetermined threshold value, the host system judges the coil element combination to be abnormal. The host system makes a level correction on the collected data and creates an alternative solution for the abnormal coil element combination, including a reduction of a number of channels.Type: ApplicationFiled: March 14, 2008Publication date: September 25, 2008Inventor: Masashi Ookawa
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Publication number: 20080231270Abstract: In a method for adjustment of a B1 field in a magnetic resonance apparatus, the position of the measurement subject relative to a coordinate system is determined from a plurality of measurement subjects with a morphological magnetic resonance measurement. Three-dimensionally associable measurement subject data are determined from the measurement subject. Respective tissue types of the measurement subject are determined using the three-dimensional measurement subject data and a segmentation of the measurement subject into regions is effected using the tissue types. Known dielectric properties are respectively associated with the tissue types. The segmentation and the association for all positions of the measurement subject are recorded in respective entries of a database, such that the database contains all entries of the measurement subjects.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Inventors: Joerg Ulrich Fontius, Franz Schmitt, Karsten Wicklow
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Publication number: 20080231271Abstract: An MRI apparatus includes an imaging signal acquisition unit, a motion signal acquisition unit, a motion amount determination unit, a motion correction unit and an image reconstruction unit. The imaging signal acquisition unit acquires MR signals as imaging signals. The motion signal acquisition unit repetitively acquires MR signals having PE amount less than that of the imaging signals as motion signals. The motion amount determination unit obtains a motion amount using the motion signals. The motion correction unit performs correction processing of the imaging signals in accordance with the motion amount. The image reconstruction unit reconstructs an image using the imaging signals after the correction processing.Type: ApplicationFiled: March 14, 2008Publication date: September 25, 2008Applicants: KABUSHIKI KAISHA TOSHIBA,, TOSHIBA MEDICAL SYSTEMS CORPORATIONS,Inventors: Masao Yui, Yoshimori Kassai, Shigehide Kuhara
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Publication number: 20080231272Abstract: Provided is a magnetic resonance imager capable of efficiently suppressing artifacts in radial scanning that is short of the number of echoes. Part of unmeasured echoes is measured as a reference echo. An estimation coefficient is calculated using echoes adjoining the reference echo, and used to estimate the unmeasured echoes.Type: ApplicationFiled: December 24, 2004Publication date: September 25, 2008Applicant: HITACHI MEDICAL CORPORATIONInventors: Yo Taniguchi, Shinji Kurokawa, Hisaaki Ochi
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Publication number: 20080231273Abstract: A magnetic resonance imaging apparatus which executes a scan for allowing an RF coil unit to transmit RF pulses to an imaging area of a subject in a static magnetic filed space and allowing the RF coil unit to acquire magnetic resonance signals generated in the imaging area, includes: a scan section which executes, as the scan, each of an actual scan for acquiring the magnetic resonance signals as actual scan data and a reference scan for acquiring the magnetic resonance signals as reference scan data; an image reconstruction unit which reconstructs an actual scan image about the imaging area, based on the actual scan data and reconstructs a reference scan image about the imaging area, based on the reference scan data; a transmission sensitivity distribution calculating unit which calculates a transmission sensitivity distribution at the transmission of the RF pulses by the RF coil unit in the imaging area, based on the reference scan image and the actual scan image; and an image correcting unit which correctType: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Inventor: Hiroyuki Kabasawa
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Publication number: 20080231274Abstract: In a method for controlling a magnetic resonance system having a radio-frequency antenna structure and a number of individually controllable transmission channels, respective parallel radio-frequency signals are emitted via the transmission channels for generation of a desired radio-frequency field distribution in at least one specific volume region within an examination volume of the magnetic resonance system. A digital signal is generated for each of the transmission channels and is modulated on a carrier frequency. The radio-frequency signal so generated is transmitted via a radio-frequency signal path to the radio-frequency antenna structure and is amplified therein in a radio-frequency power amplifier.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Inventors: Joerg Ulrich Fontius, Marian Lattka, Juergen Nistler, Franz Schmitt
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Publication number: 20080231275Abstract: In a method and an apparatus for automatic determination of objects that attenuate high energy/penetrating radiation by magnetic resonance, the magnetic resonance apparatus scans and prepares MR images, and the MR images contain information about the T2 relaxation time constant. Subsequently, penetrating radiation-attenuating objects are determined in the MR images by means of the T2 relaxation time constant.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Inventors: Kirstin Jattke, Berthold Kiefer, Sonia Nielles-Vallespin, Stefan Roell, Marianne Vorbuchner
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Publication number: 20080231276Abstract: A magnetic resonance system has a basic magnet that generates a static basic magnetic field in an examination volume, and a whole-body antenna that emits a homogeneous radio-frequency field in the examination volume, the homogeneous radio-frequency field exhibiting an excitation frequency so that nuclei in an examination subject in the examination volume are excited to emit magnetic resonance signals, and a radio-frequency shield. The radio-frequency shield is arranged between the whole-body antenna and the basic magnet. The whole-body antenna is arranged between the radio-frequency shield and the examination volume. The radio-frequency shield is fashioned to exhibit a high shielding effect in a shielding frequency range that encompasses the excitation frequency. The shielding effect drops to a significantly lower shielding effect on both sides at side bands adjoining the shielding frequency range.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Inventors: Dirk Diehl, Wolfgang Renz, Lorenz-Peter Schmidt, Ulrich Von Knobloch
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Publication number: 20080231277Abstract: The present invention provides a highly-sensitive nuclear magnetic resonance (NMR) spectrometer which achieves a high Q factor using a superconductor, and concurrently which is provided with a probe antenna maintaining the magnetic homogeneity of the static magnetic field in a sample space. An antenna coil is fabricated by using a wire having a superconducting layer formed on the surface of a metal wire.Type: ApplicationFiled: January 23, 2008Publication date: September 25, 2008Inventors: Hiroyuki Yamamoto, Kazuo Saitoh, Haruhiro Hasegawa, Masaya Takahashi, Michiya Okada
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Publication number: 20080231278Abstract: A radio-frequency coil has a first element and a second element both being adjacently arranged so as to nip a division/join portion. The first element has a first main loop portion provided along an arrangement plain surface and a first sub-loop portion provided along a surface substantially perpendicular to the arrangement plain surface. The second element has a second main loop portion provided along the arrangement plain surface and a second sub-loop portion provided facing the first sub-loop. The first sub-loop portion and the second sub-loop portion generate an induced electromotive force such that, among magnetic fields generated when a current flows in one coil, a summation of the magnetic fields, which interlink with the other coil, becomes zero.Type: ApplicationFiled: March 17, 2008Publication date: September 25, 2008Inventors: Takahiro ISHIHARA, Kazuya Okamoto, Shinji Mitsui
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Publication number: 20080231279Abstract: An RF coil includes: a first loop coil element including a first plane closed by a first coil line; and a second loop coil element including a second plane closed by a second coil line, in which part of said first plane and part of said second plane face each other, wherein: said first loop coil element and said second loop coil element so move while maintaining the facing state as to vary the square measure of the facing area in which said first coil plane and said second coil plane face each other; said first loop coil element includes: a first spreading part having a first coil line so disposed that the distance of opposing by said first coil line parallel to a first moving direction, widens in said first moving direction, in a direction normal to said first moving direction in which the movement so takes place that the square measure of said facing area increases relative to said second loop coil element in a direction parallel to said first plane; and a first coil crossing part in which a first coil lineType: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Inventor: Yuji Iwadate
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Publication number: 20080231280Abstract: In a method and arrangement for local manipulation of a B1 field in a first region of an examination subject in an examination volume of a magnetic resonance system, a B1 measurement value that represents the B1 field in the sub-volume during an adjustment measurement is integrally determined, and in desired radio-frequency signal parameters for a subsequent magnetic resonance measurement are predetermined on the basis of the determined B1 measurement value. At least during the adjustment measurement, the B1 field is influenced within a second region counter to the manipulation intended in the first region by means of an auxiliary coil element which is arranged in or at the second region of the sub-volume remote from the first region.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Inventors: Helmut Greim, Steffen Wolf
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Publication number: 20080231281Abstract: An RF coil assembly for an MRI system includes a resonator formed by a cylindrical shield and pairs of opposing conductive legs disposed symmetrically around a central axis and extending the axial length of the shield. One set of conductive leg pairs is tuned to operate at the Larmor frequency of 13C and another set is tuned to operate at the Larmor frequency of 1H. Drive circuitry operates the RF coil assembly to produce 1H spin magnetization which is transferred to 13C magnetization by the nuclear overhauser effect and to acquire MR data from the 13C spins. Multinuclear measurements can be made simultaneously at different Larmor frequencies.Type: ApplicationFiled: August 20, 2007Publication date: September 25, 2008Inventors: Sean B. Fain, Matthew G. Erickson, Krishna N. Kurpad, James H. Holmes, Thomas M. Grist
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Publication number: 20080231282Abstract: Example systems, apparatus, circuits, and so on described herein concern parallel transmission in MRI. One example apparatus includes at least two field effect transistors (FETs) that are connected by a coil that includes an LC (inductance-capacitance) leg. The apparatus includes a controller that inputs a digital signal to the FETs to control the production of an output analog radio frequency (RF) signal. The LC leg is to selectively alter the output analog RF signal and the analog RF signal is used in parallel magnetic resonance imaging (MRI) transmission.Type: ApplicationFiled: March 7, 2008Publication date: September 25, 2008Applicant: CASE WESTERN RESERVE UNIVERSITYInventors: Mark A. Griswold, Jeremiah A. Heilman, Matthew J. Riffe, Oliver Heid, Markus Vester
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Publication number: 20080231283Abstract: Measurements made with an induction logging tool are responsive to formation conductivity and permittivity. The effect of permittivity can be substantially removed by multifrequency focusing.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: BAKER HUGHES INCORPORATEDInventors: Marina N. Nikitenko, Leonty A. Tabarovsky
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Publication number: 20080231284Abstract: Disclosed is a method for determining the ageing (SoH) of a battery (1, 2), such as a lead battery, a nickel metal hydride battery, a lithium ion battery or a capacitor for a vehicle. Several parameters (5.1 to 5.n) of the battery (1, 2) are detected or determined and two parameters (5.1 to 5.n) are predefined as a pair of parameters (5.1 to 5.n, 5.1 to 5.n) and are correlated in such a way that the parameter ranges that form the basis of each parameter (5.1 to 5.n) and value pairs (X1, Y1 to Xn, Ym) of the predefined pair of parameters (5.1 to 5.n, 5.1 to 5.n) that result from said ranges are weighted in classes.Type: ApplicationFiled: May 17, 2006Publication date: September 25, 2008Inventors: Peter Birke, Michael Keller, Manfred Malik
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Publication number: 20080231285Abstract: An electronic circuit tester is disclosed which is utilized for the testing and troubleshooting of the various lighting, control and signaling circuits required in the towing of a trailer, vehicle or other conveyance. The tester generally comprises an enclosure, which may be included as a part of a wiring harness connector, or separately attached to a wiring harness connector by means of electrical wiring. The testing circuit includes a plurality of input lines, logic means, and an alerting means. The testing circuits cause a distinct alert to be produced in response to each distinct test of the trailer device driving circuits of the vehicle.Type: ApplicationFiled: December 4, 2007Publication date: September 25, 2008Inventor: Kevin Mark Curtis
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Publication number: 20080231286Abstract: A sensor switch 111a connected to a constant voltage Vc via a breeder resistor 114a and dropper diodes 112a and 113a is connected to a microprocessor 120 that configures a wire abnormality detecting device 100, and the electric potential of the connection point between the dropper diodes 112a and 113a is inputted to the microprocessor 120 as a switch logic signal D1 via a signal wire 105 and a series resistor 131a. The signal voltage level of the switch logic signal D1 is inputted to the microprocessor 120 via an AD converter 123, and the microprocessor 120 cooperates with a program memory 121 to perform a determination of whether or not the signal voltage is in an abnormal intermediate voltage state. However, during a transitional period when the switch logic signal is changing between high and low, mistaken determination is prevented by avoiding abnormality determination.Type: ApplicationFiled: December 26, 2007Publication date: September 25, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shoso TSUNEKAZU, Koji HASHIMOTO, Daisuke EGUCHI
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Publication number: 20080231287Abstract: An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.Type: ApplicationFiled: March 18, 2008Publication date: September 25, 2008Applicant: FUJITSU LIMITEDInventor: Hiroyuki FUJIMOTO
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Publication number: 20080231288Abstract: A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.Type: ApplicationFiled: February 14, 2008Publication date: September 25, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Kou Sasaki
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Publication number: 20080231289Abstract: A wire diagnostic clamp including a clamp body configured to receive multiple electrical wires is provided. The wire diagnostic clamp also includes a sensor disposed within the clamp body and being configured to detect a defect in the multiple electrical wires. The wire diagnostic clamp further includes a mounting component configured to mount the wire diagnostic clamp to a substrate.Type: ApplicationFiled: March 19, 2007Publication date: September 25, 2008Applicant: GENERAL ELECTRIC COMPANYInventors: Meena Ganesh, Selaka Bandara Bulumulla
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Publication number: 20080231290Abstract: A capacitive position sensor has a periodic array of electrodes which form capacitors between pairs of the electrodes. The location of a dielectric inhomogeneity in the vicinity of the sensor is determined by comparison of the relative change in the capacitance of the capacitors. The comparison may be carried out using a capacitive Wheatstone Bridge arrangement. The sensor configuration has the advantage that it is independent of the absolute value of the dielectric constant of the environment in which the sensor is located.Type: ApplicationFiled: May 16, 2005Publication date: September 25, 2008Applicant: SCIENTIFIC GENERICS LTD.Inventor: Victor Evgenievich Zhitomirsky
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Publication number: 20080231291Abstract: A sensor for sensing a gap between the sensor and an object of interest within a semiconductor processing chamber is provided. The sensor includes a housing, a power source inside the housing, wireless communication circuitry, a controller, measurement circuitry and a plurality of capacitive plate pairs. The controller and wireless communication circuitry are coupled to each other, and to the power source. The plurality of capacitive plate pairs are configured to form capacitors having a capacitance that varies with the gap. Measurement circuitry is coupled to the controller and to the plurality of capacitive plate pairs. The measurement circuitry is configured to measure the capacitance of the capacitive plate pairs and provide indications thereof to the controller. The controller is configured to provide an indication relative to the gap based, at least in part, upon the measured capacitances.Type: ApplicationFiled: March 26, 2008Publication date: September 25, 2008Inventors: Craig C. Ramsey, DelRae H. Gardner
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Publication number: 20080231292Abstract: A device for capacitive measurement by a floating bridge, including: a sensor module including at least one measuring electrode and at least one guard electrode arranged close to a target connected to a general earth, at least one integrated circuit for capacitive measurement, provided with a guard to which the guard electrode is connected, having an input connected to the measuring electrode, a guard connected to the reference earth of the integrated circuit, an excitation output connected to the general earth, a measurement output, and structure for supplying the integrated circuit for capacitive measurement in floating mode.Type: ApplicationFiled: November 22, 2006Publication date: September 25, 2008Inventors: Frederic Ossart, Didier Roziere
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Publication number: 20080231293Abstract: A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: Qimonda AGInventors: Udo Hartmann, Juergen Weidenhoefer
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Publication number: 20080231294Abstract: A structural health monitoring circuit apparatus and method are based on electrical impedance variations of a piezoelectric patch, which is attached to a structure to be monitored. The circuit compares a known good sweep of frequency-impedance pairs with a contemporaneous sweep to generate an alarm when an error bound is exceeded. The impedance of the piezoelectric patch is determined though adjustment of a variable reactance in a bridge configuration. By suitable design of the bridge elements, the electrical impedance of the piezoelectric patch may be directly measured. A microprocessor controlled version of this device consumes less than 2 W of power, which may be further reduced by further large scale integration or reduction to a state machine on a programmable gate array. Ultimately, this device may give personnel warnings to aircraft, automobiles, bridges, elevated roads, buildings, or home structural failures.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: NDSU RESEARCH FOUNDATIONInventors: Chao You, Shirui Wang
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Publication number: 20080231295Abstract: A device and method are disclosed for electrical contacting of semiconductor devices for testing. One embodiment provides for testing semiconductor devices or integrated circuits, including a probe card with contact tips for the electrical contacting of the semiconductor devices. The electrical connection of at least one contact tip to the test system is adapted to be switched via a resistively switching memory cell. A resistively switching memory cell in the form of a nano switch is integrated in the electrical connection of the contact tip.Type: ApplicationFiled: March 18, 2008Publication date: September 25, 2008Applicant: QIMONDA AGInventor: Bernhard Ruf
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Publication number: 20080231296Abstract: In the case of a test apparatus for testing electronic components which are present in an assembly, in particular in the form of strips, a slide-like contacting board supporting device (28), to which the contacting board (22) can be fastened, is mounted on the test head (15), wherein the contacting board supporting device (28) can be moved parallel to the plane of the contacting board when the contacting nest (24) is docked on the test head (15), with the result that the contacting board (22) can be brought into different test positions which are laterally beside one another.Type: ApplicationFiled: March 29, 2007Publication date: September 25, 2008Applicant: MULTITEST ELEKTRONISCHE SYSTEME GmbHInventors: Maximilian Schaule, Manuel Petermann, Stefan Kurz, Andeas Nagy
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Publication number: 20080231297Abstract: A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.Type: ApplicationFiled: August 6, 2007Publication date: September 25, 2008Applicant: Unitest Inc.Inventor: Jong Koo Kang
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Publication number: 20080231298Abstract: An inspection apparatus for inspecting electrical characteristics of an inspection target object includes a movable mounting table for mounting the inspection target object thereon, a probe card disposed above the mounting table, and one or more displacement sensors, provided at one or more location of the mounting table, each of the sensors measuring a distance between the mounting table and the probe card or a vicinity thereof. The inspection target object is brought into electrical contact with the probe card by overdriving the mounting table.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Hiroshi YAMADA
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Publication number: 20080231299Abstract: A circuit board tester that uses a dual-stage translation to bring a unit under test (UUT) into physical and electric contact first with a series of tall probes, then with a series of short probes. Initially, the UUT is mounted on a support plate, and spaced apart from both the tall and short probes. First, in order to perform a functional test on the UUT, a first vacuum stage is engaged, and atmospheric pressure translates the UUT longitudinally until contact is made with a first hard stop, defining a first position. At this first position, the UUT is in contact with a series of tall probes, and is spaced apart from a series of short probes. After a function test is performed, a second vacuum stage is engaged in addition to, and independent of, the first vacuum stage. Atmospheric pressure translates the UUT longitudinally until contact is made with a second hard stop, defining a second position.Type: ApplicationFiled: April 2, 2007Publication date: September 25, 2008Inventors: Neil Adams, Stuart Eickhoff, Jon Hample
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Publication number: 20080231300Abstract: An probe tip position detecting method detects tip positions of a plurality of probes by using a tip position detecting device including a sensor unit for detecting tips of the probes and a movable contact body belonging to the sensor unit, the method used in inspecting electrical characteristics of an object to be inspected by bringing the object supported on a movable mounting table into electrical contact with the probes. The method includes a first step for moving the tip position detecting device by using the mounting table to thereby bring the contact the object into contact with the tips of the probes; a second step for further moving the mounting table to thereby move the contact body toward the sensor unit without causing elastic deformation to the probes; and a third step of determining a movement starting position of the contact body as the tip positions of the probes.Type: ApplicationFiled: March 12, 2008Publication date: September 25, 2008Applicant: TOKYO ELECTRON LIMTEDInventors: Hiroshi Yamada, Masaru Suzuki
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Publication number: 20080231301Abstract: An inspection apparatus includes a mounting table movable in X and Y directions and an alignment mechanism which performs an alignment of a target object placed on the mounting table. Further, the alignment mechanism includes an image pickup device which is movable in either one of the X and Y directions and is capable of being stopped at a desired position and a controller for performing a preliminary alignment of the target object by moving the image pickup device and the mounting table in respectively movable directions.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Masaru Suzuki, Yasuhito Yamamoto
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Publication number: 20080231302Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.Type: ApplicationFiled: March 24, 2008Publication date: September 25, 2008Inventor: Morgan T. Johnson
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Publication number: 20080231303Abstract: A semiconductor device with a number of contact pads for the electrical contacting of the semiconductor device is disclosed. A padding layer, which is manufactured of a hard material, is provided at least partially below an upper layer of the contact pads.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Applicant: Qimonda AGInventors: Jochen Kallscheuer, Sascha Nerger, Bernhard Ruf
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Publication number: 20080231304Abstract: An apparatus and method of controlling the temperature of a thermal chuck system are disclosed. The system includes a temperature controller which controls a temperature transition in a thermal chuck. The temperature controller comprises inputs that receive air and fluid from an air source and water source, respectively, and an output for alternately transferring the air and fluid in proportions to the thermal chuck. A time proportional controller generates the proportions by computing a proportion band in each of a plurality of control regions. The proportion bands are used by the temperature controller to manage the flow of air and fluid to the chuck such that a minimum undershoot of the temperature transition is realized.Type: ApplicationFiled: April 1, 2008Publication date: September 25, 2008Applicant: Temptronic CorporationInventors: Norbert W. Elsdoerfer, Olga V. Mikulina, Abdellah Mourchid
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Publication number: 20080231305Abstract: An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.Type: ApplicationFiled: March 24, 2008Publication date: September 25, 2008Inventors: Igor Y. Khandros, Benjamin N. Eldridge, Gaetan L. Mathieu, Thomas H. Dozier, William D. Smith
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Publication number: 20080231306Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.Type: ApplicationFiled: December 22, 2006Publication date: September 25, 2008Applicant: STMicroelectronics, Inc., State of Incorporation: DelawareInventors: Riccardo Maggi, Massimo Scipioni
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Publication number: 20080231307Abstract: Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Inventors: Jeanne P. Bickford, John R. Goss, Nazmul Habib, Robert J. McMahon
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Publication number: 20080231308Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.Type: ApplicationFiled: September 21, 2007Publication date: September 25, 2008Inventors: Ronald Ho, Thomas G. O'Neill, Robert D. Hopkins, Frankie Y. Liu
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Publication number: 20080231309Abstract: A performance board which is attached to a semiconductor test apparatus and on which devices under test are mounted is provided. The performance board includes: a substrate; sockets which are attached to the surface of the substrate and on which devices under test are mounted; and an adiathermic cover member attached to the rear surface of a region of the substrate on which the sockets are mounted.Type: ApplicationFiled: September 29, 2007Publication date: September 25, 2008Applicant: ADVANTEST CORPORATIONInventor: SATOSHI TAKESHITA
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Publication number: 20080231310Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.Type: ApplicationFiled: October 20, 2007Publication date: September 25, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventors: Narayanan Vijayaraghavan, Balwant Singh
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Publication number: 20080231311Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.Type: ApplicationFiled: May 29, 2008Publication date: September 25, 2008Applicant: International Business Machines Corp.Inventors: VINCENZO CONDORELLI, Claudius Feger, Kevin C. Gotze, Nihad Hadzic, John U. Knickerbocker, Edmund J. Sprogis
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Publication number: 20080231312Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.Type: ApplicationFiled: May 22, 2008Publication date: September 25, 2008Inventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
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Publication number: 20080231313Abstract: A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the internal circuit, a feedback line branched off from signal line in buffer transmitting data signal to an output stage circuit of the output buffer, and a delay test circuit connected to the feedback line.Type: ApplicationFiled: March 17, 2008Publication date: September 25, 2008Applicant: NEC Electronics CorporationInventors: You Miyazaki, Mamoru Konno
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Publication number: 20080231314Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: ApplicationFiled: May 27, 2007Publication date: September 25, 2008Inventors: Steven Teig, Herman Schmit, Jason Redgrave
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Publication number: 20080231315Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: ApplicationFiled: May 27, 2007Publication date: September 25, 2008Inventor: Steven Teig
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Publication number: 20080231316Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.Type: ApplicationFiled: May 30, 2008Publication date: September 25, 2008Inventors: David Lewis, Paul Leventis, Vaughn Betz, Thomas Yau-Tsun Wong, Andy Lee, Philip Pan
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Publication number: 20080231317Abstract: A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second groups of LABs can be columns of LABs, and the columns can be vertically offset from each other (e.g., by half the number of logic elements in each LAB). The offsetting can advantageously allow more LABs to be reached using a single routing channel, or without using any routing channel, thereby reducing communication latency and improving overall IC performance.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: Altera CorporationInventor: David Cashman
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Publication number: 20080231318Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: ApplicationFiled: May 27, 2007Publication date: September 25, 2008Inventors: Herman Schmit, Randy Renfu Huang