Abstract: A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

Abstract: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.

Abstract: A TOP level switch for use in a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The TOP level shifter transmits an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both, level shifter paths emit a signal to the respectively associated input of the signal evaluation circuit.

Abstract: In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.

Abstract: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.

Abstract: A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit.

Abstract: An encoder with signal conditioning of an emitter drive signal is described. In one embodiment, the encoder includes a peak comparator, a pulse generator, a threshold comparator, and digital circuitry. The peak comparator outputs a peak comparator signal based on a comparison of an input sinusoidal signal stored at a first time with the input sinusoidal signal stored at a second time. The pulse generator determines a peak of the input sinusoidal signal based on the peak comparator signal. The threshold comparator compares a differential signal amplitude with a differential signal amplitude window at approximately the peak of the input sinusoidal signal. The differential signal amplitude is associated with the input sinusoidal signal. The digital circuitry generates an emitter modification signal in response to a determination that the differential signal amplitude is outside of the differential signal amplitude window.

Abstract: A signal transfer system. A first device operates with a first voltage and outputs a first signal and a second signal. A protection circuit receives the first and second signals and outputs the first and second signals when the first voltage is greater than or equal to a predetermined voltage, and provides a third signal and a fourth signal when the first voltage is smaller than the predetermined voltage. A delay circuit delays the second and fourth signals to generate a first delay signal and a second delay signal, respectively. A second device operates with the first signal and the first delay signal when the first voltage is greater than or equal to the predetermined voltage, and operates with the third signal and the second delay signal when the first voltage is smaller than the predetermined voltage.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.

Abstract: The present invention provides a ramp generator capable of appropriately setting a rise starting point of an output voltage of a ramp waveform and an output voltage at the time of stable output. A current adjustment unit including a differential pair of transistors and an amplifier constitute a feedback circuit. By controlling the charging/discharging of an integration capacitor by ON/OFF of a discharge current source connected to a common emitter terminal of the current adjustment unit, an output of the ramp waveform outputted from an output terminal disposed at the connection end of the integration capacitor is controlled.

Abstract: Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Abstract: The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL.

Abstract: A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.

Abstract: A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied.

Abstract: A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.

Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.

Abstract: Disclosed are methods and systems for subnanosecond rise time high voltage (HV) electric pulse delivery to biological loads. The system includes an imaging device and monitoring apparatus used for bio-photonic studies of pulse induced intracellular effects. The system further features custom fabricated microscope slide having micro-machined electrodes. A printed circuit board to interface the pulse generator to the micro-machined glass slide having the cell solution. An low-parasitic electronic setup to interface with avalanche transistor-switched pulse generation system. The pc-board and the slide are configured to match the output impedance of the pulse generator which minimizes reflection back into the pulse generator, and minimizes distortion of the pulse shape and pulse parameters. The pc-board further includes a high bandwidth voltage divider for real-time monitoring of pulses delivered to the cell solutions.

Abstract: Converter systems are disclosed that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.

Abstract: A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.

Abstract: A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions.

Abstract: A circuit for regulating power is disclosed. The present invention provides circuits and methods for current sensing variations, static droop settings, mismatched phase outputs, and temperature variations in a multiphase power regulator. The circuits may include a calibration controller that senses and regulates both a current sensing circuit and the droop in a power regulator over a range of temperatures thus equalizing phase outputs. The present invention includes the schematic organization and implementation of the circuit, the circuit's calibration, its use, and implementation. This invention advantageously provides circuits and methods to properly power a processor or IC chip according to the unique power specifications of the processor or chip.

Abstract: The invention provides in one aspect a method for vibration sensing. The method comprises powering down at least one electronic component required for recording vibration data; powering down a processor used to carry out one or more steps of the method; measuring the vibration level of a machine in a frequency band of interest; comparing the measured vibration level with a user-selected reference vibration level; and powering up the processor if the measured vibration level is greater than or equal to the reference vibration level. In another aspect the invention provides a system for vibration sensing.

Abstract: A power-diode-driver uses a single power source to supply power to the sub-drivers inside. The sub-drivers are well isolated so that they can be safely and easily expanded by connecting to other device or driver. Thus, the power-diode driver has a changeable turn-on time and a highly modulated assembly. And, hence, the present invention is suitable for mass producing reliable power-diode drivers.

Abstract: Disclosed is a semiconductor silicon wafer having an electric power supply affixed to the backside of the wafer. By fabricating the electric power supply onto the backside of the wafer that has been left unused, the semiconductor chip can have a self-supplied power, realizing the self-powered semiconductor chip with an increased efficiency. Further, since the electric power supply is installed on the wafer, not the semiconductor chip, the fabrication procedure becomes very simple, and the battery can be mounted on any type of chip.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A charge pump circuit including a plurality of switches and a switch control circuit is provided. The charge pump circuit is suitable for a display panel. The switches switch from “off” state to “on” state in an enable transition, and switch from “on” state to “off” state in a disable transition. The switch control circuit is coupled to the switches for controlling the on/off states of the switches and allowing the charge pump circuit to provide an output voltage that is different from an input voltage. The switch control circuit prolongs the time required for enable transition of the switches to be longer than the time for disable transition thereof. The equivalent impedances of the switches change from high values to low values when the switches are at the enable transition.

Abstract: The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.

Abstract: A semiconductor integrated circuit includes a first power supply whose potential is controlled under control operation from an external control circuit, a second power supply whose potential is controlled under control operation from the external control circuit, and whose potential can be set independently of the first power supply, a first power-supply system comprising a circuit driven by the first power supply, a second power-supply system comprising a circuit driven by the second power supply, and a connecting circuit that performs connecting operation between a first high-potential line of the first power-supply system and a second high-potential line of the second power-supply system in response to a potential-matching signal indicating that the first power-supply system and the second power-supply system are operated by the same potential from the external control circuit.

Abstract: An internal voltage generating circuit for use in a semiconductor memory device includes a reference voltage input terminal to receive a reference voltage, a comparison unit to output a first internal voltage, the first internal voltage having a voltage level based at least in part on the reference voltage, a first feedback unit to receive the first internal voltage and an external voltage and to provide a first feedback internal voltage to the comparison unit, a loading circuit to output a second internal voltage, and a second feedback unit to receive the second internal voltage from the loading circuit and to provide a second feedback internal voltage to the comparison unit.

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.

Abstract: The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell.

Abstract: The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of the logic portion and the memory portion, a Vth control for supplying a Vth control signal to one or both of the logic portion and the memory portion, and an antenna. Each of the plurality of transistors has a first gate electrode which is input with a logic signal, a second gate electrode which is input with the Vth control signal, and a semiconductor film such that the second gate electrode, the semiconductor film, and the first gate electrode are provided in this order from the bottom.

Abstract: A tuner and a demodulating unit thereof are provided. A trap filter for a specific frequency is installed in the IF demodulating unit so as to eliminate a frequency signal acting as a beat component.

Abstract: A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

Abstract: Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include controlling gain, power and/or a noise figure by selectively enabling one or more of a plurality of gain stages by activating one or more of a plurality of pairs of switching transistors. Each of the gain stages may comprise complementary inverter pairs, with the gain of each of the gain stages binary weighted and stored in a lookup table. A feedback resistance coupled across the gain stages may be adjusted, and may comprise a plurality of individually addressable resistors, with the resistance binary weighted and stored in a lookup table. The adjusting of the feedback resistance may comprise switching one or more of a plurality of switching transistors, each connected in parallel with one of the individually addressable resistors, which may shunt one or more of the individually addressable resistors.

Abstract: In a third operation in an amplifier, in which first and second amplifier circuits amplify a input signal, a distribution circuit adjusts the power of the signal supplied to the first amplifier circuit to within a range in which the input power to the first amplifier circuit and the output power from the first amplifier are proportional to each other. In a linear operation, the power of the signal from the first amplifier circuit and input to the comparison circuit and the power of the signal from the second amplifier circuit and input to the comparison circuit are equal. The comparison circuit adjusts the gain or the saturated power of the second amplifier circuit on the basis of the difference between the signals from the first and second amplifier circuits and input to the comparison circuit, so that the input power to the second amplifier circuit and the output power from the second amplifier circuit are proportional to each other.

Abstract: A power divider/combiner include a power n-dividing unit for dividing a power of an input signal to n divided signals (n: positive integer not less than 2); n phase adjustment units for adjusting a phase of each of said n divided signals; n amplifiers for amplifying each of said n divided signals after phase adjustment by said n phase adjustment units; and power combining units for combining said n divided signals amplified by said n amplifiers and outputting a power combined signal.

Abstract: An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties.

Abstract: Small-signal and other circuit design techniques realized by carbon nanotube field-effect transistors (CNFETs) to create analog electronics for analog signal handling, analog signal processing, and conversions between analog signals and digital signals. As the CNFETs exist and operate at nanoscale, they can be readily collocated or integrated into carbon nanotube sensing and transducing systems. Such collocation and integration is at, or adequately near, nanoscale.

Abstract: The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.

Abstract: The invention relates to an differential amplifier circuit comprising an amplifier stage comprising a first and a second transistor, the gates of which are connected to differential input terminals of the amplifier stage. The differential amplifier further comprises a temperature compensation circuit comprising a third and fourth transistor. The third transistor is connected to the source of the first transistor and the fourth transistor is connected to the source of the second transistor. Further, the temperature compensation circuit comprises a constant current source connected to the respective sources of the third and fourth transistors. Thereby the temperature compensation circuit is arranged to provide a feedback resistance in dependence on the operating temperature so as to compensate for variations of the resistance of the first and second transistors.

Abstract: An amplifying circuit includes an operational amplifier, a pull-up circuit and a pull-down circuit. The operational amplifier generates a first pull-up signal, a first pull-down signal and an output signal, wherein the phases of the first pull-up signal and the first pull-down signal are out of phase with the output signal. The pull-up circuit includes a first controlling module for outputting a second pull-up signal according to the first pull-up signal, and a first adjusting module for adjusting the output signal according to the second pull-up signal. The pull-down circuit includes a second controlling module for outputting a second pull-down signal according to the first pull-down signal, and a second adjusting module for adjusting the output signal according to the second pull-down signal.

Abstract: An operational amplifier including an input amplifier configured to amplify at least one differential input signal, a first common mode feedback amplifier configured to amplify a first common mode voltage, a cascode amplifier configured to cascode-amplify output signals from the input amplifier and the first common mode feedback amplifier, a first common mode voltage generator configured to generate a central voltage of the output signal from the cascode amplifier and input the central voltage to the first common mode feedback amplifier, and a frequency compensator configured to feedback the output signal of the cascode amplifier to the first common mode feedback amplifier so as to compensate a frequency of the first common mode feedback amplifier.

Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed. Aspects of one method may include providing an individual current source for each input transistor to a low noise amplifier (LNA), wherein the individual current sources may be isolated from each other when the LNA is turned off. The individual current sources may also form a common current source for the input transistors when the LNA is turned on. Accordingly, the input transistors to the LNA may float when the LNA is turned off, thereby coupling the input signal voltage to the source and drain terminals. The individual current sources may be isolated from each other by a coupling transistor that is turned off. When the LNA is turned on, the coupling transistor may be turned on to couple the individual current sources to each other to form the common current source for the input transistors.

Abstract: An amplifier according to the present invention includes an amplifying transistor, and an impedance converter circuit coupled to an output unit of the amplifying transistor and including a plurality of impedance converting transistors different in input impedance, which are series-connected.

Abstract: A differential amplifier circuit is connected to the input node and the output node of the final amplification stage through detection circuits. The signal level difference output from the differential amplifier circuit does not change even if the input power varies. Because a change in the power gain at the output node does not travel back to the input node when the load impedance of the wireless frequency power amplifier varies, it is possible to detect only the change in the load impedance. Damage to the final stage can be prevented by controlling the operating current of the final stage and the gain of the drive stage according to the detected load variation. Nonlinear distortion in the wireless frequency power amplifier output can also be reduced by detecting and canceling the change in the gain of the drive stage by changing the gain of the adjustment stage.