Abstract: A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.

Abstract: An integrated circuit includes a first electrode and a dielectric material layer contacting a first portion of the first electrode. The integrated circuit includes a spacer material layer contacting a sidewall portion of the dielectric material layer and a second portion of the first electrode. The second portion is within the first portion. The integrated circuit includes resistivity changing material contacting the spacer material layer and a third portion of the first electrode. The third portion is within the second portion. The integrated circuit includes a second electrode contacting the resistivity changing material.

Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall, having a mixture of a first semiconductor material with a first lattice constant, a second semiconductor material and carbon, the second semiconductor material having a second lattice constant differing from the first lattice constant.

Abstract: A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially covering the reverse biased device, the photosensitive layer releasing electrons and holes when struck by photons, wherein the photon generated electrons and holes in the photosensitive layer reach the reverse biased device and create a combination current therein when a light shines thereon.

Abstract: Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described.

Abstract: A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer.

Abstract: Provided is a substrate for a light-emitting device having good light emitting efficiency and light-emitting device using the substrate. A light transparent substrate 10 is layered with a first layer 30 having a refractive index higher than that of the light transparent substrate 10 and a second layer 40 having a refractive index lower than that of the first layer. The refractive index of the first layer 30 is set to be 1.35 times as high as that of the second layer 40. With this layer structure, in an emitting layer of the light-emitting device, a wave front of a spherical wave form exited from a point light source in the front direction is converted into that of a plane wave form, and exited outside the substrate at a high efficiency.

Abstract: The present invention relates to a polymer film comprising a polymer having liquid crystallinity, having a number-average molecular weight in terms of polystyrene of 103 to 108 and having an electron mobility or hole mobility of 10?5 cm2/Vs or more, and having a film thickness in the range from 1 nm to 100 ?m. This polymer film can be used for various polymer film devices such as an organic transistor, organic solar battery, optical sensor, electrophotographic photoreceptor, spatial light modulator, photorefractive device and the like.

Abstract: A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

Abstract: A sacrificial lead and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 three and five lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. In addition the sacrificial lead may be at the center of an opposite edge of the SOT-23 package.

Abstract: In a stacked semiconductor device assembly, solder balls 2c on the four corners most susceptible to warpage are used as test terminals in the stacked semiconductor device assembly alone, out of solder balls 2a that are used for mounting semiconductor devices on a mounting board 5 and arranged in a grid-like fashion. Thus during packaging, even when warpage occurs in the stacked semiconductor device assembly and causes a faulty connection in these terminals, it is possible to reduce the occurrence of defects in a package because these terminals are not used for operations in the package.

Abstract: An active device array substrate including a substrate, an active device array, an detecting circuit, a plurality of driver chip pads, a plurality of flexible printed circuit (FPC) pads, a plurality of connection lines and an inner shorting ring is provided. The active device array and the detecting circuit are disposed on the substrate, and the detecting circuit is electrically connected to the active device array. The driver chip pads and the FPC pads are disposed on the substrate, wherein the driver chip pads are electrically connected to the active device array. The connection lines are disposed on the substrate, and each of the connection lines is respectively connected to the detecting circuit and the corresponding FPC pad. The inner shorting ring is disposed on the substrate, and the inner shorter ring is respectively electrically connected to the corresponding FPC pad and the active device array.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: A thin film transistor (TFT) display panel as well as a manufacturing method and a detection method thereof are provided. The TFT display panel comprises at least two display regions and a detection region, wherein a gate detection line is correspondingly connected at least with all the gate lines from one of the display regions in the detection region. The embodiments of the present invention improve the safety of the circuits in the detection region, and simplify the mask process of the TFT display panel and the detection process for the display region, which in turn increases the production efficiency of the TFT and reduces the production cost.

Abstract: A thin film transistor array substrate in accordance with the present invention comprising a semiconductor layer formed over the substrate and having source/drain regions, a gate insulating film, a gate electrode, an interlayer insulating film, wiring electrodes connected to the source/drain regions, a protective film, a pixel electrode connected to the wiring electrode, a lower capacitor electrode formed with and extending from the semiconductor layer, a common line electrode formed from the same layer as the gate electrode and arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween, and an upper capacitor electrode arranged in the opposed position to the common line electrode with a dielectric film (protective film) having film thickness thinner than the interlayer insulating film interposed therebetween.

Abstract: Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.

Abstract: Embodiments of a thin film transistor (TFT) are disclosed.

Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor 1, a supporting substrate 3 is composed of AlN, AlGaN, or GaN. An AlyGa1-yN epitaxial layer 5 has a surface roughness (RMS) of 0.25 mm or less, wherein the surface roughness is defined by a square area measuring 1 ?m per side. A GaN epitaxial layer 7 is provided between the AlyGa1-yN supporting substrate 3 and the AlyGa1-yN epitaxial layer 5. A Schottky electrode 9 is provided on the AlyGa1-yN epitaxial layer 5. A first ohmic electrode 11 is provided on the AlyGa1-yN epitaxial layer 5. A second ohmic electrode 13 is provided on the AlyGa1-yN epitaxial layer 5. One of the first and second ohmic electrodes 11 and 13 constitutes a source electrode, and the other constitutes a drain electrode. The Schottky electrode 9 constitutes a gate electrode of the high electron mobility transistor 1.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path 20 of the power device includes: a JFET (junction) region 2, a drift region 3, and a substrate 4, which have ON resistances exhibiting a positive temperature dependence; and a channel region 1, which has an ON resistance exhibiting a negative temperature dependence. A temperature-induced change in the ON resistance of the entire power device is derived by allowing a temperature-induced change ?Rp in the ON resistance in the JFET (junction) region 2, the drift region 3, and the substrate 4, which have ON resistances exhibiting a positive temperature dependence, and a temperature-induced change ?Rn in the ON resistance in the channel region 1, which has an ON resistance exhibiting a negative temperature dependence, to cancel out each other. With respect to an ON resistance of the entire power device at ?30° C.

Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.

Abstract: A method for testing a status of a light unit is provided, wherein the method includes electrically coupling the light unit to a controller and transmitting a negative voltage from the controller to the light unit. The method also includes detecting at least one of current and voltage passing through the light unit and determining a status of the light unit based on at least one of the detected current and detected voltage.

Abstract: A light emitting device includes a light emitting diode (LED), a concentrator element, such as a compound parabolic concentrator, and a wavelength converting material, such as a phosphor. The concentrator element receives light from the LED and emits the light from an exit surface, which is smaller than the entrance surface. The wavelength converting material is, e.g., disposed over the exit surface. The radiance of the light emitting diode is preserved or increased despite the isotropic re-emitted light by the wavelength converting material. In one embodiment, the polarized light from a polarized LED is provided to a polarized optical system, such as a microdisplay. In another embodiment, the orthogonally polarized light from two polarized LEDs is combined, e.g., via a polarizing beamsplitter, and is provided to non-polarized optical system, such as a microdisplay. If desired, a concentrator element may be disposed between the beamsplitter and the microdisplay.

Abstract: A method for growing a ?-Ga2O3 single includes preparing a ?-Ga2O3 seed crystal and growing the ?-Ga2O3 single crystal from the ?-Ga2O3 seed crystal in a predetermined direction.

Abstract: One embodiment of the present invention provides an InGaAlN-based semiconductor light-emitting device which comprises an InGaAlN-based semiconductor multilayer structure and a carbon-based substrate which supports InGaAlN-based semiconductor multilayer structure, wherein the carbon-based substrate comprises at least one carbon-based layer. This carbon-based substrate has both high thermal conductivity and low electrical resistivity.

Abstract: A housing for an optoelectronic component which includes a carrier with a chip mounting surface is disclosed. An optical element which is produced separately from the carrier is applied to the carrier. The chip mounting surface and the optical element define a parting plane, the parting plane between carrier and optical element being arranged in the plane of the chip mounting surface. Also disclosed is an optoelectronic component having a housing of this type and a method for producing an optoelectronic component of this type.

Abstract: At un upper part of an AlGaInP based compound semiconductor layer including an active layer 14 sandwiched by a lower cladding layer 14 and an upper cladding layer 15, a circular electrode 19 for wire bonding and cross-shaped branch electrodes 18 for current spreading connected to the circular electrode 19 are formed. A contact electrode 17 for current injection is connected to the branch electrodes 18 for current spreading. An interface contact electrode 17 for current injection is provided under the AlGaInP based compound semiconductor layer. A light reflection mirror layer 10 is provided under the interface contact electrode 12 for current injection. The interface contact electrode 12 for current injection is provided right under an outer periphery of the electrode 19 for wire bonding or under a region in vicinity of the outer periphery of the electrode 19 for wire bonding.

Abstract: An optoelectronic component is described, comprising a semiconductor body that emits electromagnetic radiation of a first wavelength when the optoelectronic component is in operation, and a separate optical element disposed spacedly downstream of the semiconductor body in its radiation direction. The optical element comprises at least one first wavelength conversion material that converts radiation of the first wavelength to radiation of a second wavelength different from the first.

Abstract: A white light emitting device including: a blue light emitting diode chip having a dominant wavelength of 443 to 455 nm; a red phosphor disposed around the blue light emitting diode chip, the red phosphor excited by the blue light emitting diode chip to emit red light; and a green phosphor disposed around the blue light emitting diode chip, the green phosphor excited by the blue light emitting diode chip to emit green light, wherein the red light emitted from the red phosphor has a color coordinate falling within a space defined by four coordinate points (0.5448, 0.4544), (0.7079, 0.2920), (0.6427, 0.2905) and (0.4794, 0.4633) based on the CIE 1931 chromaticity diagram, and the green light emitted from the green phosphor has a color coordinate falling within a space defined by four coordinate points (0.1270, 0.8037), (0.4117, 0.5861), (0.4197, 0.5316) and (0.2555, 0.5030) based on the CIE 1931 color chromaticity diagram.

Abstract: An LED element of an LED stream has an LED and a hollow seat for holding the LED. The LED has a body and two pins extended from a bottom face of the body. The hollow seat has two opposite through side holes defined in an outside of the hollow seat. To assembly the LED element, the LED with the two pins upwardly plugs to inside of the hollow seat. Then the two pins respectively and outwardly pass through the corresponding through side hole of the seat until the body is held by an upper portion of the hollow seat.

Abstract: A light-emitting element package including a heat conductive layer having a first surface and a second surface, a dielectric layer disposed on the first surface of the heat conductive layer and having an opening exposing the heat conductive layer, two electrodes disposed on the dielectric layer at a side far away from the heat conductive layer, a light-emitting element, and a transparent sealing layer. The light-emitting element is disposed in the opening, carried on the first surface of the heat conductive layer, and electrically coupled to the two electrodes. The transparent sealing layer encapsulates the light-emitting element, the heat conductive layer, and the two electrodes, and exposes part of the two electrodes and the second surface of the heat conductive layer.

Abstract: Disclosed are a light emitting device having a zener diode therein and a method of fabricating the light emitting device. The light emitting device comprises a P-type silicon substrate having a zener diode region and a light emitting diode region. A first N-type compound semiconductor layer is contacted to the zener diode region of the P-type silicon substrate to exhibit characteristics of a zener diode together with the P-type silicon substrate. Further, a second N-type compound semiconductor layer is positioned on the light emitting diode region of the P-type silicon substrate. The second N-type compound semiconductor layer is spaced apart from the first N-type compound semiconductor layer. Meanwhile, a P-type compound semiconductor layer is positioned on the second N-type compound semiconductor layer, and an active layer is interposed between the second N-type compound semiconductor layer and the P-type compound semiconductor layer.

Abstract: Disclosed is a light source, which includes a light-permeable casing, a thermoconductor, which is mounted inside the casing and has a flat end portion, a plurality of radiation fins fastened to the periphery of the thermoconductor inside the casing, a light source formed of an array of LEDs and installed in the flat end portion of the thermoconductor inside the casing, and a power unit mounted inside the casing to provide the light source with the necessary working voltage.

Abstract: An LED element having a voltage regulating capability has a body, two pins, a resistor and a conductive sleeve. The resistor is connected to a shorter pin through the conductive sleeve, so an operator can easily use the conductive sleeve to cover the shorter pin and one of two terminals of the resistor. Further, to increase connecting strength among the conductive sleeve, the shorter pin and the terminal of the resistor, an operator further uses a tongs to deform the conductive sleeve to tight the pin and the terminal.

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N? layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N? layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N? layer in an area contained in the body layer in plane view.

Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.

Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall and includes a mixture of a first semiconductor material, having a first lattice constant and a second semiconductor material with a second lattice constant differing from the first lattice constant, wherein a proportion of the second semiconductor material increases with increasing distance from the side wall.

Abstract: Abstract Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.

Abstract: A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.