Abstract: A semiconductor device fabrication method for forming a gate insulating film of a low leakage transistor and a gate insulating film of a high performance transistor. A first SiON film is formed over a Si substrate through first film formation. The first SiON film is left where the low leakage transistor is to be formed, and is removed where the high performance transistor is to be formed. Through second film formation, a second SiON film is formed where the first SiON film is removed, and a third SiON film including the first SiON film is formed where the first SiON film is left. The formed first SiON film has thickness and nitrogen concentration so that the third SiON film has thickness and nitrogen concentration to be the gate insulting film of the low leakage transistor.

Abstract: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

Abstract: The semiconductor integrated circuit includes: a first electrode; a transistor, having a second electrode, formed on a semiconductor substrate; and third and fourth electrodes formed in a same metal layer. The first electrode is connected with a diffusion region constituting the transistor. The second electrode constitutes the gate of the transistor. The third and fourth electrodes are respectively in a comb shape and formed to at least partly overlie the transistor. None of the first to fourth electrodes is connected with any of the other electrodes.

Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.

Abstract: A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.

Abstract: A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance.

Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

Abstract: A semiconductor sensor and a manufacturing method of the same capable of making the specific gravity of a weight part to be greater than that of a weight part made of semiconductor material only is disclosed. The semiconductor sensor includes the weight part, a supporting part, a flexible part, and plural piezoresistive elements. The weight part includes a weight part photosensitive resin layer made of photosensitive resin in which metal particles are included. The supporting part surrounds and is separated from the weight part. The flexible part is provided between the weight part and the supporting part to support the weight part. The flexible part includes a flexible part semiconductor layer where the plural piezoresistive elements are formed. This configuration allows the specific gravity of the weight part photosensitive resin layer greater than that of the weight part semiconductor layer due to the metal particles.

Abstract: A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.

Abstract: A method of manufacturing a back-side (14) illuminated image sensor (1) is disclosed, comprising the steps of: starting with a wafer (2) having a first (3) and a second surface (4), providing light sensitive pixel regions (5) extending into the wafer (2) from the first surface (3), securing the wafer (2) onto a protective substrate (7) such that the first surface (3) faces the protective substrate, the wafer comprising a substrate of a first material (8) with an optical transparent layer (9) and a layer of semiconductor material (10), wherein the substrate (8) is selectively removed from the layer of semiconductor material by using the optical transparent layer (9) as stopping layer. For back-side illuminated image sensors, light has to transmit through the semiconductor layer and enter into the light sensitive pixel regions (5). In order to reduce absorption losses, it is very advantageous that the semiconductor layer (10) can be made relatively thin with a good uniformity.

Abstract: An object of the present invention is to provide a solid-state image sensor including a filter membrane that has excellent light resistance and can be thinned. A solid-state image sensor 1 having a plurality of pixels, wherein each of the plurality of pixels includes a filter membrane 21 for transmitting light of a predetermined color, and a photoelectric conversion unit 17 for converting the light transmitted through the filter membrane 21 into a charge; the filter membrane 21 is a single layer film composed of an inorganic material; and an optical thickness of the single layer film is smaller than a thickness equivalent to one half of a wavelength of the predetermined color, by a thickness corresponding to an amount of the light of the predetermined color absorbed by the inorganic material.

Abstract: An image capturing device includes an image sensor package and a lens module aligned with the image sensor package. The image sensor package includes a substrate, at least one passive component, an insulative layer, and an image sensor. The substrate has a surface facing an object side of the image capturing device, the surface defines a cavity therein. The at least one passive component is disposed within the cavity and electrically connected to the substrate. The insulative layer is received in the cavity and encases the at least one passive component. The image sensor is disposed on the insulative layer and electrically connected to the substrate. The holder has an end connecting with the barrel and an opposite end secured on the substrate.

Abstract: In fabrication of a semiconductor device mounted on a wiring board, a semiconductor circuit portion is formed over a glass substrate. Then, an interposer having connection terminals are bonded to the semiconductor circuit portion. After that, the glass substrate is peeled off from the semiconductor circuit portion, and a mold resin is poured to cover the periphery of the semiconductor circuit portion from a direction of the separation plane. Then, the mold resin is heated under predetermined conditions to be hardened.

Abstract: An image capturing apparatus has a plurality of solid-state image capturing devices each having light receiving sections laminated in a depth direction of a semiconductor substrate. The devices are sequentially arranged in a direction along a substrate surface. Incident light waves having wavelength bands corresponding to depths of respective light receiving sections are detected there and generate signal charges. Bands are associated with light receiving sections by the wavelength dependence of the optical absorption. Trench sections each reach from a light incident surface or an opposite substrate surface to respective light receiving sections that do not overlap each other in a plane view. Electric charge transfer sections transfer electric charges independently from the light receiving sections via side wall portions of their respective trenches to the light incident surface side or the opposite substrate surface side at the time of driving readout gate electrodes at each trench section.

Abstract: A solid-state imaging device having a plurality of light-receiving sections which are disposed in a substrate and which generate charge in response to incident light, a planarizing layer which covers predetermined elements disposed on the substrate to perform planarization, a plurality of signal lines disposed above the planarizing layer and a waveguide which guides incident light to each of the light-receiving sections, the waveguide passing through the space between the plurality of signal lines.

Abstract: An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.

Abstract: In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed.

Abstract: An image sensing chip package includes an image sensing chip having an image sensor disposed on a circuit side thereof that includes electrical conductive pads. A glue layer is applied to the circuit side and around the image sensor. A flexible film wraps the chip in such a way that an inner surface of the film faces the circuit side of the chip, an opening thereof corresponds to the image sensor, an area of the inner surface near the edges of the opening attaches to the glue layer, an inner end of each of conductors disposed on the inner surface of said film bonds to each of the electrical conductive pads, and an outer end of each of the conductors is exposed to connect with other electrical elements. A light transparent member is disposed on an outer surface of the film to seal the opening of the film.

Abstract: A semiconductor optical receiver device is provided, which a mesa comprising a plurality of semiconductor crystal layers formed on a semiconductor substrate including a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer and including a first contact layer on the semiconductor substrate, a plurality of electrodes to apply electric field to the pn junction are coupled on the semiconductor substrate, a second contact layer is formed on a buried layer in which the mesa is buried, and the electric field is applied to the pn junction through the first and second contact layers.

Abstract: A semiconductor radiation detector crystal is patterned by using a Q-switched laser to selectively remove material from a surface of said semiconductor radiation detector crystal, thus producing a groove in said surface that penetrates deeper than the thickness of a diffused layer on said surface.

Abstract: A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage.

Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Abstract: A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same.

Abstract: An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and bulk transistors on a semiconductor substrate is disclosed.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract: Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.

Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.

Abstract: An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate.

Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).

Abstract: The present invention discloses a capacitor in an integrated circuit which comprises a first and second conductive lines substantially parallel to each other and having a thickness equals substantially to a sum of a via thickness and an interconnect thickness, the first and second conductive lines, the via and the interconnect being formed by a single deposition step, and at least one dielectric material in a space horizontally across the first and second conductive lines, wherein the first and second conductive lines serve as two conductive plates of the capacitor, respectively, and the dielectric material serves as an insulator of the capacitor.

Abstract: In the semiconductor device according to the present invention, a lower electrode and an upper electrode are relatively positionally deviated from each other through a capacitance film in a direction perpendicular to the laminating direction thereof. Thus, the upper electrode and the lower electrode each have portions opposed to each other through the capacitance film in the laminating direction and portions not opposed to each other. An upper electrode plug is connected to the portion of the upper electrode not opposed to the lower electrode through an upper electrode contact hole passing through an insulating film formed on the upper electrode. Further, a lower electrode plug is connected to the portion of the lower electrode not opposed to the upper electrode through a lower electrode contact hole passing through the insulating film.

Abstract: A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern.

Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Abstract: An epitaxial layer is formed in a main surface of a semiconductor substrate of a first conductivity type. The epitaxial layer is partitioned into a first area and a second area by a device isolation area. A PN junction portion, which has a semiconductor layer of a second conductivity type and configures a variable capacitance element, is provided at the surface of the epitaxial layer of the first area. A PN junction portion, which has a semiconductor layer of the second conductivity type whose low portion is formed closer to the semiconductor substrate than the semiconductor layer of the second conductivity type configuring the above variable capacitive PN junction and which is configured as a fixed capacitance, is provided at the surface of the epitaxial layer of the second area.

Abstract: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer.

Abstract: Single-sided polishing of semiconductor wafers provided with a relaxed Si1-xGex layer involves polishing of a multiplicity of wafers in a plurality of polishing runs, a polishing run having at least one polishing step, at least one of the multiplicity of wafers obtained with a polished Si1-xGex layer at the end of each polishing run; moving the wafer during the polishing step over a rotating polishing plate provided with a polishing cloth while applying polishing pressure, and supplying polishing agent between the polishing cloth and the semiconductor wafer, the polishing agent containing an alkaline component and a component that dissolves germanium. Semiconductor wafer having a Si1-xGex layer substantially free of defects and haze is produced.

Abstract: It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate.

Abstract: A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance.

Abstract: A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <11 00> family of directions. For a <11 20> off-cut substrate, a laser diode cavity (207) may be oriented along the <1 100> direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <11 00> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract: A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound.

Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Abstract: A semiconductor device package (10) with a substantially rectangular shape comprising: a die attach pad (12) having a top surface and a bottom surface; a plurality of contact pads (26i-26n) provided in at least four rows that correspond to the rectangular shape of the package, each contact pad having a top surface and a bottom surface; at least two tie bars (18) for supporting the die attach pad until the singulation of the package during manufacturing thereof the tie bars having a top surface and a bottom surface and extending from the die attach pad towards a corner of the package; —a semiconductor die (20) mounted on the top surface of the die attach pad (12) and having bonding pads (44) formed thereon; a plurality of electrical connections between selected ones of the bond pads (44) and corresponding ones of the contact pads (26i-26n); an encapsulation encapsulating the semiconductor die (20), the top surface of the die attach pad (12), the electrical connections, the top surface of the tie bars (18) and

Abstract: A semiconductor package using copper wires and a wire bonding method for the same are proposed. The package includes a carrier having fingers and a chip mounted on the carrier. The method includes implanting stud bumps on the fingers of the carrier and electrically connecting the chip and the carrier by copper wires with one ends of the copper wires being bonded to bond pads of the chip and the other ends of the copper wires being bonded to the stud bumps on the carrier. The implanted stud bumps on the carrier improve bondability of the copper wires to the carrier and thus prevent stitch lift. With good bonding, residues of copper wires left behind after a bonding process have even tail ends and uniform tail length to enable fabrication of solder balls of uniform size, thereby eliminating a conventional step of implanting stud bumps on the bond pads of chips and preventing ball lift from occurring.

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.