Abstract: The present invention provides methods for producing conifer cotyledonary somatic embryos. The methods of the present invention each includes the step of culturing embryogenic conifer tissue in, or on, a development medium for a period of time sufficient to produce conifer cotyledonary somatic embryos from the embryogenic conifer tissue, wherein the volume of development medium is in the range of from about 35 ml to about 50 ml per 0.5 mL of embryogenic conifer tissue.

Abstract: The present invention pertains to methods for preventing reovirus recognition in the treatment of cellular proliferative disorders, and particularly ras-mediated cellular proliferative disorders, in mammals. The method comprises suppressing or otherwise inhibiting the immune system of the mammal and, concurrently or subsequently, administering to the proliferating cells an effective amount of one or more reoviruses under conditions which result in substantial lysis of the proliferating cells. The methods may include the selective removal of immune constituents that may interfere with the systemic delivery of the virus; preventing reovirus recognition by the host immune system; and removal of the virus from an immune suppressed or immune incompetent host following treatment with reovirus. Alternatively, reovirus may be administered to a mammal with a diminished immune response system under conditions which result in substantial lysis of the proliferating cells.

Abstract: In order to ensure optimum metering of a reagent to be metered into an exhaust gas during operation of a metering unit of a catalytic converter of a combustion system, in particular an internal combustion engine of a motor vehicle, in any operating state of the catalytic converter and/or in any operating state of the combustion system, a method and a device for operating a metering unit of a catalytic converter of a combustion system provide that, based on a steady-state value of the reagent quantity to be metered during a steady-state operating state of the catalytic converter and/or the combustion system, the quantity of the at least one reagent is determined and adjusted using at least one dynamic correction factor which is dependent on at least one of the performance characteristics of the catalytic converter and on at least one of the performance characteristics of the combustion system.

Abstract: A system and method for sorting of objects that includes a pathway network that has a plurality of pathways and one or more branch points. A fluid composition including one or more objects can be transported through the pathway network, where one or more of the objects are analyzed and sorted at one or more branch points based on the analysis of the objects.

Abstract: The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or detection of particles, such as cells and/or beads. The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or analysis of particles, such as cells, viruses, organelles, beads, and/or vesicles. The invention also provides microfluidic mechanisms for carrying out these manipulations and analyses. These mechanisms may enable controlled input, movement/positioning, retention/localization, treatment, measurement, release, and/or output of particles. Furthermore, these mechanisms may be combined in any suitable order and/or employed for any suitable number of times within a system.

Abstract: The present invention relates to an automatable method for the improved diagnosis of pathologically altered cells by simultaneously staining at least two different molecular markers, which exhibit a change in gene expression which is disease-associated, in a cell or constituent regions of a tissue sample by means of using combinations of antibodies and accrediting signal intensities.

Abstract: Methods and systems for the concentration and removal of metal ions from aqueous solutions are described, comprising treating the aqueous solutions with photoswitchable ionophores.

Abstract: The present invention relates to a method for processing a waste high-pressure fluid, which is yielded by bringing a high-pressure fluid into contact with a processing object in a high-pressure processing vessel to make unnecessary materials on the processing object accompany it. In accordance with the present invention, a novel processing method is provided which includes the steps of draining liquid ingredients, which is obtained from a preliminarily refined waste medium-pressure fluid, having been decompressed from the waste high-pressure fluid and provided to a separating means filled with packing materials, out of a system with unnecessary materials, and refining gas ingredients, which is also obtained from the preliminarily refined waste medium-pressure fluid, in an adsorbing means including adsorbents.

Abstract: Methods and compositions are provided for forming complexes between dsDNA and novel DNA-binding polymers comprising N-terminal thiophene-containing moieties which exhibit selectivity for T-A base pairs. By appropriate choice of target sequences and DNA-binding polymers, complexes comprising polymer-DNA are obtained with high association constants. The formation of complexes can be used for identification of specific dsDNA sequences, for inhibiting gene transcription, and as a therapeutic for inhibiting proliferation of undesired cells or modulation of expression of specific genes.

Abstract: A method for determining the risk of an individual of suffering from inflammation, opportunistic infection or disruption of immunoglobulin metabolism, comprising (a) determining the level of fragmentation or modification of Fc function of immunoglobulins in a sample taken from the individual and (b) determining thereby the risk of inflammation, impaired immune response or opportunistic infection. The invention also provides the use of a trypsin inhibitor in the manufacture of a medicament for use in the treatment or prevention of a disorder associated with elevated trypsin activity which is correlated with IgG fragmentation or modification.

Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser-reactive marking material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser-reactive marking material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.

Abstract: Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding the core die and at least one additional die from the die cluster to a weighted character map, and assigning a weighting value to each of the dice added to the weighted character map. At least one tier of buffer dice is then added to the weighted character map adjacent to each die on the weighted character map. Both the dice from the die cluster and the tier of buffer dice are marked, thereby preventing those dice from being packaged and consequently, shipped to customers.

Abstract: A method of making a monitoring pattern to measure a depth and profile of a shallow trench isolation is disclosed. An example method of making a monitoring pattern of a shallow trench isolation profile forms a first pattern on a substrate to monitor a depth of a first shallow trench isolation. In the example method, the first pattern includes a plurality of unequally spaced active regions on the substrate. The example method also forms a second pattern on the substrate to measure electrical effects associated with a depth and a profile of a second shallow trench isolation. In the example method, the second pattern includes a plurality of equally spaced active regions on the substrate and a plurality of contact regions that electrically connect the equally spaced active regions.

Abstract: Composition of carbon nanotubes (CNTs) are produced into inks that are dispensable via printing or stencil printing processes. The CNT ink is dispensed into wells formed in a cathode structure through a stencil.

Abstract: There are provided a surface emitting device and a projection display device, in which high power output can be produced by configuring a large-scaled LED. The surface emitting device includes a plurality of stacked light emitting elements provided on one module. Each of the stacked light emitting elements includes n-type layers, light emitting layers and p-type layers, which are formed in sequence.

Abstract: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations are filled with a liquid optically transparent material, such as silicone, which when cured forms a lens material. The shape of the indentations will be the shape of the lens. The mold and the LED dice/support structure are brought together so that each LED die resides within the liquid silicone in an associated indentation. The mold is then heated to cure (harden) the silicone. The mold and the support structure are then separated, leaving a complete silicone lens over each LED die. This over molding process may be repeated with different molds to create concentric shells of lenses. Each concentric lens may have a different property, such as containing a phosphor.

Abstract: A method of manufacturing an organic electroluminescent device, which, on a substrate, has a plurality of first electrodes, a light-emitting functional layer disposed to correspond to formation positions of the first electrodes, and a second electrode covering the light-emitting functional layer, includes forming a buffering layer that covers the second electrode, and forming a gas barrier layer that covers the buffering layer. The forming of the buffering layer includes coating a coating material having a monomer/oligomer material and a curing agent under a vacuum atmosphere, without a solvent, and thermally curing the coating material so as to form the buffering layer.

Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.

Abstract: A gallium nitride-based compound semiconductor light-emitting device which includes an n-type semiconductor layer of a gallium nitride-based compound semiconductor, a light-emitting layer of a gallium nitride-based compound semiconductor and a p-type semiconductor layer of a gallium nitride-based compound semiconductor formed on a substrate in this order, and has a negative electrode and a positive electrode provided on the n-type semiconductor layer and the p-type semiconductor layer, respectively; wherein the negative electrode includes a bonding pad layer and a contact metal layer which is in contact with the n-type semiconductor layer, and the contact metal layer is composed of Cr or a Cr alloy and formed through sputtering.

Abstract: The present invention provides a process for manufacturing an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer of material located over the actuator, movable feature and sacrificial material. The process may further include removing only a portion of the layer of material to expose the sacrificial material, and subjecting the exposed sacrificial material to an etchant to release the movable feature.

Abstract: To provide a back-illuminated solid-state imaging device able to suppress a crystal defect caused by a metal contamination in a process and to suppress a dark current to improve quantum efficiency, a camera including the same and a method of producing the same, having the steps of forming a structure including a substrate, a first conductive type epitaxial layer and a first conductive type impurity layer, the first conductive type epitaxial layer being formed on the substrate to have a first impurity concentration, and the first conductive type impurity layer being formed in a boundary region to have a second impurity concentration higher than the first impurity concentration of the epitaxial layer; forming a second conductive type region storing a charge generated by a photoelectric conversion in the epitaxial layer; forming an interconnection layer on the epitaxial layer; and removing the substrate.

Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

Abstract: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through isotropic etching. Etching is carried out at this time by an amount within a range of 140% to 200% of the film thickness of the second gate electrode. Next, a normal inter-layer insulating film and light-shielding film are formed. It is possible to eliminate the overlap between the gate electrodes adjacent to an opening of the light-shielding film, suppress the height of the light-shielding film at that portion, reduce shading for the light condensed by a lens and thereby improve the light condensing efficiency of the lens.

Abstract: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.

Abstract: Method of making an organic flexible integrated circuit includes providing a rigid substrate, such as a silicon wafer, and providing alternating layers of thin film conductors and dielectrics to thus yield interconnect layers including a flexible substrate on the rigid substrate to yield a high density interconnect. Further, the method includes fabricating an organic transistor, and connecting the organic transistor to the high density interconnect to form an organic integrated circuit including the flexible substrate. Then, the rigid substrate and the flexible substrate may be attached to a support. The integrated circuit attached to the rigid and flexible substrates may be tested prior to this attachment. Then the rigid substrate may be removed from the flexible substrate, such as by a destructive. The integrated circuit may be tested gain at this point. The organic integrated circuit may then be released from the support to yield a flexible integrated circuit.

Abstract: A semiconductor package comprises a substrate which includes a plurality of conducting traces and upper contact areas on its upper surface and a second plurality of lower conductive traces and external contact areas on its bottom surface and external conducting members attached to the external contact areas. The semiconductor package also includes a semiconductor die comprising an active surface with a plurality of die contact pads, electrically connected to the contact areas of the substrate by conducting members. A support layer between the conducting members on the active surface of the semiconductor die covers at least the base portion of the conducting members. A method relates to the production of the semiconductor package.

Abstract: Methods and apparatuses for an electronic assembly. The method comprises depositing a functional block into a recessed region, forming dielectric layer selectively over at least one of a selected portion of the functional block and a selected portion of the first substrate; and forming one or more electrical interconnections to the functional block. The recessed region is formed on a first substrate. The depositing of the functional block occurs on a continuous web line and using a Fluidic Self Assembly process. The functional block has a width-depth aspect ratio that substantially matches a width-depth aspect ratio of said recessed region which is one of equal to or less than 10.5:1, and equal to or less than 7.5:1.

Abstract: In a method for manufacturing a semiconductor device, either a nickel layer or a nickel-based metal layer is formed on a semiconductor substrate by using a plating process. Then, either the nickel layer or the nickel-based metal layer is washed with one of an aqueous hydrochloric acid solution and an aqueous sulfuric acid solution.

Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).

Abstract: Semiconductor device includes a pair of substrates (1, 2) disposed oppositely, semiconductor elements (5, 6) formed in the substrates (1, 2), respectively, and having semiconductor circuits (3, 4) and electrodes (7, 8), respectively, a wiring conductor (9) interposed between the electrodes (7, 8), and a through electrode (12) extending through one substrate (1) and connected to the electrode (7) via the wiring conductor (9). The other substrate (2) is disposed laterally of the through electrode (12). Surface of the through electrode (12) projecting from the one substrate (1) and lateral surface of the element (6) are coated with an insulation material (13). The through electrode (12) has one end exposed in a back surface of the one substrate (1), while other end is positioned flush with a back surface of the other substrate (2), being exposed.

Abstract: Provided is a method for producing a semiconductor chip, comprising applying a photothermal conversion layer on a light-transmitting support, provided that upon irradiation of radiation energy, the photothermal conversion layer converts the radiation energy into heat and decomposes due to the heat; laminating the semiconductor wafer and the light-transmitting support through a photocurable adhesive by placing the circuit face and the photothermal conversion layer to face each other, thereby forming a laminated body having a non-circuit face on the outside; grinding the non-circuit face of the semiconductor wafer until the semiconductor wafer reaches a desired thickness; dicing the ground semiconductor wafer from the non-circuit face side to cut it into a plurality of semiconductor chips; irradiating radiation energy from the light-transmitting support side to decompose the photothermal conversion layer, thereby causing separation into a semiconductor chips having the adhesive layer and a light-transmitting su

Abstract: A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.

Abstract: A method for manufacturing of flexible printed circuit boards is provided. The method includes the steps of: providing a tape substrate having an electrically insulating layer and an electrically conducting layer; forming a wiring pattern at the electrically conducting layer; attaching a back film on a surface of the tape substrate; and cutting the tape substrate to get a number of flexible printed circuit boards attached on the back film.

Abstract: An embedded metal heat sink for a semiconductor device and a method for manufacturing the same are described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.

Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

Abstract: There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fin. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fin. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fin. There is also a process for making a FinFET device.

Abstract: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top dielectric, and a sidewall gate is formed on a sidewall of the pillar. A source is formed proximate to an outer edge of the gate and in contact with the carbon nanotube layer. The pillar is then removed, the source area masked, and a drain is formed proximate to an inner edge of the gate and in contact with the carbon nanotube layer. The source and drain are self aligned to the gate as dictated by the placement of dielectric spacers on the inner and outer edges of the gate.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract: The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate insulating layer is formed of a filtering oxide layer having a thickness of 1 to 20 ?.

Abstract: A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.

Abstract: A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract: Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.

Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

Abstract: The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.