Abstract: A reactance is introduced into a flow path of axial currents in an induction logging tool. The reactance may be a capacitor or an inductor. A transmitter antenna is operated at a frequency defined by a cutoff frequency related to the reactance.

Abstract: A method and apparatus for determining a parameter of interest of an earth formation during drilling of a borehole. A first toroidal coil antenna induces a current along a path that includes a bottomhole assembly and the formation. A second toroidal coil antenna disposed at the drillbit and oriented at a non-zero angle to the longitudinal axis of the bottomhole assembly measures an electrical signal resulting from the current, the electrical signal being a parameter of interest of the formations.

Abstract: An apparatus for monitoring and measuring the electrical, thermal and mechanical operating parameters of high voltage power conductors. A toroidal shaped housing, which can be mounted onto an energized conductor, contains all of the necessary electrical instruments to monitor the parameters associated with the conductor. Moreover, the housing includes the processing capability to analyze disturbance and fault events based on these parameters.

Abstract: A method and apparatus for determining a location of a phase-to-earth fault on a three-phase electric line of an electric network, comprising determining, when the ratio of a fault current and load current has a first value, a first fault distance line which indicates an estimate of a distance of the fault from the measuring point in relation to an equivalent load distance, determining, when the ratio of the fault current and load current has a second value which differs from the first value, at least one second fault distance line, determining a distance at which the determined fault distance lines intersect when superimposed and determining the distance between the measuring point and the point of fault on the basis of the determined distance or distances of intersection.

Abstract: An adapter for connecting a wiring cable to be tested to a wiring analyzer. The adapter includes a body; a first set of contacts positioned on a first side of the body for electrically connecting with the wiring analyzer; and a second set of contacts positioned on a second side of the body and electrically connected to the first set of contacts for connecting with a connector on the cable to be tested. The first and second sides of the body are less than 4 inches apart so that the first set of contacts is positioned less than 4 inches from the second set of contacts. The body may include hanging structure for hanging the adapter on an interface of the wiring analyzer and a latch for securing the adapter to the interface.

Abstract: A driver for supplying a test signal to a device under test is shared by a plurality of terminals. In this way, the cost and time required for the test of the device under test can be reduced. A testing apparatus 10 relating to the present invention includes a test signal generating section 130 that generates a test signal to be supplied to a device under test 20, a driver 140 that outputs the test signal, a switch 150 that is disposed on a wire between the driver 140 and a first terminal of the device under test 20, a switch 160 that is disposed on a wire between the driver 140 and a second terminal of the device under test 20, and a connection control section 100 that (i) turns on the switch 150 and turns off the switch 160 when the test signal is supplied to the first terminal of the device under test 20, and (ii) turns off the switch 150 and turns on the switch 160 when the test signal is supplied to the second terminal of the device under test 20.

Abstract: Provided is a semiconductor device determining connection status between an output terminal connected to an output buffer and an external device, the semiconductor device including a test voltage generating circuit to generate test voltage for changing voltage of the output terminal, a connection detection determining circuit to compare voltage of the output terminal with reference voltage and to determine connection status of the external device based on the comparing result, and a compensation circuit generating simulation current where leak current generated at the output buffer is reproduced in a simulatory manner and compensating voltage change of the output terminal by the simulation current.

Abstract: New electro-electronic equipment Functional Parametric Tester and Emulator of Electronic Modules and PCB's. The Functional Parametric Tester and Emulator of Electronic Modules and PCB's is an equipment that allows performance of functional and parametric testing in a great variety of electronic circuits, electronic modules or electronic systems. The equipment's main characteristic is the programming ease and flexibility due to the embedded software with Electronic Circuit Library, which is a set of electronic circuits that allows the emulation of a great variety of electronic systems and execution of various functional automated tests.

Abstract: In one embodiment, a method for testing a differential signaling channel having a differential pair of signal paths, and a pair of signal grounds bounding the differential pair, includes: causing positive and negative phases of a differential waveform to be driven over respective paths of the differential pair while monitoring a signal induced in a capacitive sense plate positioned adjacent to, and capacitively coupled to, all of the paths and grounds of the channel; when an amplitude of the monitored signal is within a first range, indicating to a user that there are no open defects in the differential signaling channel; and when the amplitude of the monitored signal falls within one or more second ranges, and not within the first range, indicating to the user that an open exists in the differential signaling channel. Other embodiments are also disclosed.

Abstract: The present invention provides a device, test cards, methods and kits which are useful for determining the particle fraction and rate of viscosity of a fluid sample, the presence of an analyte in a fluid sample, or the aggregation of particles in a fluid sample to detect an analyte or as an immunologic assay.

Abstract: A system, apparatus, and method for dynamic measurement of inductance trend of a motor are disclosed. In one of the embodiment herein the system is configured to acquire inputs from the DUT using a Trigger system, a horizontal subsystem and the programming unit. The system is also configured to process such information for dynamic analysis and representation on an interface provided in the system based on different step sizes.

Abstract: A transceiver system and method determining a voltage standing wave ratio (VSWR) is provided. The system includes at least one amplifier, a filter bank, a plurality of detectors, and at least one processor. The at least one amplifier receives an input signal. The filter bank is in electrical communication with the at least one amplifier. The plurality of detectors are in electrical communication with the filter bank, where a first detector of the plurality of detectors is in electrical communication with a first portion of the filter bank, and a second detector of the plurality of detectors is in electrical communication with a second portion of the filter bank. The at least one processor is in electrical communication with the plurality of detectors, and estimates a VSWR based upon voltages detected by the first and second detectors.

Abstract: A method for measuring the noise factor (FDUT) of a device under test, which requires exclusively a network analyzer. The noise factor (FDUT) is calculated from the internal noise (NNWA) of the network analyzer determined in a calibration process, the power amplification (GDUT) of the device under test determined by measuring the S-parameters of the device under test, and the measured value (PNOISE) of the noise output (NNWA) applied at a first gate of the device under test without exciting the device under test with a noise signal.

Abstract: A system and related method are provided to calibrate for wire capacitance during use to minimize error in conductivity measurement of the target fluid. The system includes a signal generator configured to drive the conductivity cell and the temperature element, with an alternative current (AC) drive signal having variable parameter. The system further includes a processor assembly electrically coupled to the conductivity cell and the temperature element to calculate a conductivity value of the fluid. The conductivity value is a function of the values of the temperature measurement, the compensation measurement, and the raw conductivity measurement, thereby compensating the conductivity value for capacitance effects. In this manner, the system effectively compensates for capacitance attributable to wiring extending between the electrode and other electronics of the sensor, usable with wiring of varied and unknown lengths.

Abstract: A capacitive sensing device comprises a set of sensing elements disposed in a two-dimensional arrangement. The two-dimensional arrangement is comprised of full elements and partial elements. A plurality of the partial elements are proximate at least one edge of the two-dimensional arrangement. Additionally, a partial element of the partial elements is smaller in element area than a full element of the full elements. An edge electrode trace of the capacitive sensing device is comprised of a selectively coupled plurality of the partial elements. The selectively coupled plurality of the partial elements resides proximate a first edge of the two-dimensional arrangement.

Abstract: Apparatus and method for measuring the capacitance to ground of a conductor are disclosed. The apparatus includes at least three switching elements, a voltage measurement circuit, and a controller. Two terminals of a first switching element are connected respectively to a distal terminal of a sample capacitor and a first voltage. Two terminals of a second switching element are connected respectively to a proximal terminal of the sample capacitor and a second voltage. Two terminals of a third switching element are connected respectively to the proximal terminal and the first voltage. The proximal terminal is directly electrically connected to one conductor end. The conductor has an unknown capacitance to ground representative of an object to be sensed. The change in the capacitance of the unknown capacitance capacitor can be determined and a proximity or contact of the object can thus be sensed by using the above apparatus and method.

Abstract: The present disclosure relates to a capacitive sensor film (50) for mounting to a body. The film comprises a dielectric backing layer (2) having, on one side, a rear major surface (2a) facing, in use, the body and, on the other side, a front major surface (2b) bearing a front conductor (4) at least partly surrounding a sensor conductor (7) which is electrically isolated against the front conductor (4) by zones where the front conductor (4) is removed and the front major surface (2b) of the backing layer (2) or another layer beneath the front conductor (4) is exposed. A guard conductor (1) is provided on at least one of the major surfaces (2a, 2b) of the backing layer, to provide an electrical shield for the sensor conductor. The guard conductor may comprise the said front conductor (4).

Abstract: The invention relates to a method for servicing, especially checking, an apparatus for capacitive ascertaining and/or monitoring at least one process variable of a medium, wherein the apparatus has at least one probe unit (3) with a probe electrode (6) and an auxiliary electrode (7). The invention includes that the probe electrode (6) and/or the auxiliary electrode (7) are/is supplied at least with one test signal or connected with at least one electrical potential, that at least one response signal is tapped from the probe unit (3), and that, at least from the response signal and a predeterminable desired value, information is obtained concerning the apparatus.

Abstract: The present invention relates to a method for selectively detecting and/or measuring gaseous SO2 at a temperature of at least 500° C.

Abstract: A contacting-type conductivity sensor is provided. A first insulating layer has a proximal surface to contact a liquid sample, and an opposite, distal surface. A plurality of electrodes is disposed on the proximal surface of the first insulating layer. Each of a plurality of conductive vias is electrically coupled to a respective one of the plurality of electrodes, where each via defines a conductive path from the proximal surface to the distal surface of the first insulating layer. A plurality of traces is disposed adjacent the distal surface of the first insulating layer, and each of the plurality of traces is electrically coupled to a respective one of the plurality of conductive vias. A plurality of conductors is provided where each conductor is electrically coupled to a respective one of the plurality of traces. A cover layer is coupled to the first insulating layer.

Abstract: A device for measuring the resistivity ?c of an interface between a semiconductor and a metal, comprising at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, at least two interface portions containing the metal or an alloy of said semiconductor and said metal, each of the two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.

Abstract: A measuring bridge arrangement has a measuring bridge with a first supply terminal and first and second measuring signal terminals. The measuring bridge arrangement has a working point adjustment circuit formed to feed the measuring bridge via at least the first supply terminal in a measuring state of operation, and to apply a signal to one of the measuring signal terminals in the test state of operation in order to bring the measuring bridge to a test working point different from a measuring working point in the measuring state of operation. The measuring bridge has a test tap, wherein a test signal dependent on resistive properties of at least one element of the measuring bridge can be tapped at the test tap of the measuring bridge.

Abstract: A novel device for testing semiconductor chips is disclosed. A benefit with all the embodiments described herein is that the device may experience zero (or near zero) nascent force. The device may be comprised of a printed circuit board (PCB) that has at least one PCB piercing structure, a probe contactor substrate that has at least one substrate piercing structure, wherein the substrate piercing structure is electrically connected to a probe contactor, and an interposer that has at least one electrical via made of a conductive elastomer. When the PCB piercing structure and the substrate piercing structure pierce the elastomer, the PCB becomes electrically connected to the probe contactor. Instead of the piercing structure, the PCB or the probe contractor substrate may be adhered to the elastomer by an adhesive, such that the PCB becomes electrically connected to the probe contactor. The PCB piercing structure and the substrate piercing structure may include a flying lead wire, soldered pins or pressed pins.

Abstract: A probe card includes a flat plate-shaped wiring board, a columnar base portion, and a thee-dimensional spiral contactor. The base portion is interposed between a wiring pattern of the wiring board and the bottom of the contactor.

Abstract: The present invention provides a semiconductor test apparatus that can reduce influence of noise in high-frequency measurement and that can be manufactured inexpensively by simplification of the constitution. A semiconductor test apparatus according to the present invention is one for use in an electrical test of a semiconductor wafer in which numerous integrated circuits each having electrode pads are incorporated. It comprises a probe card and a tester having a connection portion to the probe card. The probe card has numerous probes that can be connected to the electrode pads of the semiconductor wafer and a probe board having on one surface probe lands to which the probes are attached, having on the other surface tester lands corresponding to the probes, and having wiring paths each connecting the probe land and the tester land corresponding to each other. The tester is directly connected to the probe card as the connection portion contacts the tester lands.

Abstract: A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.

Abstract: Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes.

Abstract: A location device for holding a number of probes is provided. The probes include a body, a first needle and a second needle respectively and coaxially disposed at opposite ends of the body. The location device includes a first support structure, a second support structure overlapping the first support structure and a number of through holes running through the first support structure and the second support structure. Each of the through holes includes a locating hole, a first aperture and a second aperture respectively disposed at opposite ends of and communicated with the locating hole and configured for respectively receiving the first, second needle of the probe. The first, second needle respectively extend out of the first, second aperture. The probes are clamped by the first, second support structure and located by the locating hole of the support device.

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.

Abstract: A method and device for determining the quality of the interface surface between a layer of a dielectric material and the top surface of the semiconductor substrate are disclosed. In one aspect, the method comprises providing a semiconductor substrate with a top surface whereon a layer of a dielectric material is deposited thereby forming an interface surface, the surface of the layer of the dielectric material being or not in direct contact with the semiconductor substrate defining a top surface. A charge is then applied on a dedicated area of the top surface. A voltage Vs is measured on the top surface. The dedicated area is illuminated to define an illuminated spot. The photovoltage is measured inside and outside the determined illuminated spot during the illumination of the area.

Abstract: According to an example embodiment, a semiconductor device test system includes a semiconductor device and a test apparatus. The semiconductor device includes a plurality of function blocks for performing predetermined functions at different operating speeds and a plurality of ports, each corresponding to a respective function block. The test apparatus is adapted to generate a plurality of signals with different frequencies corresponding to each of the operating speeds of the function blocks, to output a plurality of input test data to the ports in response to the signals, and to receive a plurality of output test data from the ports to determine if the semiconductor device is normal.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: A method for configuring an electronics device having reconfigurable network component layers is disclosed. The method selects a first group of pixels from at least one of the reconfigurable network component layers to form a network component on a substrate of the electronics device and activates the network component in at least one plane of the device substrate using a plurality of micro-electromechanical system (MEMS) switches adjacent to the first group of selected pixels. The method adjusts a first shape of the activated network component for the electronics device using the reconfigurable network component layers.

Abstract: A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second field effect transistors, fourth and fifth field effect transistors serially connected between the first and second power source terminals, and a sixth field effect transistor having a gate connected to the word line and used for data transfer between a second bit line and the drains of the fourth and fifth field effect transistors. The threshold voltages of the first and fourth field effect transistors are different from each other and the magnitude relation thereof is determined according to ROM data.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided.

Abstract: A two-wire transmitter for receiving power supply from an external circuit through two transmission lines and also transmitting a current signal based on the measurement value of a sensor includes a current control section to which a voltage is supplied from an external circuit, for controlling the current value of the current signal based on an electric signal responsive to the measurement value of the sensor, if current consumption of the two-wire transmitter becomes smaller than the current value of the current signal, the current control section for charging and if the current consumption becomes larger than the current value of the current signal, the current control section for discharging; a computation control section for outputting the electric signal to the current control section and also outputting a setting signal based on predetermined computation processing information; a clock supply circuit for controlling the frequency of a clock signal based on the setting signal and supplying the clock sig

Abstract: Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die device and that provides the state of all of the dice at a common output. Such a multi-die device can comprise two or more dice in a multi-die package, wherein each of said dice has a first drive parameter when indicating a first state and a second drive parameter when indicating a second state. When the first drive parameter of the two or more dice is at a value such that when one or more of said two or more dice is in the first state, said common output can indicate that all of the dice in the multi-die device are in the first state.

Abstract: A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges.

Abstract: A complex switch control system including many switches, a switching voltage control circuit and a comparator is provided. The switching voltage control circuit converts an operating voltage into a switching voltage according to the states of the switches. The comparator compares the switching voltage with a reference voltage and outputs a switch state signal to a keyboard controller. A duty cycle of the switch state signal corresponds to the states of the switches.

Abstract: In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.

Abstract: A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A switch de-bouncing device includes a majority counter that counts samples generated by a sampler sampling a switch output where a counter value is incremented for each sample indicating a first switch state and decremented for each sample indicating a second switch state of the switch. A controller determines that the switch is in the first switch state when the counter value is above a first state threshold and is in the second switch state when the counter value is below a second state threshold.

Abstract: A Bluetooth® enhanced data rate receiver (1) has a DC offset estimation circuit (9) comprising a detector (10) for identifying turning points in a demodulated signal and measuring the signal level at these turning points. The detector (10) discards measured levels of maxima that are not sufficiently different to a level of a preceding minimum and levels of minima that are not sufficiently different to a level of a preceding maximum. The detector (10) also discards levels that are smaller than certain thresholds. An averaging means (11) calculates the average of each adjacent maximum and minimum levels of the signal output by the detector (10). A processing means (12) selects a high, low and medium value of the calculated averages and estimates a DC offset value as the average of this set of calculated averages.

Abstract: A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives a clock signal as a trigger signal, performs a sequential logic operation based on the clock signal, and outputs a result of the sequential logic operation. The second logic circuit is coupled to the first logic circuit. The second logic circuit performs a combinational logic operation based on the output of the first logic circuit and outputs a result of the combinational logic operation as a converted signal. The converted signal has the same waveform and frequency as those of the clock signal, and the phases of the clock signal and the converted signal are the same or only slightly different.

Abstract: A process inserts a random noise in a Time to Digital Converter (TDC) designed for calculating the phase error between a first high frequency signal FDCO with respect to a second reference signal, switching at a lower frequency.

Abstract: Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. The present invention advantageously provides for a frequency divider structure that can be easily programmed to provide any integer divide ratio with a 50% duty cycle.