Patents Issued in December 4, 2008
  • Publication number: 20080297210
    Abstract: A clock multiplier includes a phase-frequency detector, a voltage-current converter, a duty ratio control circuit, a plurality of variable delay cells and an edge combiner. The phase-frequency detector generates control signals. The voltage-current converter converts the control signals to generate first and second current control voltages. The duty ratio control circuit modifies the duty ratio of an input clock signal based on the first and second current control voltages. Each of the variable delay cells generates a triangular wave voltage based on the modified input signal, generates a square wave voltage based on the triangular wave voltage to generate a delay signal. The edge combiner generates a plurality of multiplied clocks based on the delay signals from the variable delay cells.
    Type: Application
    Filed: August 15, 2007
    Publication date: December 4, 2008
    Inventor: Woo-Seok Kim
  • Publication number: 20080297211
    Abstract: An operation mode setting apparatus includes an operation mode setting control unit that discriminates the phase of a reference clock from the phase of a feedback clock and generates a locking suspension signal, and an operation mode setting unit that generates a locking completion signal in response to a pulse signal and a phase comparison signal under the control of a reset signal and the locking suspension signal.
    Type: Application
    Filed: December 20, 2007
    Publication date: December 4, 2008
    Applicant: HYNIX SEMINCONDUCTOR, INC.
    Inventor: Seok Bo Shim
  • Publication number: 20080297212
    Abstract: A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit, the startup circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit having a low voltage terminal; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and a second terminal, the dropping resistor dropping the high voltage DC bus voltage to a reduced voltage and providing the reduced voltage at the second terminal; further comprising a low voltage regulator coupled to the second terminal for using the reduced voltage for enabling generation of a regulated startup low voltage DC output at a preset level at the low voltage terminal for powering at least one part of the application circuit during startup of the application circuit, wherein the high voltage DC bus voltage is the only voltage source provided externally to the integrated circuit package.
    Type: Application
    Filed: August 13, 2008
    Publication date: December 4, 2008
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Massimo Grasso, Sergio Morini
  • Publication number: 20080297213
    Abstract: A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Inventors: Aliazam Abbasfar, Amir Amirkhany, Bruno W. Garlepp
  • Publication number: 20080297214
    Abstract: A delay locked loop (DLL) architecture includes a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.
    Type: Application
    Filed: June 29, 2007
    Publication date: December 4, 2008
    Inventor: Sri Navaneethakrishnan Easwaran
  • Publication number: 20080297215
    Abstract: A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to delay an external clock signal to produce a substantially in-phase output clock signal, a main loop configured to control delay through the delay line, and a secondary loop configured to adjust delay through the main loop. The clock synchronization method generally includes adjusting a delay along a delay line in response to a first phase difference between an input clock to the delay line and a shared clock signal delayed by a shared dynamic I/O model of an output driver. The method further includes adjusting the shared dynamic I/O model in response to a second phase difference between an output clock signal and the shared clock signal.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Yantao Ma
  • Publication number: 20080297216
    Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 4, 2008
    Inventors: Meei-Ling Chiang, Dwight K. Elvey, Sanjeev Maheshwari, Emerson S. Fang
  • Publication number: 20080297217
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 4, 2008
    Inventors: David R. Welland, Donald A. Kerth, Caiyi Wang
  • Publication number: 20080297218
    Abstract: An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
    Type: Application
    Filed: July 28, 2008
    Publication date: December 4, 2008
    Inventors: Jody Greenberg, Sehat Sutardja
  • Publication number: 20080297219
    Abstract: Equal delay flip-flop systems and complementary input complementary output equal delay flip-flop circuits are disclosed. In one embodiment, an equal delay flip-flop system includes a first delay flip-flop for processing a first input, including a first tri-state input driver for driving the first input, a first master latch for sampling and/or forwarding the first input, a first transmission gate for relaying the first input forwarded by the first master latch, and a first slave latch for storing and/or forwarding the first input. The equal delay flip-flop system further includes a second delay flip-flop for processing a second input, including a second tri-state input driver for driving the second input, a second master latch for sampling and/or forwarding the second input, a second transmission gate for relaying the second input forwarded by the second master latch, and a second slave latch for storing and/or forwarding the second input.
    Type: Application
    Filed: April 23, 2008
    Publication date: December 4, 2008
    Inventors: SUJAN MANOHAR, Pavan Vithal Torvi
  • Publication number: 20080297220
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: May 19, 2008
    Publication date: December 4, 2008
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Publication number: 20080297221
    Abstract: A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tatsuaki Denda, Kazuhiro Kobayashi
  • Publication number: 20080297222
    Abstract: Spurious noise that occurs in the vicinity of a carrier can be removed even when a high-resolution cycle is set, thereby realizing low jitters in a high-precision variable clock signal. Cycle data that is set by a pattern generator 10 in a waveform generation apparatus (a semiconductor test apparatus) 1 is corrected in such a manner that spurious noise that occurs in a carrier of a high-precision variable clock is produced at a position far from the carrier. As a result, the spurious noise can be assuredly removed by a PLL 50, thereby realizing low jitters in the high-precision variable clock signal.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 4, 2008
    Inventor: Kenji Tamura
  • Publication number: 20080297223
    Abstract: A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.
    Type: Application
    Filed: May 1, 2008
    Publication date: December 4, 2008
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Mathias Duppils, Min Fang
  • Publication number: 20080297224
    Abstract: An aspect of the present invention minimizes static current consumption in an output block which receives a lower strength input signal and drives a corresponding output signal with a higher strength. Such a feature may be obtained while ensuring that no closed path exists between a first and second reference potentials (having voltage levels equaling upper and lower limits of the swing of the output signal) used by a circuit portion driving a pair of transistors operating as an inverter in the output block. In one embodiment, such a closed path is avoided during the steady state of the output signal, while in an alternative embodiment, the closed path is avoided during the transitions as well.
    Type: Application
    Filed: May 15, 2008
    Publication date: December 4, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Karthik Rajagopal
  • Publication number: 20080297225
    Abstract: A logarithmic amplifier is configured to produce a logarithmic output signal that is an logarithmic function of an input signal. The amplifier comprises a reference signal, first and second function generators, and a low-pass filter. The first function generator is configured to produce a periodic exponential waveform from the reference signal based upon a resistor-capacitor time constant, wherein the exponential waveform exponentially increases from a minimum value to a maximum value in each period. The second function generator is configured to produce a pulsed waveform from the exponential waveform, wherein the pulsed waveform has a signal period, and wherein the pulsed waveform comprises a first portion having a first amplitude for a first time period and a second portion having a different amplitude for the remainder of the signal period, and wherein the duration of the first time period is determined in response to the exponential waveform.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Applicant: HONEYWELL INTERNATIONAL, INC.
    Inventor: Scot Olson
  • Publication number: 20080297226
    Abstract: A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John C. Kriz, Antonio M. Marques, Bernard L. Morris
  • Publication number: 20080297227
    Abstract: An integrated circuit system comprising: forming an analog switch including: providing a current source for driving the analog switch, coupling a first source follower to the current source for forming a first input to the analog switch, coupling a second source follower to the current source for forming a second input to the analog switch, and coupling a switch to the first source follower and the second source follower for selecting the first input, the second input, or a combination thereof; and selecting a voltage output signal from the first source follower, the second source follower, or a combination thereof including isolating the first input from the second input.
    Type: Application
    Filed: March 7, 2008
    Publication date: December 4, 2008
    Applicant: MICREL, INC.
    Inventor: Philip W. Yee
  • Publication number: 20080297228
    Abstract: A temperature sensing circuit using a delay locked loop and a temperature sensing method. The temperature sensing circuit includes a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature. A variable delay unit may have a chain structure of a plurality of delay cells depending upon temperature. The variable delay unit may receive the external clock and generate variable delay pulses having respectively different delay amounts based on temperature. A decision control unit is configured to sense a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. Accordingly, an unnecessary time and cost causable by temperature compensation can be reduced, and an automatic temperature compensation and a precise temperature sensing operation can be obtained.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jin-Gook KIM
  • Publication number: 20080297229
    Abstract: A CMOS voltage reference circuit for a low voltage (1v), low power supply application is described. The circuit achieves a temperature coefficient of 31 ppm for a relatively large temperature range of ?40 C to 125 C. A combination of subthreshold current characteristics and moderate inversion operation of MOSFET's are utilized in conjunction to achieve a fairly stable temperature independent output voltage reference (VREF) from the circuit.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventor: Navin Kumar Ramamoorthy
  • Publication number: 20080297230
    Abstract: This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.
    Type: Application
    Filed: February 4, 2008
    Publication date: December 4, 2008
    Inventors: Andrew Steven Dzurak, Sobhath Ramesh Ekanayake, Robert Graham Clark, Torsten Lehmann
  • Publication number: 20080297231
    Abstract: Apparatus (40) comprising a multistage charge pump (10) having an output (41) for connecting a load (Cout, KL). The charge pump (10) comprises m gain stages for charging and discharging m external stage capacitors (C) in order to provide an output voltage (Vout) at the output (41) that is about m times higher than a supply voltage (Vdd) of the charge pump (10). The charging and discharging is influenced by switches inside said charge pump (10) that are controlled by a switching signal having a switching frequency (fosc). A monitoring circuit (20) is provided that monitors temperature-induced changes of the value of an external reference capacitor (Cref). Furthermore, means (30) for adjusting the switching frequency (fosc) are employed in order to compensate variations of the gain of said charge pump (10) that are caused by the changes of the value of the m external stage capacitors (C).
    Type: Application
    Filed: December 22, 2005
    Publication date: December 4, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Friedbert Riedel
  • Publication number: 20080297232
    Abstract: The invention provides a charge pump circuit which reduces rise time of an output current even when an input signal is of high frequency. PMOS1 and PMOS2 have gates connected to each other, and the gate of the PMOS1 is connected to the drain thereof. A supply potential (Vdd) is applied to the sources of the PMOS1 and the PMOS2, and the PMOS1 and the PMOS2 form a current mirror circuit. First and second switching elements and a first constant-current source are connected to the drain of the PMOS2. A connection point (a node) of the first switching element and the second switching element is connected to an output terminal. The drain of the PMOS1 is connected to the first constant-current source through a third switching element, and connected to a second constant-current source through a fourth switching element.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 4, 2008
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Tsuyoshi Yoshimura, Taichiro Kawai
  • Publication number: 20080297233
    Abstract: A semiconductor integrated circuit having an internal circuit group, which includes at least one internal circuit, includes a plurality of process monitoring circuits, each of which is disposed at a different location in the internal circuit group, each of the process monitoring circuits, which is operated in response to a power supply voltage, detecting monitoring data in the area where one of the process monitoring circuits is disposed, and a power supply voltage generating circuit generating the power supply voltage corresponding to the monitoring data, and supplying the power supply voltage to the internal circuit group.
    Type: Application
    Filed: March 19, 2008
    Publication date: December 4, 2008
    Inventor: Yasuhiro Tokunaga
  • Publication number: 20080297234
    Abstract: A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jorgen Moholt, Per Olaf Pahr, Tore Martinussen
  • Publication number: 20080297235
    Abstract: A voltage controller for controlling an output voltage to a predetermined value. The voltage controller has a first terminal configured to connect a supply voltage, a second terminal configured to output the output voltage, a control voltage generating unit configured to provide a control voltage, and a control transistor. The control transistor is connected as a series controller between the first terminal and the second terminal. The control voltage can be applied to the control terminal of the control transistor, wherein the output voltage is controlled in a manner dependent on the supply voltage and the control voltage. Furthermore, an offset voltage is superposed on the control voltage.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: DIRK HAMMERSCHMIDT, MARIO MOTZ
  • Publication number: 20080297236
    Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 4, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takashi OHSAWA
  • Publication number: 20080297237
    Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 4, 2008
    Applicant: SYNOPSYS, INC.
    Inventors: Victor Moroz, Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin
  • Publication number: 20080297238
    Abstract: A current source circuit is provided. The circuit includes a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage. A second source/drain terminal of the first transistor is used to receive a current signal, and the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of the second transistor is grounded. A second source/drain terminal of the second transistor is coupled to a voltage source and outputs a bias current. A gate terminal of the second transistor is coupled to the gate terminal of the first transistor.
    Type: Application
    Filed: January 30, 2008
    Publication date: December 4, 2008
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Ming-Dou Ker, Jung-Sheng Chen, Chun-Yuan Hsu
  • Publication number: 20080297239
    Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Inventors: Hassan Elwan, Amr Fahim, Edward Youssounan, Ahmed A. Emira, Dejun Wang
  • Publication number: 20080297240
    Abstract: A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 4, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki Kondo, Masaru Sawada, Norio Murakami, Syoichi Masui
  • Publication number: 20080297241
    Abstract: An application-specific integrated circuit (CS) comprises a first analog stage (E1), comprising first filtering means (C11-C2M, R11-R2P) responsible for carrying out a filtering of the high-pass type on an input signal (SE) so as to deliver an intermediate signal (SI), and a second digital stage (E2), comprising second filtering means (M2) capable of introducing various first time constants depending on combinations of coefficient values and responsible for correcting any distortion potentially present in the intermediate signal (SI). The first filtering means comprise an assembly of electronic components configured in parallel and/or in series and capable of introducing various second time constants depending on their combination.
    Type: Application
    Filed: November 6, 2007
    Publication date: December 4, 2008
    Applicant: SIEMENS VDO AUTOMOTIVE
    Inventors: Alain Ramond, Simon-Didier Venzal, Michel Suquet
  • Publication number: 20080297242
    Abstract: An integrated circuit includes a monitor node adapted to receive a monitored signal. The integrated circuit also includes a multi-purpose node. The integrated circuit is adapted to receive and store a threshold presented at the multi-purpose node during a first time period. The integrated circuit is also adapted to output a fault signal from the multi-purpose node at a time after the predetermined time period. The fault signal is indicative of a relationship between the monitored signal and the threshold. With this arrangement, the multi-purpose node achieves at least two functions.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Inventors: Ravi Vig, John Cummings, Jonathan Lamarre, David J. Haas
  • Publication number: 20080297243
    Abstract: A linear programmable switch-capacitance gain amplifier (PGA) is described. The PGA divides the dB-gain curve into several parts by the concept of piece-wise linearity, and then simultaneously executes the dB-linear gain adjustment of MSB and the LSB at the same gain stage. Present invention achieves the PGA dB-linearity by setting up every capacitance of the sampling capacitor array and the holding capacitor array, then arranging the sampling capacitor array and the holding capacitor array by coordinating the switching of the capacitor switches.
    Type: Application
    Filed: January 23, 2008
    Publication date: December 4, 2008
    Inventor: Yi-Chen Chen
  • Publication number: 20080297244
    Abstract: One embodiment of an apparatus for filtering an electrical signal includes a loop filter with an input and an output that applies a transfer function to a signal at the input. The transfer function has substantially no real part. The loop filter has a dominant pole placed substantially at or above an upper frequency in the frequency range of interest for the loop filter.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Soeren Poulsen, Lars Risbo
  • Publication number: 20080297245
    Abstract: A circuit for pre-distorting a signal input to an amplifier includes a signal divider operable for dividing an input signal into signal portions that travel in a primary path and a secondary path. A delay element in each of the primary and secondary paths introduces a group delay to the signal portions in the respective paths. A signal combiner is operable for combining the signals in the respective paths into a combined output signal. A variable gain circuit is arranged in each of the primary and secondary paths. The variable gain circuit is operable to vary the level of the input signal in each path and thereby modulate the overall phase delay of the combined output signal.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Applicant: ANDREW CORPORATION
    Inventor: Jim A. Bingham
  • Publication number: 20080297246
    Abstract: An amplifier circuit receives a phase modulated signal at an input node. The power supply terminal of the amplifier circuit is modulated in accordance with an amplitude envelope signal. The voltage on the power supply terminal is modulated using one or more linear regulators depending on the magnitude of the envelope signal.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventor: Stewart S. Taylor
  • Publication number: 20080297247
    Abstract: A method of reducing distortion in the output of an amplifier is provided. The method comprises subtractively combining an error signals with the appropriate phase shift with input signals to be amplified. The error signal being generated by subtractively combining a fed-forward portion of the input signal with a portion of the fed-back amplified output signal, and signal processing applied to it between its generation and application to correcting the input signal in the baseband domain. The error therefore being down-converted, filtered, and up-converted in the feedback path. The filtered baseband error signal components providing inputs to a controller which adjusts active elements of the amplification and feedback path in order to minimize the distortion within the output of the amplifier.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Applicant: SiGe Semiconductor Inc.
    Inventors: Gordon G. Rabjohn, Johan Grundlingh
  • Publication number: 20080297248
    Abstract: A Class D amplifier circuit in accordance with an embodiment of the present application includes a converter stage operable to provide a desired AC voltage and a Class D amplifier stage, connected to the converter stage. The Class D amplifier stage includes a first bi-directional switch connected to the converter stage, a second bi-directional switch, connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected across the desired AC voltage provided by the converter stage and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at a midpoint node positioned between the first bi-directional switch and the second bi-directional switch.
    Type: Application
    Filed: May 9, 2008
    Publication date: December 4, 2008
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Jun Honda
  • Publication number: 20080297249
    Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.
    Type: Application
    Filed: July 21, 2008
    Publication date: December 4, 2008
    Inventors: Leonard Forbes, David R. Cuthbert
  • Publication number: 20080297250
    Abstract: An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor.
    Type: Application
    Filed: April 25, 2008
    Publication date: December 4, 2008
    Applicant: MICREL, INC.
    Inventor: Philip W. Yee
  • Publication number: 20080297251
    Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 4, 2008
    Applicant: Broadcom Corporation
    Inventors: Namik Kemal Kocaman, Afshin Momtaz
  • Publication number: 20080297252
    Abstract: A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage.
    Type: Application
    Filed: November 5, 2007
    Publication date: December 4, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Toshihide Oka, Masaaki Shimada
  • Publication number: 20080297253
    Abstract: An electrical apparatus comprising an amplifier having a first input, a second input, and an output. The apparatus further comprises a first electrical path coupled to the first input and having a first resistance and a first electrical path coupled to the second input and having a second resistance. The apparatus further comprises a second electrical path coupled to the second input and having a third resistance and a second electrical path, comprising an electrically-controllable resistance, coupled between the output and the first input. Further, the apparatus comprises circuitry for controlling the electrically-controllable resistance for adjusting a ratio between the electrically-controllable resistance and the third resistance to approximate a ratio between the first resistance and the second resistance.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qunying Li, Juergen Luebbe
  • Publication number: 20080297254
    Abstract: A class AB amplifier includes: a voltage amplifier stage operating off a first source voltage, and amplifying a differential input voltage to produce a first amplified voltage; a level shift stage coupled to the voltage amplifier stage and adjusting a direct current level of the first amplified voltage to produce a first shift voltage; and a power amplifier stage coupled to the level shift stage, operating off a second source voltage, and converting the first shift voltage to produce a first output current. The second source voltage is larger than the first source voltage.
    Type: Application
    Filed: May 23, 2008
    Publication date: December 4, 2008
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Wien-Hua CHANG
  • Publication number: 20080297255
    Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a, 12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising a circuit (54) for compensating a series input impedance of the amplifier (31-34).
    Type: Application
    Filed: January 30, 2006
    Publication date: December 4, 2008
    Applicant: NXP B.V.
    Inventors: Edwin Van Der Heijden, Hugo Veenstra
  • Publication number: 20080297256
    Abstract: An RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power detection channel and the instantaneous/peak power detection channel of the RF detector. A method of RF detection includes providing representations of the RF input signal at different gain levels, selecting one or more of the representations, and averaging the selected signals. The gain levels of the selected representations is adjusted to provide information about the average power level of the RF input signal.
    Type: Application
    Filed: May 14, 2008
    Publication date: December 4, 2008
    Inventors: Yalcin Alper Eken, Peter Katzin
  • Publication number: 20080297257
    Abstract: The amplifier comprises an inverting negative feedback amplifier circuit using an operational amplifier, a comparator for comparing the potential of the negative phase input terminal of the operational amplifier with the reference potential Vref of the comparator, and a low-pass filter. The imaginary short state of the operational amplifier is lost when clipping occurs on the output signal. It is thus possible to detect clipping by monitoring the potential of the negative phase input terminal.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Yamaha Corporation
    Inventor: Masayuki Iwamatsu
  • Publication number: 20080297258
    Abstract: A first transistor includes: a first terminal that receives one of differential input signals; a second terminal that receives a control signal for varying an impedance; a third terminal connected to the second transistor; and a fourth terminal that supplies a potential to a substrate. A second transistor includes: a fifth terminal that receives the other of the differential input signals; a sixth terminal that receives a control signal, the seventh terminal connected to the first transistor, and the eighth terminal that supplies a potential to a substrate. The third terminal, the fourth terminal, the seventh terminal, and the eighth terminal are connected together.
    Type: Application
    Filed: May 23, 2008
    Publication date: December 4, 2008
    Inventors: Tomohiro Naito, Toru Dan
  • Publication number: 20080297259
    Abstract: A configurable LNA architecture for a multi-band RF receiver front end comprises a bank of LNAs, each optimized to a different frequency band, wherein each LNA has a configurable topology. Each LNA comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor presents a real resistance at inputs of the LNAs, without introducing thermal noise.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventor: Fenghao Mu