Abstract: A method of fabricating an organic EL device by which sealing films can be patterned, without using any wet process. The method has the steps of: preparing a substrate 1 on which a first electrode 2 has been formed and forming a laminated film 7 by laminating an organic layer 3 comprising a luminescent layer and a second electrode 4 on the first electrode 2 in this order; forming a first sealing film 5 which covers the whole region of the laminated film 7; forming on the surface of the first sealing film 5 a second sealing film 6 having an opening pattern; and patterning the first sealing film 5 by dry-etching the first sealing film 5 using the second sealing film 6 having the opening pattern as a mask.

Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features.

Abstract: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

Abstract: Methods for fabricating contacts to semiconductor structures are provided. A method comprises forming two members extending from a semiconductor substrate and separated by a portion of the substrate. First and second semiconductor devices are formed in and on the substrate and each comprise a common impurity doped region that is disposed within the portion of the substrate. A dielectric layer is deposited overlying the members, the semiconductor devices, and the common impurity doped region to a thickness such that a depression overlying the impurity doped region is formed. A fill material is deposited to substantially fill the depression and a portion of the dielectric layer is etched. A masking layer is deposited and a portion of the masking layer is removed to expose the fill material. A via is formed by etching the fill material and dielectric layer and a conductive material is deposited therein.

Abstract: Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact being enlarged to reduce resistance without impacting device yield. The semiconductor structure includes a substrate; at least two gate electrodes on the substrate; sidewall spacers adjacent to each of the gate electrodes; a silicide region on the substrate between the gate electrodes; and a contact on the silicide region, wherein the contact includes a self-aligned lower portion on the silicide region, which extends between the sidewall spacers and follows contours of the sidewall spacers, and an upper portion, and wherein the self-aligned lower portion includes a bottom surface adjacent to the silicide region and a top surface adjacent to the upper portion, with the upper portion being narrower than the top surface. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility.

Abstract: Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.

Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress generation of a crack and peeling in a resin BM and deterioration of coverage of an upper layer of the resin BM, even if a black resin is used as a material of the resin BM in order to improve a contrast of brightness and a contrast of color.

Abstract: A method of fabricating silicon micro-mirrors includes etching from opposite sides of a silicon wafer with a polished surface on at least one of the opposite sides, to form silicon bars each having a parallelogram-shaped cross-section and including a portion of the polished surface. At least one of the silicon bars is mounted on a mounting surface. The polished surface of the silicon bar may be used to reflect optical signals.

Abstract: A solution for platinum chemical mechanical polishing is disclosed. Further, a method for forming Pt patterns is disclosed which utilizes the disclosed Pt-CMP solution which contains an alkali aqueous solution and an oxidizer which improves the polishing rate and polishing characteristics of Pt which forms a lower electrode of a metal capacitor.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: A plasma reactor chamber is characterized by performing two steps for each one of plural selected chamber parameters. The first step consists of ramping the level of the one chamber parameter while sampling RF electrical parameters at an RF bias power input to said wafer support pedestal and computing from each sample of said RF electrical parameters the values of the plasma parameters. The second step consists of deducing, from the corresponding chamber parameter data generated in the first step, a single variable function for each of the plural plasma parameters having said one chamber parameter as an independent variable, and constructing combinations of these functions that are three variable functions having each of the chamber parameters as a variable.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.

Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.

Abstract: There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce or prevent the formation of an undercut area in the base of the vertical fin. The structure is formed via the self-limiting properties of the reaction so that the products of the reaction form both vertically on a surface of the vertical fin and horizontally on a surface of an insulating layer (e.g., buried oxide). The products preferentially accumulate faster at the base of the vertical fin where the products from both the horizontal and vertical surfaces overlap. This accumulation or build-up results from a volume expansion stemming from the reaction.

Abstract: An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than the interconnect metal lines. To form this structure, first and second pluralities of trenches are formed in the dielectric layer. At least one of the second plurality of trenches is shallower than the first plurality of trenches. The first and second pluralities of trenches are filled with a conductive layer and then planarized.

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component.

Abstract: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.

Abstract: A method forms a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C.; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas.

Abstract: Disclosed herein is a method for forming an interlayer dielectric film for a semiconductor device by using a polyhedral molecular silsesquioxane. According to the method, the polyhedral molecular silsesquioxane is used as a monomer for a siloxane-based resin or as a pore-forming agent (porogen) to prepare a composition for forming a dielectric film, and the composition is coated on a substrate to form an interlayer dielectric film for a semiconductor device. The interlayer dielectric film formed by the method has a low dielectric constant and shows superior mechanical properties.

Abstract: This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an exposed outer second surface comprising at least one of silicon and silicon dioxide is provided. A layer comprising a metal is deposited over at least the outer second surface. A silanol is flowed to the metal of the outer second surface and to the outer first surface effective to selectively deposit a silicon dioxide comprising layer over the outer second surface as compared to the outer first surface. Other aspects and implementations are contemplated.

Abstract: The present invention relates to low a dielectric material essential for a next generation semiconductor with high density and high performance, and more particularly to a low dielectric material that is thermally stable and has good film-forming properties and excellent mechanical properties, a dielectric film comprising the low dielectric material, and a semiconductor device manufactured using the dielectric film.

Abstract: A method of using a film formation apparatus for a semiconductor process includes removing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus, and then chemically planarizing the inner surface of the reaction chamber by a planarizing gas. The inner surface contains as a main component quartz or silicon carbide. The removing is performed while supplying the cleaning gas into the reaction chamber, and setting the reaction chamber at a first temperature and first pressure to activate the cleaning gas. The planarizing is performed while supplying the planarizing gas into the reaction chamber, and setting the reaction chamber at a second temperature and second pressure to activate the planarizing gas. The planarizing gas contains fluorine and hydrogen fluoride. The second temperature is within a range of from 300 to 800° C.

Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.

Abstract: Nonwoven fabric laminates suitable for use as semipermeable membrane supports are produced by forming a spunbond nonwoven fabric first layer of continuous thermoplastic polymer filaments; forming a wet-laid nonwoven fabric second layer of discrete length thermoplastic polymer fibers; and bonding the first and second layers in opposing face-to-face relationship to form a composite support, where the first and second layers define first and second outer surfaces of the composite support. The resulting semipermeable membrane supports provide an advantageous balance of properties, including smoothness, porosity, interlaminar adhesion, and flux properties.

Abstract: The invention is directed to highly crystalline, frit-sintered glass-ceramic materials and seals made using them that are suitable for solid oxide fuel cell applications. The seals have a coefficient of thermal expansion in the range of 70-130×10?7° C., preferably 85-115×10?7° C. The glass-ceramic materials have a crystalline component and a glass component, the crystalline component being>50% of the glass-ceramic and the glass component being<50%. In one preferred embodiment the crystalline component is >75%. Regarding the crystalline component only,>50% of the crystals in the crystalline component of the glass-ceramic has a structure selected from the structural groups represented by walstromite, cyclowollastonite, ?-(Ca,Sr)SiO3, kalsilite, kaliophilite and wollastonite (the primary crystalline phase) and the remaining <50% of the crystalline component is at least one secondary crystalline phase.

Abstract: Thermal insulation is provided for use in applications requiring continuous resistance to temperatures of 1260° C. without reaction with alumino-silicate firebricks, the insulation comprises fibers having a composition in wt % 65%<SiO2<86%, MgO<10%, 14%<CaO<28%, Al2O3<2%, ZrO2<3%, B2O3<5%, P2O5<5%, 72%<SiO2+ZrO2+B2O3+5*P2O5, 95%<SiO2+CaO+MgO+Al2O3+ZrO2+B2O3+P2O5. Addition of elements selected from the group Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y or mixtures thereof improves fiber quality and the strength of blankets made from the fibers.

Abstract: An aluminoborosilicate glass having a density less than 2.40 g/cm3 and a specific modulus of elasticity greater than 30 GPa·cm3·g?1 is disclosed that comprises the following components (in wt. %): SiO2 58-70, Al2O3 12-20, B2O3 5-15, MgO 0-9, CaO 2-12, BaO 0, 1-5, SnO2 0-1, As2O3 0-2, the glass, apart from random impurities, being free of SrO and free of alkali oxides. The glass is particularly suitable as a substrate glass for LCD displays, for example.

Abstract: The invention pertains to a process for combusting coke of a coke-containing FCC catalyst in a regeneration unit of a FCC unit having the introduction of oxygen-containing gas through a gas-transport unit into the regeneration unit and combusting the coke by means of an oxygen-containing gas, in which the oxygen-containing gas is cooled in a cooling unit before it is brought in contact with the coke-containing FCC catalyst. The invention further relates to an apparatus for performing said process.

Abstract: A catalytic material includes microporous zeolites supported on a mesoporous inorganic oxide support. The microporous zeolite can include zeolite Beta, zeolite Y (including “ultra stable Y”—USY), mordenite, Zeolite L, ZSM-5, ZSM-11, ZSM-12, ZSM-20, Theta-1, ZSM-23, ZSM-34, ZSM-35, ZSM-48, SSZ-32, PSH-3, MCM-22, MCM-49, MCM-56, ITQ-1, ITQ-2, ITQ-4, ITQ-21, SAPO-5, SAPO-11, SAPO-37, Breck-6, ALPO4-5, etc. The mesoporous inorganic oxide can be e.g., silica or silicate. The catalytic material can be further modified by introducing some metals e.g. aluminum, titanium, molybdenum, nickel, cobalt, iron, tungsten, palladium and platinum. It can be used as catalysts for acylation, alkylation, dimerization, oligomerization, polymerization, hydrogenation, dehydrogenation, aromatization, isomerization, hydrotreating, catalytic cracking and hydrocracking reactions.

Abstract: The objective is to incarcerate a Lewis acid metal in a polymer and to make this catalyst recoverable while maintaining its function as a Lewis acid metal catalyst. The present invention is a polymer-incarcerated Lewis acid metal catalyst in which a Lewis acid metal is incarcerated in a crosslinked polymer and the crosslinked polymer is crosslinked using the crosslinking groups contained in a crosslinkable polymer. The polymer incarcerated Lewis acid metal catalyst is characterized by the crosslinkable polymer containing at least one type of monomer unit containing hydrophobic substituents and hydrophilic substituents containing crosslinking groups, and the hydrophobic substituents contain aromatic substituents. This crosslinkable polymer preferably comprises at least one type of monomer unit containing hydrophobic substituents and hydrophilic substituents containing crosslinking groups and a monomer unit containing hydrophobic substituents.

Abstract: Decomposition of methane to produce carbon monoxide-free hydrogen is accomplished using un-supported, nanometer sized, hydrogen reduced, nickel oxide particles made by a precipitation process. A nickel compound, such as NiCl2 or Ni(NO3) is dissolved in water and suitably precipitated as nickel hydroxide. The precipitate is separated, dried and calcined to form the NiO catalyst precursor particles.

Abstract: The present invention provides catalysts, reactors, and methods of steam reforming alcohols over a catalyst. Surprisingly superior results and properties obtained in methods and catalysts of the present invention are also described.

Abstract: A thermal transfer image receiving sheet containing a substrate having thereon a porous intermediate layer and an image receiving layer in that order, wherein the porous intermediate layer has a void ratio of not less than 30%; the porous intermediate layer contains inorganic microparticles; and the porous intermediate layer and the image receiving layer are formed by a coating method.

Abstract: The introduction of nanostructures in a liquid provides a means for changing the physical and/or chemical properties of the liquid. Improvements in heat transfer, electrical properties, viscosity, and lubricity can be realized upon dispersion of nanotubes in liquids. Stable dispersions of nanostructures are described and surfactants/dispersants are identified which can disperse nanostructures in petroleum liquid medium. The appropriate dispersant is chosen for the selected nanostructure material and the oil based medium and the dispersant is dissolved into the liquid medium to form a solution. The nanostructure is added to the dispersant containing the solution with agitation, ultrasonication, and/or combinations thereof. Nanostructures dispersed in a fluid form a nanofluid utilized as a shock absorber oil whereby the nanostructures serve to improve the viscosity index of the fluid or more particularly the shock absorber oil in the form of a lubricant additive.

Abstract: Disclosed are conditioning compositions comprising by weight: (a) from about 0.1% to about 10% of a surfactant system comprising at least one cationic surfactant; (b) from about 0.05% to about 10% of a polymer selected from the group consisting of an anionic polymer, an amphoteric polymer, and mixtures thereof; and (c) an aqueous carrier; wherein the surfactant system and the polymer form a water-insoluble complex upon dilution, and wherein the composition is transparent or translucent. The compositions are especially suitable for hair care products such as hair conditioning products for rinse-off use.

Abstract: A cleaning implement with a handle and a removable cleaning pad can be used to effectively clean surfaces. The cleaning pad is impregnated with an acidic cleaning composition. The cleaning pad may be dry to the touch. The cleaning implement may be a manual tool or a motorized tool. Examples of suitable cleaning implements include a hard surface floor mop, a carpet mop, an auto cleaning device, a toilet cleaning device, a bathroom cleaning device, and a shower cleaning device.

Abstract: A light duty liquid cleaning composition comprising at least one ammonium or metal salt of a C8-C16 linear alkyl benzene sulfonate surfactant, at least one ammonium or metal salt of an ethoxylated C8-C18 alkyl ether sulfate surfactant having 1 to 30 moles of ethylene oxide, and at least one betaine surfactant; wherein (a) a total amount of surfactant in the composition is at least 30 weight %, (b) the composition has a pH less than 7 and a viscosity of less than 75 cPs measured at 25° C., (c) if a magnesium salt of a C8-C16 linear alkyl benzene sulfonate surfactant is present in the composition, it is present in an amount of 0.1 to less than 3 or greater than 16% by weight of the composition, and (d) the composition does not contain an inorganic magnesium salt.

Abstract: The present invention relates to a detergent auxiliary composition comprising: (i) a liquid or liquefiable active component; and (ii) a water-insoluble solid support component and (iii) a water-soluble and/or water dispersible encapsulating material; and (iv) optionally one or more adjunct components, characterised in that the composition further comprises (v) a surface deposition enhancing cationic polymer or oligomer having cationic groups such that fewer than 50% are de-activated when a 1% by weight solution of the polymer or oligomer (prepared in deionised water and then adjusted to pH 7.0 with sodium carbonate or citric acid) is stored at 25° C.

Abstract: The invention pertains to a method of inactivating prions located on surfaces. In an embodiment, the invention pertains to a method of inactivating prions located on surfaces using a composition including a peracid. In an embodiment, the invention pertains to a method of inactivating prions located on surfaces using a composition including a peracid and a surfactant. The composition may comprise additional functional ingredients.

Abstract: The present invention provides preferred, preferably liquid, hard surface cleaning compositions, compositions with cleaning liquid composition on a substrate, compositions used with absorbent pads and implements and devices for making the process of cleaning hard surfaces and/or maintaining their appearance and hygiene easier and more effective.

Abstract: The present patent application relates to a cleansing composition comprising in an aqueous medium at least one surfactant selected from alkylpolyglycosides, maltose esters, glycerolated fatty alcohols, N-alkylglucamine derivatives, amido ether carboxylates, acetates, alaninates, aspartates, glycinates, citrates, galacturonates, fatty acid salts constituting soaps, phosphates, amphoteric and zwitterionic surfactants, and at least one amphiphilic polymer comprising at least one ethylenically unsaturated monomer containing a sulphonic group in free form or in partially or totally neutralized form and comprising at least one hydrophobic portion. The composition can especially constitute a foaming composition that has a good volume of foam by virtue of the presence of the amphiphilic polymer. The composition of the invention may especially be used in cosmetology or dermatology, as a cleansing product or make-up-removing product for the skin, the scalp and/or the hair.

Abstract: In accordance with the present invention, there are provided peptides that bind to a member of the mammalian selectin family and inhibit the binding of a carbohydrate to the selectin. Invention peptides are useful to inhibit of the adhesion of cells containing particular cell-surface carbohydrates to cells containing cell-surface selectins. Also provided are pharmaceutical compositions comprising invention peptides useful in methods for inhibiting a carbohydrate from binding to a selectin, and in methods of inhibiting tumor cell metastasis in a subject.

Abstract: The present invention addresses the treatment of age-related macular degeneration using regulation of pathogenic mechanisms similar to atherosclerosis. In further specific embodiments, compositions that increase reverse cholesterol transport are utilized as therapeutic targets for age-related macular degeneration. In a specific embodiment, the lipid content of the retinal pigment epithelium, and/or Bruch's membrane is reduced by delivering Apolipoprotein A1, particularly a mimetic peptide.

Abstract: The present invention addresses the treatment of age-related macular degeneration, and treatment of individuals with impaired visual function such as impaired dark adaptation, using regulation of pathogenic mechanisms similar to atherosclerosis. In further specific embodiments, compositions that increase reverse cholesterol transport are utilized as therapeutic targets for age-related macular degeneration and improving impaired dark adaptation. In a specific embodiment, the lipid content of the retinal pigment epithelium, and/or Bruch's membrane is reduced by delivering Apolipoprotein A1, particularly a mimetic peptide.