Abstract: A method for the startup of a solar power inverter in which a waiting period is increased between successive attempts to start the inverter. This method allows the inverter to start up in a reasonable amount of time while avoiding excessive cycling during prolonged periods of low light.

Abstract: A plug and an outlet are electrically and directly connected, and when a control circuit determines that AC power is input from a power source to a bidirectional insulated DC/AC inverter by voltage V1 detected in a voltage detection circuit, driving of each bridge circuits is inhibited so as not to output AC power outward from the bidirectional insulated DC/AC inverter.

Abstract: The present invention is a DC/AC inverter for converting a DC supply voltage signal to an AC voltage signal. The DC/AC inverter includes a drive circuit, a switch circuit, a transformer circuit and an auxiliary circuit. The drive circuit provides a first drive signal and a second drive signal. The switch circuit includes a high-side transistor for receiving the first drive signal from the drive circuit and a low-side transistor for receiving the second drive signal from the drive circuit. The switch circuit further receives the DC supply voltage signal and generates a voltage signal. The transformer circuit receives the voltage signal from the switch circuit and transforms it to the AC voltage signal. The auxiliary circuit adjusts a gate-source voltage of the high-side transistor and thus enables the DC/AC inverter to be applicable to a wide DC voltage supply range.

Abstract: A data storage device for storing digital information in a readable form is described made up of one or more memory elements, each memory element comprising a planar magnetic conduit capable of sustaining and propagating a magnetic domain wall formed into a continuous propagation track. Each continuous track is provided with at least one and preferably a large number of inversion nodes whereat the magnetization direction of a domain wall propagating along the conduit under action of a suitable applied field, such as a rotating magnetic field, is changed.

Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

Abstract: A ballistic memory cell structure employing ballistic transistor technology for switching between a read state and a store state is disclosed. The memory cell structure includes substrate structures forming a side wall and a main chamber for defining a linear ballistic channel between the two. The main chamber is formed to include a deflection channel with deflective surfaces to deflect an electron emitted from an electron source into the memory cell structure. Deflection controllers are coupled to the substrate structures for generating biasing fields that adjust the trajectory of electrons flowing through the linear ballistic channel and the deflection channel. Logic output terminals are positioned beyond channel exits for registering exiting electrons and determining a read or store state.

Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Abstract: A multi-bit magnetic random access memory device and a method for writing to and sensing the multi-bit magnetic random access memory device. The magnetic memory includes a memory cell with a multilayer structure having a plurality of data layers which can each store one bit. The structure includes a plurality of magnetically changeable ferromagnetic layers, a ferromagnetic reference layer having a fixed magnetization state, a first spacer layer separating the magnetically changeable ferromagnetic layers, and a second spacer layer separating the ferromagnetic reference layer from the magnetically changeable ferromagnetic layers. This structure allows for more than one-bit to be stored as well as for efficient writing and reduced power consumption.

Abstract: A method and system for providing and utilizing a magnetic memory are described. The magnetic memory includes a plurality of magnetic storage cells. Each magnetic storage cell includes magnetic element(s) programmable due to spin transfer when a write current is passed through the magnetic element(s) and selection device(s). The method and system include driving a first current in proximity to but not through the magnetic element(s) of a portion of the magnetic storage cells. The first current generates a magnetic field. The method and system also include driving a second current through the magnetic element(s) of the portion of the magnetic storage cells. The first and second currents are preferably both driven through bit line(s) coupled with the magnetic element(s). The first and second currents are turned on at a start time. The second current and the magnetic field are sufficient to program the magnetic element(s).

Abstract: A memory device includes a memory element, a first wiring and a second wiring. The memory element includes a memory layer retaining information based on a magnetization state of a magnetic material and a magnetization pinned layer in which a magnetization direction is pinned and which is provided for the memory layer through a non-magnetic layer, in which current flows in a stacking direction to change a magnetization direction of the memory layer. The first wiring supplies current flowing in the stacking direction of the memory element, and the second wiring supplies current to apply a current magnetic field to the memory element. When information is recorded in the memory device, a first pulse current is supplied to the first wiring, a second pulse current is supplied to the second wiring, and the second pulse current falls at least 10 picoseconds after the first pulse current falls.

Abstract: A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

Abstract: A magnetic random access memory device include a spin torque MRAM cell (100) having a reduced switching current (Ic) wherein standard materials may be used for a free layer (108). A fixed magnetic element (112) polarizes electrons passing therethrough, and the free magnetic element (108) having a first plane anisotropy comprises a first magnetization (130) whose direction is varied by the spin torque of the polarized electrons. An insulator (110) is positioned between the fixed magnetic element (112) and the free magnetic element (108), and a keeper layer (104) positioned contiguous to the free magnetic element (108) and having a second plane anisotropy orthogonal to the first plane anisotropy, reduces the first plane anisotropy and hence reduces the spin torque switching current (Ic). The keeper layer (104) may include alternating synthetic antiferromagnetic layers (132, 134) of magnetization approximately equal in magnitude and opposite in direction.

Abstract: Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references are set to respective members of a second set of values, and the physical states of the cells are read according to the second set. At least one member of the second set is different from any member of the first set, so that the two readings together read the physical states of the cells with higher resolution than the first reading alone.

Abstract: A non-volatile memory and methods include cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is defective or not; and a second data hold circuit configured to hold data read out of the first data hold circuits, and to control skipping a defective column address of the memory cell array in accordance with the data read out of the first data hold circuit.

Abstract: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.

Abstract: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.

Abstract: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

Abstract: A NAND type flash memory array which is composed of a plurality of memory cells with a shallow junction on an SOI substrate to make the body region depleted fully when each channel of the memory cells is turned on is provided. The invention improves the efficiency of a reading operation, enables an erasing operation on the SOI structure and enables use of a low voltage VPASS instead of a high voltage VPASS, which is used for a programming operation in a conventional NAND type flash memory array, and therefore it diminishes programming disturbance more effectively than a conventional array.

Abstract: A non-volatile semiconductor memory device and method of programming the non-volatile semiconductor memory device are disclosed. The non-volatile semiconductor memory device includes a selected word-line and unselected word-lines including at least one unselected word-line to which a first voltage signal is applied. The selected word-line is coupled to a selected memory transistor and receives a program voltage signal in response to a program voltage enable signal. A first voltage signal is applied to the at least one unselected word-line. The first voltage signal has a voltage level of a reduced pass voltage signal before the program voltage enable signal is activated and has a voltage level of a pass voltage signal while the program voltage enable signal is activated.

Abstract: Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

Abstract: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied to a second circuit portion with transistors. The output of the first circuit portion is coupled to ground by a discharge transistor. A third circuit portion with transistors receives a third voltage transformed, starting from the second voltage for biasing at least one word line connected downstream of the third circuit portion. A circuit portion with a discharge switch incorporates the discharge transistor, and further includes a pair of transistors connected in series to each other by an interconnection node. The interconnection node is connected to the body terminal of the discharge transistor.

Abstract: A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.

Abstract: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

Abstract: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.

Abstract: A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

Abstract: This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the memory cell to transmit the data; a second bit line transmitting reference data used to detect the data stored in the memory cell; a first sense node and a second sense node transmitting the data stored in the memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop applying a load current to the memory cell during a data read operation and amplifying a potential difference generated between the first sense node and the second sense node by turning off the first short-circuiting switch.

Abstract: The present invention provides a semiconductor device and a control method thereof, the semiconductor device including: a bit line connected to a memory cell; a voltage control circuit controlling a voltage supplied from a voltage source to the bit line; a differential amplifier circuit providing the control voltage to the voltage control circuit in response to a voltage at a node coupled to the bit line and a reference voltage; and a current source providing a current to the differential amplifier circuit. The current source provides more current to the differential amplifier circuit in the first period including a period for precharging than in the second period after precharging.

Abstract: A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block with a dummy bit line connected to the dummy column and to a timing circuit. A normal bit line connected to the normal memory cells provides the read normal bit to input/output logic. Whenever a normal memory cell is accessed during the read operation, the circuitry of the corresponding dummy row enables the dummy bit line to discharge, and when the voltage across the dummy bit line reaches a predetermined value, the timing circuit produces a timing signal to activate the input/output circuitry to read the data stored in the accessed memory cell.

Abstract: A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.

Abstract: For sensing a target temperature, first and second temperature detectors generate first and second delay signals having negative and positive delay changes with temperature. A comparator senses the target temperature from the first and second delay signals such as by activating an output signal when the temperature is at least the target temperature.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines during a write operation.

Abstract: This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

Abstract: Analog beamformers for continuous wave ultrasonic receivers, typically realized in integrated circuit form and using a direct quadrature baseband conversion architecture for CW Doppler to eliminate a second down conversion mixer and second synthesizer. The beamformers use integrated mixers and LO's for phase steering, and dedicated ring counters for each channel for lower noise. Input filtering may be provided with switchable RF input low pass filters. The integrated circuit includes the ultrasound signal VGA and beamformer on the same chip. An auxiliary channel may be included for a self-test mode. Also a programmable bit soft shutdown feature, programmable via the serial port, allows disabling individual channels. Various other features are disclosed including cascading of multiple integrated circuits for a much greater number of channels.

Abstract: A method of providing an indication of the direction of a target such as a sniper. A rifle mounted sensor array detects an acoustic pulse originating from the target. The signal is processed to estimate the direction of the target, and an indication is provided when the weapon is aligned with the estimated direction. The direction of arrival of an acoustic pulse is estimated by spectrally decomposing each signal from the sensor so as to generate one or more spectral components for each signal, and processing the spectral components to estimate the direction of arrival.

Abstract: A position indicator comprises: a first indicator pattern composed of a plurality of substantially identical first partial patterns periodically arranged in a direction of extension, and a second indicator pattern composed of a plurality of substantially identical second partial patterns periodically arranged in the direction of extension. The first partial patterns may extend, along a first line extending transversely to the direction of extension, and the second partial patterns may extend along a second line extending transversely to the first line and the direction of extension The first and second partial patterns may be each composed of plural sub-patterns disposed adjacent to one another in the direction of extension. The sub-patterns of each pair of sub-patterns of the respective partial pattern are different from each other.

Abstract: A timer includes a timing device that generates first and second time counts responsive to user input. A display is provided that displays the first time count in one of a first set of time units and a second set of time units. A user actuatable device is operatively connected to said display and causes the display to clear the first time count and display the second time count.

Abstract: A digital audio signal player includes a reproducing unit to pick a disc audio signal which is stored in a disk, and a digital signal processor for controlling input and output of the disc audio signal of the memory. Thus, when the system processing unit receives the trigger signal of the trigger switch after the contact member is pressed to contact the trigger switch, the system processing unit drives the digital signal processor to modulate the disc audio signal stored in the memory according to the detected signal of the sensor so as to produce a special audio signal output.

Abstract: Systems and methods in accordance with embodiments can be used to re-write user data to a rotatable storage medium. When a position of a write element is not within a threshold during a data write operation, a part of a data track potentially affected by the write operation, while the position of the write element was not within the threshold, can be determined. When the device including the rotatable storage medium is free from other data transfer operations, the data of the data track potentially affected by the write operation can be re-written. In this manner, data that may be considered less reliable due to the misplacement of a write element during a data write operation, can be re-written.

Abstract: A method for verifying sectors on an optical disc is provided. The method includes writing user data to unverified sectors of the optical disc and verifying the sectors of the optical disc with the user data. The sectors of the optical disc are verified by reading the user data on the unverified sectors of the optical disc and comparing the user data read from the unverified sectors of the optical disc with user data stored on a system buffer. The sectors of the optical disc are verified to determine whether any one of the unverified sectors having user data is defective. Also, the verifying of the unverified sectors establishes verified sectors having user data. The sectors of the optical disc that have been verified are tracked with a bitmap that is continually updated as the sectors are verified.

Abstract: An information recording device is used for recording record information in an information recording medium at least including a first recording layer capable of forming a first recording area and a second recording layer capable of forming a second recording area. The information recording device includes: write elements; acquisition elements for acquiring offset information indicating a relative shift; calculation elements for calculating an address (“Y?=Inv Y??”) indicating a second boundary point opposing to a first boundary point according to the offset information; and control elements for controlling the write elements so as to write record information (i) while making the first boundary point a recording end or start position and (ii) making the second boundary point indicated by the calculated address a recording start or end position.

Abstract: A rotation correcting apparatus has a tracking servo controller which generates a tracking signal to perform a tracking servo control for guiding an optical beam spot outputted from a pickup to tracks of an optical disk and a track jump control for moving the optical beam spot to a certain track; a feed motor controller which controls a feed motor for moving the pickup to radius direction of the optical disk; a storage which stores signal component with a prescribed frequency band including a rotation frequency of the optical disk, the signal component being included in an output signal of the tracking servo controller; and a combination unit which combines the signal component stored in the storage with the tracking signal to generate an ultimate tracking signal for the tracking servo control and the tracking jump control, wherein the feed motor controller controls the feed motor based on the tracking signal generated by the tracking servo controller without using the signal component stored in the storage.

Abstract: An optical disk apparatus for recording data on an optical disk having a land pre-pit (LPP). An encoder of a DVD-R/RW drive records data while inserting synchronization information having a length of 14T at the top of a synchronous frame. The encoder sets synchronization information of the i-th frame (wherein i is an integer which is 0 or greater) and the (i+1)th frame of a plurality of consecutive frames to either a mark or a space such that each DSV is minimized. The encoder sets the synchronization information of the (i+2)th frame such that the polarity of the synchronization information of the (i+2)th frame is opposite to the polarity of the synchronization information of the i-th frame, and sets the synchronization information of (i+3)th frame such that the polarity of the synchronization information of (i+3)th frame is opposite to the polarity of the synchronization information of the (i+1)th frame.

Abstract: In one embodiment, the recording medium includes a user data area on which one or more recording ranges are allocated and a management area. The method includes receiving a command to record the data on a closed recording range. The closed recording range has no recordable position. An open recording range having a recordable position is selected from one or more open recording ranges on the user data area, and the data is recorded starting from the recordable position of the selected open recording range.

Abstract: A method of and drive for recording medium defect management, and a defect managed recording medium. The defect management method includes: writing first state information that specifies that an update cycle of a temporary defect management structure (TDMS) is open when updating of the TDMS begins, the TDMS containing information regarding temporary defect management; updating the TDMS when data is written to or read from the information storage medium; and writing second state information that specifies that the update cycle of the TDMS is closed, when the updating of the TDMS is completed.

Abstract: A method of and drive for recording medium defect management, and a defect managed recording medium. The defect management method includes: writing first state information that specifies that an update cycle of a temporary defect management structure (TDMS) is open when updating of the TDMS begins, the TDMS containing information regarding temporary defect management; updating the TDMS when data is written to or read from the information storage medium; and writing second state information that specifies that the update cycle of the TDMS is closed, when the updating of the TDMS is completed.