Abstract: A resolver of a variable reluctance type includes a resolver stator portion of a substantially annular shape centered about a central axis, and a resolver rotor portion which is attached to a shaft of a motor rotor portion arranged inwardly of the resolver stator portion. The resolver is operable to increase accuracy for detecting a rotational angle when a size of gap g between a rotor core and a resolver stator portion at a predetermined point at an outer circumferential edge of the rotor core is set by using a maximum value for the gap g (gmax), a minimum value for the gap g (gmin), angle ? defined by a predetermined point and a reference point, axial double angle n, and the coefficient.

Abstract: An apparatus for sensing rotation of a wheel includes a sensor and a detector. The sensor is disposed in a wheel, and is operable to detect the earth magnetic field. The detector is operable to detect a change of a sensed earth magnetic field in order to sense rotation of the wheel based on the detected change.

Abstract: Provided is a current sensor capable of detecting an induced magnetic field by a current to be detected with higher precision. The first and second modules are provided on facing surfaces of integrated substrates, respectively, with spacers in between. Each of the first and second modules includes an element substrate, and an MR element layer. On each of the MR elements layers, provided is an MR element having a stacked structure including a pinned layer, a nonmagnetic intermediate layer, and a free layer whose magnetization direction changes according to the induced magnetic field and which exhibits an anisotropic field in a direction different from that of the magnetization of the pinned layer. The stacked structures of the MR elements are provided in a same layer level.

Abstract: To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

Abstract: The present invention is directed to methods for chemical species signal suppression in magnetic resonance imaging procedures, wherein Dixon techniques are enhanced by continuously sampling techniques. In the invention, k-space data is acquired during the entire period of read gradient associated with a gradient echo pulse acquisition scheme. The invention utilizes a total sampling time (TST) acquisition during the entire read gradient, using three echoes of a TST data set to achieve chemical species separation in both homogenous fields as well as areas of field inhomogeneity. As an example, a continuously sampled rectilinearly FLASH pulse sequence is modified such that the time between echoes was configured to be 2.2 milliseconds, with TE selected to allow 180° phase variation in the fat magnetization between each of the three TE's (TE1, TE2, and TE3).

Abstract: When scanning a patient to generate an image thereof, radio frequency (RF) coil modules are scalably coupled to each other using a plurality of clips to form flat or polygonal coil arrays that are placed on or around the patient or a portion thereof. A user assesses the volume to be imaged, identifies a coil array configuration of suitable size and shape and employs clips of one or more pre-determined angles to construct the identified coil array configuration, which is placed on or about the volume. Coil modules are coupled to a preamplifier interface box (PIB), which provides preamplified coil signal(s) to a patient imaging device, such as an MRI scanner. Small arrays are constructible to accommodate pediatric patients and/or smaller animals. Modules are hermetically sealed, can be sanitized between uses, and discarded at end-of-life. In one aspect, the modular coil array, clips, and PIB are maintained in an isolated contamination zone, separate from the patient imaging device.

Abstract: A coolant sub-assembly is provided for use in a DNP apparatus. The sub-assembly comprises a plurality of concentric jackets surrounding an inner bore tube having first and second opposed ends. The jackets are adapted to inhibit heat flow to the inner bore tube, a DNP working region being defined within the inner bore tube where a DNP process will be performed on a sample in the DNP working region. A coolant supply path extends adjacent an outer surface of the inner bore tube at the DNP working region in order to cool said outer surface, whereby a sample holder assembly can be inserted through the first end of the inner bore tube to bring a sample holder into the DNP working region and can be moved through the second end of the inner bore tube. An auxiliary coolant supply path supplies coolant to a sample, located in use in the sample holder at the DNP working region, through at least one aperture in the inner bore tube wall at the DNP working region.

Abstract: An airborne electromagnetic survey system for conducting geological mapping is disclosed. A transmitter closed loop structure is used in the system and is designed for connection to a towing airborne vehicle. The transmitter loop structure comprises a plurality of interconnected loop segments, and transmitting means are fitted to at least one of the loop segments for generating and transmitting an earthbound primary electromagnetic field effective for geological surveying. Sensing means are fitted to the loop segments for receiving and sensing a vertical component of a secondary resulting electromagnetic field which arises from an interaction of the primary electromagnetic field with ground bodies that are traversed by the sensing means, while simultaneously nulling the primary electromagnetic field.

Abstract: A method for measuring a resistance and an inductance of a permanent magnet synchronous motor (PMSM) in a static state includes inputting a rated current of the PMSM and 150% of the rated current at a state of locking an axle of the PMSM, recording corresponding voltages V100% and V150%, and dividing the voltage difference with the current difference to obtain the resistance of the PMSM. The method continues dividing an electrical period into six voltage vectors, and performing four voltage cycles for every the voltage vector. The voltage cycle includes step of outputting a quarter of the voltage V150%, and outputting the voltage V150% after the current being stable. After one of the six voltage vectors being finished, the method switches to the other voltage vectors and repeats the voltage cycles, and the method is completed till all of the six voltage vectors being finished.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: The invention provides for a method of using a network analyzer and a test controller for measuring S-parameters of a device, which can assume a plurality of states, and which can switch very fast from one state to another. The test controller sends a trigger to the analyzer, which starts a frequency sweep when it receives this trigger. The frequency sweep, having substantially the same start and stop frequency, is provided to the device. The analyzer then executes a measurement of at least one S-parameter of the device, stores the S-parameter data from the measurement and provides the test controller with a trigger. The test controller then updates the device to the next state in a predetermined sequence of states when it receives the trigger from the analyzer. These steps are repeated until all states in the predetermined sequence of states have been measured.

Abstract: A measuring apparatus is provided which has least one voltage source for providing a supply voltage for a semiconductor device to be tested, at least one first tester channel connected to the supply voltage source via a first RC element having a first resistor and a first capacitor connected in series therewith, wherein the first tester channel is adapted for the temporally resolved measurement of a charging voltage of the first capacitor.

Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Abstract: On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: A circuit for rounding the edges of a digital pulse so as to reduce interference has a first rounding block, a second rounding block and an output stage. The first rounding block rounds the second and fourth pulse edges so as to prolong rising and falling time of the digital pulse. The second rounding block rounds the first and third pulse edges in accordance with non-linear characteristics of a semiconductor of the second rounding block. The output stage is a feedback circuit where the first rounding block is coupled with the second rounding block and the second rounding block is coupled with the feedback circuit.

Abstract: A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

Abstract: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.

Abstract: In various embodiments of the invention, a power-harvesting termination circuit may be used to 1) match the impedance of a signal line being terminated, and 2) recover a portion of electrical power from a signal on the signal line and provide the recovered power as an electrical voltage to be used to power other circuits. The power may be harvested at either the receiving device or at the transmitting device.

Abstract: A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract: In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

Abstract: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.

Abstract: A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.

Abstract: A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.

Abstract: A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

Abstract: The present invention relates to an apparatus for accurately detecting a mains phase. The apparatus is constructed with a zero-crossing detector, a digital phase detector, a digital loop filter, and a digital controlled oscillator (DCO) of a direct digital synthesized (DDS) manner. The present apparatus employs an all-digital loop architecture and a high sampling clock to recover a signal with a phase orthogonal with the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. The present apparatus is capable of implementing signal tracking of a zero frequency error and a zero phase in a wide range, and can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc.

Abstract: An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.

Abstract: A phase discriminator for being used in a phase-locked loop to determine if a phase difference between a reference signal and a target signal has reached a programmable gap value is disclose which comprises a programmable phase gap selector receiving the reference signal, a first phase digital converter converting an output signal from the programmable phase gap selector to a first digital code, a second phase digital converter converting a phase difference between the target signal and the reference signal to a second digital code, and a code comparator comparing the first and second digital code and generating a first instructional signal based on a change of order of the values of the first and second digital code.

Abstract: Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: An apparatus for setting an attenuation of an attenuator includes a control transistor, which includes a drain connected to a gate of a shunt transistor of the attenuator. A channel resistance of the shunt transistor corresponds to a current density of the control transistor, and the channel resistance of the shunt transistor determines the attenuation of the attenuator. The current density of the control transistor is based at least in part on a control voltage input to the apparatus.

Abstract: A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value.

Abstract: A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.

Abstract: An integrated circuit and method of generating a bias signal for a data signal receiver is disclosed. One embodiment provides a replica circuit configured to generate a feedback signal, wherein the replica circuit is a replica of at least a part of a data signal receiver, and wherein the feedback signal depends on a reference signal of the data signal receiver. A compensation circuit is configured to compensate an influence of the reference signal on the feedback signal. An amplifier circuit is configured to generate a bias signal based on the feedback signal, the bias signal being provided to the data signal receiver.

Abstract: A programmable current generator includes a decoder unit to generate a first and a second set of control signals as a function of a current control word. The current generator further includes a first and a second array of current sources, wherein the current sources of the first array generate a first current and an auxiliary current, each depending on the first set of control signals and on a reference current. The second array of current sources generates a second current depending on a second set of control signals and on the auxiliary current. An output current is generated depending on the first and the second current.

Abstract: A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: The contents of a distortion compensation table for adjusting a waveform of a signal input to an amplification apparatus are more precisely adjusted to suppress distortion occurring in an output signal. A table value calculation unit exercises adaptive control over compensation data I and Q according to the perturbation method using power series to update a power series distortion compensation table when distortion of an output signal from a power amplification unit is greater than a first threshold used in the adaptive control process performed on the compensation data I and Q according to the perturbation method using power series.

Abstract: There is provided a feed-forward amplifier which enables a predistortion circuit to obtain sufficient distortion compensation effects even if ambient temperature or the like changes.

Abstract: A Class D amplifier includes a ramp generator that generates a ramp signal and an inverted ramp signal. A signal generator generates first, second, third and fourth signals by comparing the ramp and inverted ramp signals to an input signal. A frequency of the ramp signal is approximately two orders of magnitude higher than a frequency of the input signal. The signal generator transitions from a first state to a second state of a first control signal after one of the first and second signals occurs, transitions from a first state to a second state of a second control signal after one of the third and fourth signals occurs, and transitions from the second state to the first state of one of the first and second control signals when the other of the first and second control signals transitions to the second state.

Abstract: A low-voltage operational amplifier includes a differential amplifying stage, an output amplifying stage and a compensation stage. The differential amplifying stage amplifies a difference between a first signal and a second signal that constitute a differential pair using an input pair of NMOS transistors, and outputs an amplified first signal and an amplified second signal. The output amplifying stage amplifies a difference between the amplified first signal and the amplified second signal using an input pair of PMOS transistors, and outputs a first output signal and a second output signal that constitute a differential pair. The compensation stage receives the amplified first signal, the amplified second signal, the first output signal, and the second output signal, and reduces a settling time of the first output signal and the second output signal.

Abstract: A disclosed operational amplifier circuit with a multi-stage amplifier configuration provides fast-response and high withstand-voltage characteristics without using high withstand-voltage transistors as output transistors in its amplifying stages. The output voltage range of a differential amplifier circuit in a first stage is limited by voltage clamping based on a reverse withstand voltage of a bipolar diode. The output voltage range of an amplifier circuit in a second stage is limited by voltage clamping based on a reverse withstand voltage of another bipolar diode. A constant voltage circuit and an apparatus including such an operational amplifier circuit are also disclosed.

Abstract: A differential stage which uses a bias generator circuit to set the operating currents of the input stage FETs to make the incremental Gm primarily a function of a single resistor embedded in the biasing circuit, such that the input stage has a Gm which only gradually departs from nominal under overdrive, and continues to supply output currents which increase with an increasing differential input signal.