Abstract: A backup and archiving system utilizing tape cassettes avoids bottlenecks at a higher performance level that may be caused by a central working storage, especially during backup and archiving procedures. Such a backup and archiving system provides a distributed hardware architecture in which several Component Computers work without reciprocal obstruction.

Abstract: A method, system, and computer readable medium for maintaining the order of write-commands issued to a data storage, where the write-commands are issued by one or more host. In one embodiment of the present invention the method includes assigning an order-descriptor to each write-command, storing the write-command, storing the order-descriptor, and collating a plurality of order-descriptors and their corresponding write-commands to obtain an ordered write-command stream.

Abstract: Performance of a storage subsystem is monitored at a proper level in a computer system having host computers, the storage subsystems, and a management computer. Each storage subsystem has physical disks and a disk controller to control input/output of the data to/from the physical disks. The disk controller provides storage areas of the physical disks as one or more logical volumes to the host computer. The management computer makes each of the logical volumes correspond to one of a plurality of groups, sets monitoring conditions of the logical volumes every group, monitors performance information of the logical volumes in accordance with the set monitoring conditions, and if a correspondence between the logical volume and the group is changed, changes the monitoring conditions set to at least one of the plurality of groups.

Abstract: A technique places content, such as data, of one or more data containers on volumes of a striped volume set (SVS). The placement of data across the volumes of the SVS allows specification of a deterministic pattern of fixed length. That is, the pattern determines a placement of data of a data container that is striped among the volumes of the SVS. The placement pattern is such that the stripes are distributed exactly or nearly equally among the volumes and that, within any local span of a small multiple of the number of volumes, the stripes are distributed nearly equally among the volumes. The placement pattern is also substantially similar for a plurality of SVSs having different numbers of volumes.

Abstract: A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or increasing performance. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. In some embodiments, less than the full tag portion is archived. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. In some embodiments, less than the full archive is restored. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: Embodiments disclosed herein provide a cache management system comprising a cache and a cache manager that can poll cached assets at different frequencies based on their relative activity status and independent of other applications. In one embodiment, the cache manager may maintain one or more lists, each corresponding to a polling layer associated with a particular polling schedule or frequency. Cached assets may be added to or removed from a list or they may be promoted or demoted to a different list, thereby changing their polling frequency. By polling less active files at a lower frequency than more active files, significant system resources can be saved, thereby increasing overall system speed and performance. Additionally, because a cache manager according to embodiments disclosed herein does not require detailed contextual information about the files that it is managing, such a cache manager can be easily implemented with any cache.

Abstract: A transactional shared memory system has a plurality of discrete application nodes; a plurality of discrete memory nodes; a network interconnecting the application nodes and the memory nodes, and a controller for directing transactions in a distributed system utilizing the shared memory. The memory nodes collectively provide an address space of shared memory that is provided to the application nodes via the network. The controller has instructions to transfer a batched transaction instruction set from an application node to at least one memory node. This instruction set includes one or more write, compare and read instruction subsets, and/or combinations thereof. At least one subset has a valid non null memory node identifier and memory address range. The memory node identifier may be indicated by the memory address range.

Abstract: An information processing apparatus for processing an access request to access a recording medium from an application includes the following elements. A setting unit sets a priority unique to the access request from the application or permission information indicating whether or not processing on the access request from the application is permitted. A queue controller stores the access request provided with the priority or the permission information in a queue. An access request processor processes the access request stored in the queue according to the priority or the permission information.

Abstract: Provided are a method, system, and program for establishing copy relationships to copy source data to target data. A request is received to establish a copy relationship indicating to copy source data to target data. A determination is made as to whether the source data defined in the request comprises target data defined in a preexisting copy relationship. A determination is made as to whether base source data copied to the target data in the preexisting copy relationship also comprises the source data indicated in the request in response to determining that the source data defined in the request comprises target data in the preexisting copy relationship. A new copy relationship is defined to copy the determined base source data to the target data indicated in the request.

Abstract: A method, apparatus, and computer instructions in a processor for associating a data type with a memory location. The type is associated with a location by means of metadata that is generated and manipulated by hardware instructions that are typically generated by a compiler as it generates the other instructions that comprise the machine code version of a program. A determination is made as to whether a data value about to be stored is of the required data type for that location. The hardware indicates an error condition if the types do not match.

Abstract: A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage collection barrier instruction; wherein the processor is configured to execute the garbage collection barrier instruction, including by: evaluating a memory reference to determine a condition associated with the garbage collection barrier instruction; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

Abstract: A system for high-speed access and recording includes a demodulator, a buffer memory, and a hard disk. During a write cycle, a content stream is stored in buffer memory and thereafter transferred to the demodulator. When the buffer memory reaches its storage capacity, its contents are transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. The hard disk further includes includes a high-speed zone and a random-access zone, which are configured to operate in a high-speed mode, a random-access mode, and a buffer-cleaning mode.

Abstract: A method and apparatus for implementing a remote mirroring data facility for a computer system comprising a central processing unit (CPU); a first storage system that is coupled to the CPU so that the CPU can store information in the first storage system; a second storage system coupled to the CPU via a communication link; and a mirroring controller to mirror at least some of the information stored in the first storage system in the second storage system by transferring the at least some of the information over the communication link. The communication link can be implemented via a network cloud, which may be the Internet or an intranet. Multiple pipes can be used to pass data through the network cloud in parallel. Alternatively, the communication link can be implemented using wireless technology.

Abstract: An architecture provides the ability to create and maintain multiple instances of virtual servers, such as virtual filers (vfilers), within a server, such as a filer. A vfiler is a logical partitioning of network and storage resources of the filer platform to establish an instance of a multi-protocol server. Each vfiler is allocated a subset of dedicated units of storage resources, such as volumes or logical sub-volumes (qtrees), and one or more network address resources. Each vfiler is also allowed shared access to a file system resource of a storage operating system. To ensure controlled access to the allocated and shared resources, each vfiler is further assigned its own security domain for each access protocol. A vfiler boundary check is performed by the file system to verify that a current vfiler is allowed to access certain storage resources for a requested file stored on the filer platform.

Abstract: Disclosed is a technique for data synchronization. A first identifier for a portion of data on a primary volume is determined, wherein a unique identifier is associated with each portion of data at the primary volume. A second identifier for a portion of corresponding data at a secondary volume is determined, wherein a unique identifier is associated with each portion of data at the secondary volume. The first and second identifiers are compared. When the first and second identifiers do not match, the portion of corresponding data at the secondary volume in a storage device is replaced with the portion of data at the primary volume.

Abstract: An apparatus, system, and method are disclosed for detecting mismatches in a mirror volume. A receive module receives a start indicator from a primary storage system. The start indicator includes a starting location of a first block to be modified on a track in a secondary storage system. The first block corresponds to an identically located first block of a modified record in the primary storage system. The tracks the first blocks on the primary and secondary storage systems each comprise irregular count key data (“CKD”) tracks. A compare module compares the first block location indicated by the start indicator with block locations listed in track metadata. The track metadata describes user records on the irregular CKD tracks of the secondary storage system. An alert module generates an alert in response to the first block not aligning with a beginning block of a record on the secondary storage system.

Abstract: Methods, devices, and products are disclosed for recording media. An input is received via a user interface to record media. An entry is created in a recording schedule to record the media. The recording schedule is sent to a restoration server, such that the recording schedule is mirrored to the restoration server.

Abstract: A method, for determining sufficiency of a given set of portions included within a storage system (SS) to accommodate one or more flows of data anticipated as flowing therethrough, may include: configuring the given set to include at least one of following portions, a given stable of one or more providers of data-storage (PDSs), and an SS-infrastructure; identifying components within members of the given set as queuing centers according to the one or more flows, respectively; estimating one or more capacity values, based upon the one or more flows, that will be demanded of the components, respectively; and determining whether the estimated one or more capacity values are acceptable in a context of corresponding capacity values attributed to the components, respectively.

Abstract: An indication to allocate storage is received, where the storage is to be used to store previous version data associated with a protected data set. One or more storage groups are allocated of at least a prescribed allocation group size and comprising a set of physically contiguous storage locations.

Abstract: On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.

Abstract: A computing device is partitioned to include a host partition (HP) instantiated at least in part to provide storage capabilities, and also to include a client partition (CP) instantiated at least in part to consume such storage capabilities of the HP in the form of a virtual storage device at the CP. The HP implements the virtual storage device of the CP as an image file on a physical storage device. The image file at the HP is compacted while the CP is active and employing the corresponding virtual storage device.

Abstract: A method for assigning element addresses in an automated data storage library includes determining if a data storage device, such as a tape cartridge, belongs to a particular host's cartridge assignment policy. If so, the data storage device is issued a virtual import/export element address taken from a set of non-common virtual import/export element addresses, if available. If no non-common address is available, then a common virtual import/export element address is assigned to the data storage device. If no addresses, either common or non-common, are available, then the data storage device is queued until an address becomes available.

Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.

Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.

Abstract: Embodiments of a method and system for saving system context after a power outage are disclosed herein. A power agent operates to reduce the possibility of data corruption due to partially written data during an unexpected power outage. The power agent can determine an amount of time remaining before a power store is depleted. Based on the amount of time, the power agent can store system context information. Correspondingly, the power agent can operate to save complete system context, partial system context, or flush (I/O) buffers. Once power is restored, the power agent can restore the system context based on the nature of the save. Other embodiments are described and claimed.

Abstract: A processor includes a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order. The coprocessor interface unit includes a coprocessor store data queue. If data stored in a register of the coprocessor is to be stored in a register file of the execution unit, the data is transferred from the coprocessor to the coprocessor store data queue. A graduation unit coupled to the coprocessor is also provided. The graduation unit provides a signal to the coprocessor that determines whether an instruction executed by the coprocessor is permitted to alter an architectural state of the processor.

Abstract: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

Abstract: Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch instruction group includes a branch type instruction, a branch target is characterized in relation to a fetch boundary, which delimits a memory region contiguous with the memory region that hosts the currently fetched instruction group. Instruction prefetching is included based, at least in part, on the predecoded characterization of the branch target.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.

Abstract: A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file.

Abstract: Many processor architectures include registers in the form of a stacked register file, for holding data used during execution of processing operations. As taught herein, the physical registers forming the stack are organized into banks. One or more of the banks is activated and deactivated, as needed to meet the demands of register allocations.

Abstract: Apparatus and methods of reducing dynamic memory stack by a register stack engine are disclosed. An example apparatus and method identifies a local parameter of a caller function. A scratch register corresponding to the local parameter is moved to the top of a register stack, and a local parameter of a callee function is assigned to the scratch register.

Abstract: A processor system and a processor readable medium, which implement a method for implementing multiple contexts on one or more SPE are disclosed. Code and/or data for a first and second contexts may be respectively stored simultaneously in first and second regions of an SPE's local memory, storing code and/or data for a second context in a second region of the local memory, the SPE may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the SPE may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another SPE's local memory.

Abstract: An apparatus, program product and method sample at different times nodes that are performing similar work. Performance data associated with first and second node subsets performing the similar work are sampled at different times, e.g., in a round-robin fashion, and in accordance with a given sampling rate. The performance data is analyzed. Nodes whose performance suffers as a result of a sampling operation may be identified and removed from a subsequent operation.

Abstract: A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

Abstract: A method and system for controlling timing in a processor is disclosed. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and wherein each instruction has a second default execution time during a second condition; during a first mode, executing the plurality of instructions within a same execution time regardless of whether a condition is the first condition or the second condition; and during a second mode, executing the plurality of instructions within random execution time regardless of whether a condition is the first condition or the second condition. According to the system and method disclosed herein, the method effectively modifies the timing of a processor by controlling and/or minimizing variations in the execution times of instructions.

Abstract: Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

Abstract: The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, even when branch prediction fails, BHR information can be accurately restored. Accordingly, prediction accuracy can be improved.

Abstract: A data processing system 2 is provided which includes an instruction decoder 18 responsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler pointer in dependence upon a handler base address HBA and the index value field and then to branch to that handler pointer position. A handler program 24, 26 at the branch target is then executed following which a return is made to an address following the handler branch instruction using a link address value stored when the handler branch instruction was executed.

Abstract: Embodiments of the invention provide a method and an apparatus to collect and dynamically update system locality information during runtime. In one method embodiment, the present invention collects system locality information at boot time to be provided to an operating system. The system locality information describes distances between devices within an integrated processing system. The operating system is then notified that a triggering event has occurred that may potentially alter the distances between devices within the integrated processing system. Upon receipt of this notification, the operating system invokes an Advanced Configuration and Power Interface (ACPI) procedure that provides updated system locality information during runtime to reflect the changes in distances between devices within the integrated processor system after the occurrence of the triggering event.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: The invention is directed towards routing a packet using both IPSec and common routing protocols within dynamic network topologies in a VPN. The routing of IPSec packets employs Open System Interconnection (OSI) layer three information. In one embodiment, a tree mechanism is used for looking up layer three information that may be associated with a protected subnetwork. When a packet is identified as being associated with a protected subnetwork, the packet may be encrypted and encapsulated, including the original destination and source IP address header information within another packet employing the IP Encapsulating Security Payload (ESP) protocol. New source and destination IP addresses are provided for the new packet using IP addresses associated with an entry gateway and an exit gateway to the VPN. The new packet may then be routed through the VPN using traditional routing protocols.

Abstract: The invention relates to a communication system which comprises at least one user equipment having a plurality of identities associated therewith. The user equipment has means for storing at least one of the identities. Storage means are provided for storing at least one of the plurality of identities and means for receiving identity information from the user equipment, for obtaining from the storage means at least one identity associated with the received identity information and for sending to the user equipment the at least one obtained from the storage means.

Abstract: Under the present invention, when a request for a certificate is made, a set of (mapping) rules are used to identify an appropriate directory and any other information sources, and to retrieve information for the certificate therefrom. The directory name is then transformed using the set of rules for use in the certificate. Thereafter, a template for the certificate is developed using the set of rules. The template and the request are then communicated to the PKI, which will generate and return the certificate. Upon receipt, the present invention can verify that the certificate actually includes the transformed name.

Abstract: For protecting a computer from manipulation of register contents, copies of registers to be protected (6; PC) are created in separate redundancy registers (10a-10c). At each instruction execution, the content of the register to be protected is compared with the copy thereof. The instruction is only executed if there is a match of register contents. If there is a mismatch of register contents, this is interpreted as an indication that the content of the register to be protected has been manipulated, and error handling is performed.

Abstract: Methods, systems, and computer program products that, by defining a common interface, allow for a single implementation of operations common to both kernel mode and user mode processing, relative to a hardware adapter. Corresponding kernel mode and user mode implementations of the operations are provided. For a given process, a call to the common interface is mapped to the kernel mode implementation for kernel mode processes and to the user mode implementation for user mode processes. The mapping may be performed at runtime or may be static. The common operation may provide a user mode process direct access to a hardware adapter, such as for sending and receiving information, without switching to kernel mode. A kernel mode implementation for operations unique to kernel mode processing, such as specifying security parameters for the hardware adapter to enforce, or initiating and terminating communication through the hardware adapter, also may be provided.

Abstract: Provided is a storage system for solving the problem in that, when the registration of a nonexistent user is deleted, only a system administrator can access files that the user left, so that a load placed on the administrator increases at the time of an audit. The authentication program for permitting a user, who is attempting to log in to a storage system, to access a file recorded in the storage system, the program including: a first step for receiving a user name and a password from the user; a second step for referring to a validity term corresponding to a pair of the user name and the password recorded in the storage system; and a third step for permitting access by the user to a file corresponding to the validity term based on a result of the second step, the first to third steps being executed by a processor.