Abstract: Authentication of two devices in communication with a third device is achieved where the first and second devices each possess a shared secret value. The authentication includes communication of authentication values from the first device to the second device using the third device. Similarly, there is communication of values from the second device to the first device using the third device. The third device retains the communicated values. The values are calculated to permit the third device to authenticate the first and second devices without the third device receiving the shared secret value. The authentication may be used to establish a communications channel between the first and the second devices.

Abstract: A method and apparatus identifying an item by attaching a radio frequency identification device to the item; obtaining encryption information; generating an encrypted code from the encryption information by a programmer; inserting the encrypted code into the radio frequency identification device by the programmer whereas the encrypted code may be one of a plurality of encrypted codes; attempting to access the radio frequency identification device by a security reader by transmission of another encrypted code to the radio frequency identification device; and responding with a correct access signal by the radio frequency identification device in response to receipt of the other encrypted code if the other encrypted code is same as the inserted encrypted code.

Abstract: Synchronous validation and acknowledgment of electronic data interchange (EDI) transactions. A connection session on a communication network is established for handling EDI transactions from a source. A collection of EDI transactions is received via the communication network. A receipt acknowledgement is returned to the source indicating the EDI transactions have been received. The EDI transactions are validated as the EDI transactions are received. A validation acknowledgement is transmitted via the communication network to the source before the connection session is terminated. The validation acknowledgement indicates the EDI transactions have been validated.

Abstract: An apparatus for communicating, including a communicating unit that enables the apparatus to communicate with a communications counterparty via the communicating unit. The communicating unit includes a unit for providing an individual certificate that is a digital certificate being provided with information identifying the apparatus for communicating in order to receive an authentication by the communications counterparty when communicating, and a unit for communicating when having been authenticated with the individual certificate by the communications counterparty. The apparatus further includes at least one storage area for storing the individual certificate and a common certificate that is a digital certificate not being provided with apparatus identifying information, in a replacement component as a minimum unit enabled for replacement.

Abstract: Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed.

Abstract: Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. Other methods and systems for encoding/decoding digital watermarks are also disclosed.

Abstract: A method and system for efficiently retrieving secured data by securely pre-processing provided access information, provides data store security based on a single piece of access information, which is generally public, such as the proper name of a business or individual that is used to retrieve mailing address information. The access information is hashed for access to a secured data store and efficient access and low data storage for permutations of input access information are provided by verifying the presence of an entry for the hashed access information in a look-up table. If an entry is found, the data store is accessed using the hashed access information, but if an entry is not found, another look-up table corresponding to another information type may be tried or the input access information permuted and retried.

Abstract: The current society can be referred to as a card society, since people can use various types of cards for a variety of applications. However, card users must always carry a number of cards depending upon the application, and must use different cards according to the purpose, which can bother such users. A memory of an IC chip of an IC card includes a fingerprint information area to verify the identity of a card owner, a personal information area in which personal information of the card owner is classified and recorded with different security levels set up, a company information area in which each company writes information of the company using an “encryption key” unique to the company, and a public organization information area in which each public organization writes information of the public organization using an “encryption key” unique to the public organization.

Abstract: In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

Abstract: A secure hard drive comprises a storage medium that stores encrypted digital content and corresponding encrypted content keys. A public key decryption module receives one of the encrypted content keys from the storage medium and decrypts the encrypted content key using a private key to generate a content key. A block decryption module receives the encrypted digital content corresponding to the one of the encrypted content keys from the storage medium and the content key from the public key decryption module and decrypts the encrypted content using the content key. The storage medium is a magnetic storage medium. The public key decryption module and the block decryption module are implemented by a system on chip (SOC). A content player receives the decrypted digital content from the block decryption module and generates at least one of an analog output signal and a digital output signal.

Abstract: Embodiments of methods and apparatus for providing integrity protection for management and control traffic of wireless communication networks are generally described herein. Other embodiments may be described and claimed.

Abstract: A processing system may include a first processing unit for a first partition and a second processing unit for a second partition. To support power management, an interrupt handler in the processing system may receive a standby command from an operating system. In response to receiving the standby command, the interrupt handler may cause the first processing unit to transition into a reduced power mode. After the second partition detects a wake event, the second partition may cause the first processing unit to transition out of the reduced power mode. In an example embodiment, the interrupt handler executes within the first partition, and the first processing unit transitions into the reduced power mode by entering an idle loop within the interrupt handler. The first partition may determine from within the idle loop whether the first partition has been released from the low power state. Other embodiments are described and claimed.

Abstract: A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number.

Abstract: When a plurality of electric devices is charged, each electric device is charged by priorities. The data processing apparatus related to the present invention comprises; a first data processing unit which comprises a first memory, a first data control section and a first battery; a second data processing unit which comprises a second memory, a second data control section and a second battery. The first data processing unit and the second data processing unit can be mechanically attached to and removed from each other.

Abstract: A method and an apparatus for switching performance are provided. The method includes: providing a performance adjustable circuit working at a specific threshold frequency; determining a working power supply of the performance adjustable circuit; when the working power supply is higher or lower than a specific threshold level range corresponding to the specific threshold, adjusting the performance adjustable circuit to work at another specific threshold frequency.

Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Abstract: In one embodiment, a method for reducing power consumption at a cache includes determining a nonuniform architecture for a cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to reduce power consumption at the cache. In another embodiment, the method also includes determining a code placement according to which code is writeable to a memory separate from the cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to further reduce power consumption at the cache.

Abstract: Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.

Abstract: In a method for managing power consumption among compute nodes having respective power components, an increase in the power utilization of a first compute node of the compute nodes may be detected. In response to a detected increase, a sum of the power consumption levels of the compute nodes and the requested increase in power utilization of the first compute node is compared with an allowable power budget for a compute node pool. In addition, the power state of the first compute node power component is varied in response to the comparison.

Abstract: A PCI Express system and a method of transitioning link state thereof. The PCI Express system includes an upstream component, a downstream component and a link. The upstream component and the downstream component transmit data to each other via the link. When at least one of the upstream component and the downstream component stops data transmission under a normal working state and if the system idle time period reaches a threshold idle time, then transiting the link into a second link state.

Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

Abstract: The invention relates to electronic devices for generating synchronization signals, in particular to ultrahigh resolution synchronization signals whose temporal accuracy is less than a nanosecond. The inventive device operates not only with an internal clock but also with the external clock of a synchronizable device, thereby avoiding any temporal drift and uncertainty of the synchronization signals. The main element of the device is embodied in the form of a programmable digital component which operates with the external clock frequency and comprises programmable delay lines enabling to attain ultrahigh temporal resolutions. Said invention also relates to a system comprising several synchronization devices which are interconnected in such a way that the synchronization of different devices remains perfect. The invention makes it possible to control with high accuracy a quasi-unlimited number of devices.

Abstract: A method, apparatus and computer instructions for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.

Abstract: The claimed subject matter provides a system and/or a method that facilitates re-locating a web application associated with a network service utilizing a portion of serialized data. The network service can be any collection of resources that are maintained by a party (e.g., third-party, off-site, etc.) and accessible by an identified user over a network (e.g., WAN, Internet, etc.). A receiver component can receive a request for initiating and execution of a process that is maintained by the network service. A servicing component can analyze representations of multiple processes within the network service and determines whether to enable initiation and execution of the process based at least in part upon the analysis.

Abstract: A computing services grid. The grid can include a service desk coupled to one or more computing service instances. Each service instance can conform to an interface which is common to all service instances in the grid. A routing component can be disposed in the grid. Specifically, the routing component can route individual service requests to individual ones of the service instances. An instance selection service is used to satisfy QoS characteristics associated with the requester of the service. The grid further can include a service instance monitoring component. The monitoring component can monitor the performance of individual service instances charged with processing individual service requests. Fail-over logic can be configured to re-route service requests from selected service instances to others of the service instances where the monitoring component detects a fail-over condition in the selected service instances.

Abstract: A system such as a Web-based system in which a plurality of computers interact with each other is monitored to detect online an anomaly. Transactions of a service provided by each of a plurality of computers to another computer are collected, a matrix of correlations between nodes in the system is calculated from the transactions, and a feature vector representing anode activity balance is obtained from the matrix. The feature vector is monitored using a probability model to detect a transition to an anomalous state.

Abstract: Handling failure of a primary group at a first data center that is part of plurality of data centers providing triangular asynchronous replication includes creating a data mirroring relationship between at least one storage volume at a second data center having a synchronous backup group that is part of the plurality of data centers and at least one storage volume at a third data center having an asynchronous backup group that is part of the plurality of data centers and resuming work at the third data center. Handling failure of a primary group at a first data center may also include synchronizing the at least one storage volume at the second data center with the at least one storage volume at the third data center prior to resuming work at the third data center.

Abstract: The present invention provides a system, method, and computer program product for partially pre-writing data stored in an array of mass storage devices to a spare disk dedicated to the array prior to detecting a failure in the array. The system then reconstructs data from the failed disk using data partially pre-written to the spare disk. Since some of the data has already been pre-written to the spare disk, embodiments of the present invention reduce the number of I/O operations performed by a storage system during a process of reconstructing data from the failed disk to the spare disk.

Abstract: Systems and methods for automating database table and application data collection into one process to facilitate remote diagnostics of a computer problem are disclosed. A customized batch file is created by a remote support technician that can be run on a user computer that has the actual data to be gathered for the computer problem to be diagnosed. An output data file is created by the running batch file compiling problem diagnosis data from the user computer. The data file can then be viewed via a single viewing process that displays the application and database data of the data file through a single GUI and allows easy viewing manipulation of that data through the GUI. Because the database table data may be saved in a string delimited format with table field names saved with it, the database program is not needed in order to view the tables.

Abstract: A method for automated software debugging includes steps of: receiving an interface configured for accessing a program; receiving a behavioral model of the program; receiving a failing input sequence from the program; executing the failing input sequence on both the behavioral model and the program; validating, after each executing step, an expected behavior of the program by executing specially constructed test sequences from the behavioral model; performing model mutation for creating a hypothesis of faulty behaviors; verifying hypothesized faulty behaviors; and scoring hypothesized faulty behaviors for producing a ranked list of diagnoses. The method also includes a step of presenting the ranked list of diagnoses to a user.

Abstract: A display device having electronic album function and the method thereof is disclosed. The present invention includes an Electronic Photo Frame (EPF) controller which checks the existence of the memory and reads image data from the memory if any, an interface device which converts the interface format of the image data from the EPF controller, transmits it to main controller and sends interrupts to the main controller when there is a transmission error, and a counter which counts the number of interrupts transmitted to the main controller. When the number of interrupts with the same clock exceeds a predetermined number, the main controller ignores the interrupts, resets the interface device and reloads the image data from the memory. Otherwise, the main controller performs the regular interrupt routine.

Abstract: Network state information and network topology information associated with a network is retrieved and transformed using a meta-language. The transformed data is compared against known network fault patterns to identify a matching network fault signature. The matching network fault signature is used to diagnose potential cause(s) of network problems that resulted in the matched signature.

Abstract: Having detected an anomalous fault in a peripheral I/O slot, a processor entity may need to perform some remedial action, wherein the peripheral slot may have a fault line. First a voltage may be detected on the slot. Processor entity may set a fault if a voltage is found. A hotplug controller which may provide outputs that the processing entity may store as a fault syndrome word. The service processor or operating system, either during initial program load, or at another time, may detect that the fault could be a false fault depending on a set of predefined conditions and following the mechanism described here can then clear the fault earlier set. If an action from a previous device list is set, then there may be a clearing of the voltage fault based on determining that the action is set.

Abstract: A trace controller receives data access information during load instruction execution and ID (AID) of a load/store buffer to store the data access information during load instruction execution. Then, it generates trace control information TC based on the received data access information and selects a buffer to store the generated trace control information from a plurality of trace control buffers according to the received AID. After that, it receives read data information after load instruction execution and ID (RID) of a load/store buffer used for load instruction execution. Finally, it selects a buffer storing the trace control information TC from the plurality of trace control buffers according to the RID.

Abstract: Automatic Protection Switching (APS) and error signal processing coordination apparatus and methods are disclosed. If a communication module that enables communication signals and error signals to be exchanged with a remote communication module is configured in an APS protection group, error signal processing by the communication module is restricted. This prevents Time Division Multiplexing (TDM) T1/E1 Remote Defect Indication (RDI) signal processing, for example, from interfering with Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) unidirectional One-plus-One APS. Under certain conditions, however, a restricted communication module may be allowed to perform a restricted error processing operation or revert to normal unrestricted error signal processing.

Abstract: A method for assisting a user to connect a problem with a device, such as a printer includes extracting, from records comprising user actions on the device, string of user actions on the device. The string of user action is compared with at least one predetermined sequence of user actions for correction of predefined problem with the device. Based on the comparison, an evaluation is made as to whether at least one prior user has attempted the predetermined sequence and, if so, a procedure is implemented to avoid a user repeating the prior attempt.

Abstract: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.

Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: The present invention provides a programmable logic device including a main circuit unit capable of variably building desired user logic, based on configuration data inputted from a storage device, and a configuration data monitor unit for monitoring configuration data stored in the storage device.

Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test.

Abstract: A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: A method and apparatus for assigning automatic repeat request (ARQ)/hybrid-automatic repeat request (H-ARQ) processes in a wireless transmit/receive unit (WTRU) to support enhanced uplink (EU) data transmissions. After parameters associated with the ARQ/H-ARQ processes are configured, the WTRU assigns an ARQ/H-ARQ process for selected data. After transmitting the data, the WTRU determines whether feedback information for the data has been received. The WTRU releases the ARQ/H-ARQ process if an acknowledgement (ACK) message has been received, and retransmits the data if a non-acknowledgement (NACK) message or no feedback information has been received in a predetermined time period while incrementing a transmission counter in the WTRU. When an ARQ/H-ARQ transmission limit has been reached, the WTRU may discard the data or reinitiate the transmission.

Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.

Abstract: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Abstract: A disk drive is disclosed comprising a disk, a buffer memory, and control circuitry operable to receive a write command from a host, wherein the write command comprises write data and a write data address. Write EDC data is generated in response to the write data and the write data address, wherein the write data and the write EDC data are stored in the buffer memory. The write data is read from the buffer memory, and write check data is generated in response to the write data and the write data address. The write EDC data is read from the buffer memory and compared to the write check data to detect a write error. If the write error is not detected, the write data is written to the disk without writing the write EDC data to the disk.

Abstract: A transmitter for a dog training system, the transmitter having a command input device for inputting a training command input into the transmitter, and a transmitter controller connected to the command input device. The transmitter controller translates the training command input into identification data and command data. The transmitter controller also generates at least one forward error correction codeword from the identification data and the command data.

Abstract: A digital multimedia broadcasting (DMB) reception apparatus receives DMB service in a mobile communication system. In the DMB reception apparatus, a Reed-Solomon (R-S) decoder receives a coded broadcast signal and outputs an error symbol with a transport error indicator bit, if all data bits in the symbol are ‘0’. A moving picture experts group (MPEG) decoder discards the error symbol.

Abstract: A method and an apparatus is provided for producing branch metrics in a LogMAP turbo decoding operation. During a forward recursion of a trellis, a set of primary branch metrics is generated. The primary branch metrics are stored in receiver form in a relatively small memory cache module and corresponding secondary branch metrics are produced by negating the primary branch metrics. The primary branch metrics and the secondary branch metrics constitute all possible branch metrics for a given state in the trellis. During a backwards recursion of the trellis, the stored primary branch metrics are retrieved from the memory cache module and the secondary branch metrics are regenerated by negating the retrieved primary branch metrics.