Abstract: To enable easy and quick identification of the location of a fault in a virtualized environment, a physical server 20 is communicatively connected with a management server 10 accumulating and storing a first event history of a history of events having occurred in the virtual server 212 and a second event history of a history of events having occurred in the physical server 20. On receiving an event relating to a fault of a business process 2122 operating in the virtual server 212, the management server 10 searches the event histories as accumulated and stored for the second event history on the virtual server 212 having transmitted the same event and the first event history obtained from the table as stored on the physical server 20 implementing the virtual server 212 having transmitted the event, and identifies a cause of the fault based on a result of the search.

Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

Abstract: The present disclosure is directed toward a method for restoring a computer processor to a previous state. Described is a processor/memory architecture that may store successive instructions/data into a pushdown stack. As instructions are loaded and executed, the loading and executing of new instructions may be suspended. The instruction execution and memory stack then may be restored to a previous processor state in terms of instructions, processor memory state, register values, etc.

Abstract: An electronic device is connected to a loop transmission line via a bypass circuit and detects being bypassed from the loop transmission line. Each electronic device connected to a looped transmission line via each bypass circuit receives a positioning map in which an own address is registered, and judges whether the own address is still registered. The electronic device can judge whether this electronic device is being bypassed from the loop transmission line by the bypass circuit using a conventional sequence.

Abstract: Methods and systems are provided for detecting temporal relationships that are uniquely associated with a selected root cause. The method comprises identifying error codes associated with a root cause, wherein each error code comprises a plurality of event indicators and temporal data describing when the event indicator was generated, analyzing each of the error codes to detect a combination of event indicators that is associated with error codes corresponding to the selected root cause and to a non-selected root cause, and detecting a temporal relationship involving the combination of event indicators, wherein the temporal relationship is uniquely associated with error codes corresponding to the selected root cause.

Abstract: A context analyzer may be configured to receive, from a software support system associated with a software application associated with multiple architectural layers, an incident report associated with a software incident of the software application. The incident report may include context information associated with the software application at the time of the software incident, the context information being received from a plurality of context providers. An incident model generator may be configured to determine, from parsed context information output by a first context parser and a second context parser, a plurality of entities and links therebetween associated with the software application, and configured to display an incident model that includes the entities and the links and that provides access to the parsed context information on an entity-specific basis.

Abstract: A system or method for automated management of compliance of a target asset to a predetermined requirement including receiving a predetermined requirement for compliance testing of one of a plurality of assets, comparing the received predetermined requirement to one or more stored compliance requirements to identify whether one or more stored compliance requirements corresponds to the received predetermined requirement, selecting a target asset from among the plurality of assets, transmitting the new compliance requirement, receiving results responsive to the transmitted new compliance requirement, and validating the received results to determine compliance of the target asset with the predetermined requirement as identified in the received results.

Abstract: A method in one embodiment includes detecting an identifier of a drive that has written data to a data storage medium; performing a data transfer operation to read the data from the data storage medium; monitoring the data transfer operation for detecting temporary errors; determining whether an error burst has occurred based on the monitoring; and if an error burst has occurred, altering a condition of the data transfer operation, the alteration being selected based on the identifier of the drive that wrote the data to the data storage medium. Additional methods and systems are also disclosed.

Abstract: The general field of the invention is that of viewing systems that have to display information or images having different criticality levels. The viewing system according to the invention comprises at least one secure graphic manager with a criticality level at least equal to the highest criticality level of the graphic applications. The manager has the following detection means: violation of the segregation of the applications in their respective display window; overrunning of the processing times of each application; and violation of the specific storage spaces of the graphic applications.

Abstract: An apparatus, system, and method are disclosed for automated data determination propagation. A data package source collects data and compiles the data into data packages. A local data package prioritization module determines a prioritized order of the data packages based on a local priority matrix. The local data package prioritization module sends the data packages in the prioritized order over a temporary data connection to a central data package prioritization module. The local data package prioritization module updates the local priority matrix over the temporary data connection based on a central priority matrix. The central data package prioritization module receives the data packages and makes one or more updates to the central priority matrix based on the data packages.

Abstract: A storage medium recording an information reacquisition procedure generation program causing a computer to execute a process of generating a reacquisition procedure for reacquiring information, the information reacquisition procedure generation program causing the computer to execute a method comprising: reading a message history from a storage unit storing the message history recording a series of messages exchanged to and from a device providing information until the information is provided; generating a message transitional relationship with respect to the information by extracting a parent-child relationship between the respective messages contained in the series of messages based on the series of messages until the information contained in the read message history is acquired as well as by combining the same or similar messages of the series of messages into one; and outputting the reacquisition procedure with respect to the information based on the generated transitional relationship.

Abstract: An invention is provided for managing non-volatile memory having a plurality of memory blocks and a plurality of error values associated with the memory blocks. The method includes recording an error value indicating a number of errors occurring in a memory block during an operation accessing the memory block. The error values can then be aggregated to calculate an overall health of the memory, or used individually, for example, by selecting a memory block for a memory operation based on the associated error value. In general, the error value is updated when the most recent number of errors occurring in the memory block during an operation accessing the memory block is greater than a current recorded value.

Abstract: A user interface displays multiple steps in sequential relationship to each other, and may group various steps together and provide completion indicators for each step as well as an overall completion indicator. Error conditions, status information, queries, and details about a particular step or group of steps may be displayed inline with the steps in a task detail portion of the user interface. The task detail portion may be collapsible and expandable by the user. Progress and completion indicators may be updated for each step, groups of steps, and the overall sequence. In a typical use, a software installation sequence may comprise installation steps from multiple software components. The user interface may illustrate the status of individual tasks, groups of task, and the overall sequence as the tasks are performed, and enable errors to be resolved by displaying queries and other information inline with the steps.

Abstract: As set forth herein, a system identifies soft failures of devices. An interface captures transactional data between one or more users and one or more devices within the system. A data log receives the transactional data from the interface and stores the data as historical data for subsequent retrieval. A warning system evaluates the historical data in the data log to identify one or more devices that have a soft failure condition, wherein an alarm is output for each soft failure identified. A display module combines the historical data from the data log and one or more alarms from the warning system into a single display for review.

Abstract: An apparatus, system, and method are disclosed for data priority determination. A receiving module receives a data package. A parsing module parses out priority indicators from the data package. A comparison module compares the priority indicators to entries in a priority matrix, determining whether the data package is of a defined data package type. In response to a determination that the data package is of the defined data package type, a priority determination module determines a data package priority of the data package based on a data package priority of the defined data package type. In response to a determination that the data package is not of the defined data package type, a type definition module defines a new data package type having a data package priority based on the priority indicators. A priority update module updates the data package priority of the defined data package type.

Abstract: An electronic device including: a memory unit in which a plurality of error information is stored; and a control unit selecting from among the plurality of error information, an error information such that at least one of a type and a frequency of the error that occurred satisfies/satisfy a predetermined condition, the control unit also making the memory unit save the error information.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.

Abstract: A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: A shared diagnosis method may be for an electronic integrated system embedding a plurality of memory units associated with Built In Self Test (BIST) hardware portions for executing a test on memory locations of the memory units. A FAIL signal may be provided from the hardware portions, together with the memory locations of the memory units on which the test is executed. The method may include loading of address, state and data signals, generated during the test on the memory locations, in a series of bitmapping registers and supplied by multiplexer devices, which receive as inputs the address, state, and data signals from the memory units and from the hardware portions. The enabling for the loading of the bitmapping registers is through the processing of a Fail signal in a counter supplied by a multiplexer device receiving the Fail signals from the hardware portions.

Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

Abstract: Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.

Abstract: Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects test vectors that cause a prescribed characteristic of the device under test, which is to be measured when test signals that are each based on one of the test vectors are supplied to the device under test, to fulfill a preset condition; and a judging section that judges pass/fail of the device under test based on measured values of the prescribed characteristic of the device under test supplied with the test signal based on the test vectors selected by the vector selecting section.

Abstract: A method and apparatus for power control of the re-transmission data packet in a wireless communication system is disclosed. A first wireless communication device is provided that receives (210) a data packet from a second wireless communication device and determines (220) if the data packet is correctly decoded. If the data packet is not correctly decoded, the first wireless communication device calculates (230) a first re-transmission power required for correctly decoding the data packet based on a signal to noise ratio (Eb/No) versus frame error rate (FER) relationship. And further calculates a power difference (240) between the calculated re-transmission power and the power of the received data packet and transmits the power difference (250) to the second wireless communication device. The second wireless communication device calculates (340) a second re-transmission power based on the received power difference and re-transmits (350) the data packet at the calculated re-transmission power.

Abstract: In some embodiments, a mobile device includes interface to receive multicast and broadcast service (MBS) signals and to transmit uplink signals, The mobile device also includes logic to detect errors in the transmission of the received MBS signals and provide negative acknowledge (NACK) signals indicating at least some of the errors in a contention-based MBS feedback channel in at least some of the uplink signals. Other embodiments are described.

Abstract: An information processing apparatus that receives image data sent from a sending apparatus in packet communications, the information processing apparatus includes: a receiving unit adapted to receive a packet for transmitting the image data; a detecting unit adapted to detect a transmission error in the packet; and a sending unit adapted to send a retransmission request for a packet in which the detecting unit has detected a transmission error to the sending apparatus; wherein, when the detecting unit has detected a transmission error in a packet that corresponds to a region of interest that has been preset in the image data, the sending unit sends a retransmission request for the packet with a higher priority than a transmission request for a packet that does not correspond to the region of interest.

Abstract: A method of handling a hybrid automatic repeat request (HARQ) process for semi-persistent scheduling (SPS) in a user equipment (UE) of a wireless communication system is disclosed. The method includes steps of configuring an SPS functionality which utilizes at least one HARQ process; receiving a first new data indicator (NDI) addressed to an SPS cell radio network temporary identifier (SPS C-RNTI) of the UE for a first HARQ process of the at least one HARQ process; and considering the next transmission to be received by the first HARQ Process as a first transmission of the first HARQ Process when receiving a second NDI addressed to a C-RNTI of the UE for the first HARQ process.

Abstract: A system and method for rate matching to enhance system throughput based on packet size is provided. A method for transmitting information includes encoding a block of N bits, where N is an integer, demultiplexing the encoded block of N bits into at least one subblock of systematic bits and at least one subblock of parity bits, and permuting the at least one subblock of systematic bits and the at least one subblock of parity bits to generate at least one permuted subblock. The method also includes forming at least one output block from the at least one permuted subblock, computing a starting position of a redundancy version for a hybrid automatic repeat request (HARQ) transmission based on a relationship between N and a threshold, and transmitting the redundancy version. The redundancy version begins at the computed starting position and ends when a specified number of bits has been transmitted.

Abstract: A data retransmission method for a radio communication system, in which a plurality of data streams are transmitted from a plurality of transmission systems, the method includes when there is a transmission error in transmission data in any of the plurality of data streams, adaptively selecting beamforming or spatial coding for retransmission of the transmission data; and retransmitting the transmission data with transmission errors by using either of selected beamforming or spatial coding, wherein a criterion for adaptively selecting the beamforming or spatial coding is that by comparing a retransmission period with a prescribed fading speed, the beamforming is selected when the retransmission period is smaller than the prescribed fading speed, while the spatial coding is selected when the retransmission period is smaller than the prescribed fading speed.

Abstract: A method and system for large data transfer between a sender and a receiver. The sender transmits to the receiver a plurality of data packets in sequence. The time elapsed for each of the plurality of data packets after transmission of said each of the plurality of data packets is determined. The receiver transmits a message from the receiver to the sender notifying the sender that an identified one of the plurality of the data packets is missing. The sender retransmits to the receiver the identified one of the plurality of data packets only when the elapsed time determined for the identified one of the plurality of the data packets is greater than a predetermined time interval.

Abstract: A method constructs a code, wherein the code is a large-girth quasi-cyclic low-density parity-check code. A base matrix is selected for the code. A cost matrix corresponding to the base matrix is determined. A single element in the base is changed repeatedly maximize a reduction in cost. A parity check matrix is constructing for the code from the base matrix when the cost is zero, and an information block is encoded as a code word using the parity check matrix in an encoder.

Abstract: A regular quasi-cyclic matrix is generated in which specific regularity is given to cyclic permutation matrices. A mask matrix capable of supporting a plurality of encoding rates is generated. A specific cyclic permutation matrix in the regular quasi-cyclic matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix with an LDGM structure is generated in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

Abstract: A storage device stores identification information for identifying a pseudo-uncorrectable error sector, which is treated in a pseudo manner as a sector including an uncorrectable error, in the pseudo-uncorrectable error sector. The storage device further performs data processing on the sector by using the identification information stored in the sector. Moreover, the storage device stores log process information indicating whether an error log is registered in the pseudo-uncorrectable error sector in an error process related to the uncorrectable error that is treated to be included in a pseudo manner in the pseudo-uncorrectable error sector. In addition, the storage device performs data processing by using the log process information and the identification information.

Abstract: Exemplary embodiments of the invention provide a generalized Turbo principle that enables the exchange of region beliefs between components. The generalized Turbo principle provides various advantages over the traditional Turbo principle such as, for example, a lower Bit Error Rate (BER) and/or a better quality of the end-result marginals. In one exemplary embodiment, a method includes: receiving an encoded signal (501); and decoding the received signal using a generalized Turbo principle wherein region beliefs are exchanged between components (502). In another exemplary embodiment, methods, computer programs and apparatus are presented for generating a graph structure for a system having a plurality of components. As a non-limiting example, the generated graph structure may be seen to correspond to the region graphs underlying the generalized Turbo principle.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. An embodiment of a decoder includes means for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

Abstract: A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors. Also described is a method of operation in the memory system.

Abstract: A control method is for controlling a storage device that writes data in a storage medium including a plurality of groups each having a plurality of sectors and a redundancy sector in which error correction information is stored to perform error correction on data stored in the sectors per each of the groups. The control method includes: rewriting data stored in the sectors included in one of the groups; and writing invalidation data indicating that the error correction information is invalid in the redundancy sector if the error correction information stored in the redundancy sector of the one of the groups has not been rewritten.

Abstract: Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.

Abstract: Methods and apparatuses to model the relation between the delay samples and congestion losses and to protect media flows against congestion losses are disclosed. In one embodiment, the method comprises measuring congestion by delay samples, and performing a dynamic FEC algorithm that uses convex hull clustering for loss-event classification, including determining an FEC rate according to the loss-event classification. In another embodiment, the method comprises measuring congestion by delay samples, modeling loss events associated with the delay samples by grouping loss events as unions of convex hulls to identify a period of potentially increased congestion, dynamically changing the FEC rate based on the modeling, and applying FEC protection to the media flow during the period based on the FEC rate.

Abstract: A method and device for adjusting communications power are used for detecting a communications condition between a connection port and a connection target, and a communications-supporting power of the connection port that includes at least one of a transmitting power and a receiving power is adjusted according to a detected communications condition. Therefore, accuracy of data transmission and reception is ensured, and power used for data transmission and reception is reduced.

Abstract: In a method of decoding data symbols into codewords, reliability information of the data symbols is provided. A first group of symbols from a first set of groups of symbols is selected, wherein the first set of groups of symbols is defined by at least a first parity-check of a parity-check matrix of a linear block code which has been used to encode the data symbols. The selection is based on the reliability information. A second group of symbols from a second set of groups of symbols is selected, wherein the second set of groups of symbols is defined by at least a second parity-check of the parity-check matrix. The selection is based on the selected first group of symbols and the reliability information. At least a part of the codeword is composed on the basis of the first group of symbols and the second group of symbols.

Abstract: Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in units of mp (a multiple of p) symbols; mp generator polynomials are used; and the generator polynomials gj(x) are selected such that a coefficient of degree deg(gi(x)) of x becomes zero for all gi(x) lower in degree than that and circuits in which these generator polynomials gj(x) are combined are connected with each other.

Abstract: Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.

Abstract: A-decoding-apparatus includes first-equalization-unit configured to obtain an-equalized-bit-string subjected to hard-decision by equalizing the-input-signal, and to obtain reliability-value-data as soft-decision which is indicating reliability of the-hard-decision with respect to each bit of the-equalized-bit-string, second-equalization-unit configured to obtain a plurality of candidates of the-equalized-bit-string subjected to hard-decision by equalizing the-first-signal, conversion-unit configured to covert the-reliability-value-data corresponding to the-candidates of the-equalized-bit-string, decoding-unit configured to obtain a-bit-string by performing error-correction decoding by using the-converted-reliability-value-date as soft-decision on the-reliability-value-data, determination-unit configured to determine whether the-bit-string obtained by the-decoding-unit contains an-error, and control-unit configured to control the-conversion-unit and the-decoding-unit based on determination-result obtained by t

Abstract: Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first CSUM; error checking the received data block in a second sequence using a second polynomial, using the first CSUM as a second predetermined initial error checking state, producing a second CSUM; comparing the second CSUM to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.

Abstract: An apparatus (1) for implementing a cyclic redundancy check (CRC) error detection methodology to compute a CRC error detection code for data according to the methodology, comprising computation means (2) which uses parallel computation (4) to compute the CRC error detection code, and configurator means (3) which uses the CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and configures (25) the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of a CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.

Abstract: Provided are a communication apparatus and a method therefor that are capable of executing a checksum attachment processing without increase of a circuit scale. A data generating unit (for example, a CPU) that forms a communication apparatus generates data, and stores the data in a memory. A checksum processor calculates a checksum for the data read from the memory, and writes the checksum into a predetermined position in the data stored in the memory. A data sending unit (for example, a transmission processor, a MAC processing circuit, and a PHY processing circuit) reads the data having the written checksum from the memory, and sends the data to a network.

Abstract: A method begins by receiving at least a portion of a merchant master file. The method continues, for a merchant data file, by determining whether a corresponding merchant profile record exists within a merchant profile database. The method continues, when the corresponding merchant profile record exists in the merchant profile database, by comparing the merchant data file with the corresponding merchant profile record. The method continues, when an inconsistency exists between the corresponding merchant profile record and the merchant data file, by determining status of the merchant data file with respect to the at least a portion of the merchant master file. The method continues, when the status of the merchant data file is a first status level, by generating an inconsistency message that identifies the inconsistency.

Abstract: A system for analyzing an information system comprising a computer readable medium; and a set of computer readable instructions embodied in the computer readable medium for transmitting an audit application to a first store controller so that the audit application can generate audit data representing audit information from the first store controller, receiving audit data from the first store controller, transmitting an audit application to a second store controller so that the audit application can generate audit data representing audit information from the second store controller, receiving audit data from the second store controller, determining a comparison basis according to the audit information from the first store controller, comparing the audit date from the second store controller to the comparison basis, generating a set of comparison data resulting from the comparison, displaying items from the second store controller that are different from the comparison basis.