Abstract: A data processing control unit for controlling two or more data processing operations SMI1,SMI2. The data processing control unit may include a control memory in control data may be stored which represents information about access to a main memory by the two or more data processing operations. A control data controller may be connected to the control memory. The control data controller may include a control data controller input or receiving an access request from one or more of the data processing operations. The control data controller may modify the data in the control memory upon receiving the access request. A process controller may be connected to the control memory. The process controller may control at least a part of the data processing operations SMI1.SMI2 based on a comparison of data in the control memory with a criterion.

Abstract: When a plurality of disk control apparatuses function as one disk control apparatus with a mutual connecting network, a processor is used as an independent resource. Moreover, states of use of resources are monitored, and processing from distribution of the resources to allocation of control tasks is optimized promptly so as to be compatible with a user request. By promptly making system performance compatible with the user request according to the present invention, a state in which the user request and the system performance are alienated from each other for a long time is eliminated.

Abstract: A backup method that uses snapshot delta views to create backups of a data collection is provided. The method comprises taking a first snapshot of the data collection, in response to determining that a previous snapshot used to create a backup does not exist; creating a backup of the data collection using the first snapshot, in response to determining that the previous snapshot does not exist; recording that the first snapshot was used as a source for the creation of a backup; and taking a second snapshot of the data collection, in response to determining that the previous snapshot that was used as a source for a backup does exist.

Abstract: A computer system includes a first volume that is read and written from a first computer and in which write data is written, a second volume that stores journal data in the first volume with the journal data delimited at each predetermined point, a third volume as a virtual volume, a virtual-volume creating unit that creates, when a backup instruction for the first volume at a predetermined point is received, the third volume from which a second computer can read the journal data and in which the second computer can write the journal data, a mapping unit that maps the journal data to the third volume, and a backup unit that transfers the write data to a storage device via the second computer or transfers, through the third volume to which the journal data is mapped by the mapping unit, the journal data to the storage device via the second computer and backs up the write data and the journal data.

Abstract: Provided is a computer system, comprising a storage system and a management computer. The management computer manages differential copy start times, differential data amounts of first pairs, and a data amount that can be copied in differential copy per unit time; identifies one of the first pairs for which the differential copy is to be started and a start time of the differential copy; subtracts the data amount of differential copy per unit time that is allocated to the identified one of the first pairs from a differential data amount of the identified first pairs; add the unit time to the identified start time; judges that the differential copy has been finished at a time when the subtracted differential data amount reaches zero or less; and calculates time zones in which the first pairs execute differential copy based on the time at which differential copy has been finished.

Abstract: An encryption for a distributed global online backup system with global two-stage deduplication in the absence of an indexing database where data blocks are encrypted using their SHA-1 signatures as encryption keys.

Abstract: A switch connectable between hosts and storage device, the switch for providing a service of allotting virtual areas to be deployed in the storage device to any of the hosts upon demand, the switch includes: a processor for controlling allotment of virtual areas to the hosts and allocation of physical areas of the storage device to the virtual areas; and a memory for storing information of the host allowed access to the virtual areas, the processor controlling access by any of the hosts to the virtual area so as to restrict access by any of the hosts to a part of the virtual areas allotted to the any of the hosts in reference to the memory.

Abstract: A backup apparatus and method which stores backup data into a backup data storage area includes detecting whether to increase a capacity of the backup data storage area, assigning a storage area, within an addition-source area set as a storage area permitted to be additionally assigned as the backup data storage area, when a storage area the capacity of which is to be increased is detected, detecting whether to increase the capacity of the addition-source area, and setting the addition-source area in a free storage area as the backup data storage area when detecting that the capacity of the addition-source area is to be increased.

Abstract: A method, apparatus, and software product allow signalling toward a multi-channel memory subsystem within an application processing architecture, and routing of that signalling via a single sandbox which provides memory protection by controlling memory usage and blocking the signalling if it is unauthorized. The signalling via the sandbox leads to a plurality of different memory locations, and the sandbox is an intermediary for substantially all execution memory accesses to the multi-channel memory subsystem.

Abstract: Systems and methods for data swapping in a storage network are provided. The method comprises associating a flag with a first track on a first volume (TA1) and a first track on a second volume (TB1) to indicate that I/O access to TA1 is to be redirected to TB1, and that I/O access to TB1 is to be redirected to TA1; locking TA1 and TB1 to prohibit I/O access to TA1 and TB1; copying data stored on TA1 and TB1 to cache; swapping data between TA1 and TB1; unlocking TA1 and TB1 to allow I/O access to TA1 and TB1; redirecting I/O access to TB1, in response to receiving an I/O request to access TA1, when TA1 is flagged, and redirecting I/O access to TA1, in response to receiving an I/O request to access TB1, when TB1 is flagged.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.

Abstract: A method for managing memory of a mobile phone provides a memory allocation table for images captured by a camera module of the mobile phone. The memory allocation table records memory allocation information of the images. All application programs of the mobile phone can load the image in one memory space allocated for the image according to the memory allocation information in the memory allocation table.

Abstract: An externally-connected volume of a main storage is correlated to an AOU volume inside of an external storage. The AOU volume is allocated with a not-yet-used page in a pool in accordance with data writing. When a command is issued to the externally-connected volume for formatting or others, a first controller in the main storage converts the command into a format command or an area deallocation command with respect to the AOU volume in the external storage. As such, the external AOU volume is subjected to a write process in its entirety, thereby being able to prevent any unnecessary page allocation. With such a configuration, the storage system of the present invention can use pages in the pool with good efficiency.

Abstract: An adaptive buffer device includes a plurality of entries each including an address field and a record block, and a control unit for selectively setting each entry to one of a normal status and a transformed status. When the control unit sets a first one of the entries to the normal status, the address field thereof records a first address, and the record block thereof records data corresponding to the first address and data corresponding to addresses adjacent to the first address. When the control unit sets a second one of the entries to the transformed status, the control unit reconfigures the address field and the record block thereof into a plurality of units, each of which includes a second address, data corresponding to the second address, and data corresponding to addresses adjacent to the second address. In addition, an adaptive buffer method is also disclosed.

Abstract: The management of a data storage system. The system may store data objects that are subject to change in container sets. The data storage system uses location maps to map the data objects to a corresponding container. When there has been, or will be, a change in the availability of containers, a new location map is created which maps the data objects to a new potentially overlapping set of containers. New data objects are added to the new set of containers, and a data object is found by searching all location maps. As an alternative or as an addition to this system, data objects may be stored in a manner that they may be efficiently removed when a condition is met. A container is created which stores all data objects to be removed when the condition occurs. When the condition occurs, the container is removed.

Abstract: A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

Abstract: A method, apparatus, and computer program product are used for reading from a table that splits a plurality of physical addresses between a plurality of channels. One of the physical addresses is determined based at least partly on a virtual address used by an execution device such as the hardware environment, and based at least partly on information about a channel. Then, the physical address is provided to the execution device.

Abstract: An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.

Abstract: A method for selecting a hash function, a method for storing and searching a routing table and devices thereof are provided. The method for selecting a hash function includes: hashing data to be hashed by using a current alternative hash function; decoding a hash result; accumulating decoded results until no carry occurs during the accumulation; and selecting a current alternative hash function with no carry generated as a formal hash function. The method for storing a routing table includes: dividing the routing table into a next-level node pointer portion and a prefix portion for being stored; and selecting a hash function by using the above method for selecting a hash function. The method for searching a routing table includes: directly searching an IP address to be searched according to a directly stored length of a next-level node pointer portion for storing the routing table; and reading a prefix node according to a searched result.

Abstract: An address space expansion method implemented by the electronic device which includes a storage unit, wherein the storage unit includes a first storage unit and a second storage unit, comprising: responding to the user operation to generate a target address; determining whether a address range of the target address is less than or equal to a predetermined address range, and generating a corresponding control signal; enabling the first storage unit or the second storage unit according to the generated corresponding control signal; acquiring a physical address corresponding to the target address and providing the physical address to the enabled storage unit according to the corresponding control signal and a predetermined converting rule; accessing and performing a reading/writing operation for data corresponding to the physical address of the enabled storage unit.

Abstract: A mechanism is provided for invoking a multi-library application on a multiple processor system, wherein the multiple processor system comprises a Power Processing Element (PPE) and a plurality of Synergistic Processing Element (SPE). Applications including multi-libraries run in the memory of the PPE. The mechanism comprises maintaining the status of each SPE in the application running on the PPE, where there are SPE agents for capturing the instructions from the PPE in the SPEs that have been started. In response to a request for invoking a library, the PPE determines whether the number of available SPEs for invoking the library is adequate based on the current status of SPEs. If the number of available SPEs is adequate, the PPE sends a run instruction to selected SPEs. After finishing the invocation of all libraries, the PPE sends termination instructions to all started SPEs.

Abstract: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Abstract: Executing a service program for an accelerator application program in a hybrid computing environment that includes a host computer and an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module; where the service program includes a host portion and an accelerator portion and executing a service program for an accelerator includes receiving, from the host portion, operating information for the accelerator portion; starting the accelerator portion on the accelerator; providing, to the accelerator portion, operating information for the accelerator application program; establishing direct data communications between the host portion and the accelerator portion; and, responsive to an instruction communicated directly from the host portion, executing the accelerator application program.

Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Abstract: A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.

Abstract: A method of transforming low-level programming language code written for execution by a target processor includes receiving data comprising a plurality of low-level programming language instructions ordered for sequential execution by the target processor; detecting a pair of instructions in the plurality of low-level programming language instructions having a memory dependency therebetween; and inserting one or more instructions between the detected pair of instructions in the plurality of low-level programming language instructions having a memory dependency therebetween. The one or more instructions inserted between the detected pair of instructions create a true data dependency on a value stored in an architectural register of the target processor between the detected pair of instructions.

Abstract: A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method cancels the second portion issue.

Abstract: A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system. The available nodes and available acceleration devices in the computing system are identified. In addition, a plurality of virtual acceleration device definitions is created. Each virtual acceleration device definition includes attributes used to configure at least one of the plurality of identified acceleration devices. When an inquiry containing an identification of computing system resources to be used in processing the inquiry is received, at least one virtual acceleration device definition that is capable of configuring an acceleration device in accordance with the computing system resources identified by the inquiry is identified.

Abstract: The described embodiments provide a processor for generating a result vector with shifted values. During operation, the processor receives a first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a key element position in the second input vector. The processor then determines a number of bit positions to shift the base value using selected relevant elements in the first input vector. The processor then shifts the copy of the base value by the number of bit positions and writes the value into a corresponding element in the result vector. In addition, a predicate vector can be used to control the values that are written to the result vector.

Abstract: A branch target buffer (BTB) system and method for storing target address is provided, applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When storing the target address of the branch instruction, the BTB stores the variation range, carry bit and sub/add bit of the target address without having to store all the bits of the target address. Because the BTB of the present invention does not need to store the identical part of the branch instruction address and the target address, the present invention reduces the number of bits of the target address field for the BTB of the processor. Although the present invention uses less bits for target address field, the present invention is able to generate a complete target address without affecting the computation performance.

Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Abstract: The invention refers to a computer-implemented method and system for loading a loadware file on a CANopen device. The CANopen device comprises an electronic data sheet, which is extended to comprise a load object. After reading the load object with the load parameters, the respective loadware file is located, selected and accessed. Accessing the loadware file is done by applying the read load parameters.

Abstract: A method and apparatus for an instantly-on computer system is presented. A computer that incorporates fast non-volatile primary memory for storing the operating system, resulting in an instant-on or instant-booting of the computer. Large parts of the operating system code and application code are stored in non-volatile write-protectable areas that cannot be modified by malicious sources, resulting in a secure computer. It solves the problem from typical computers having to load the operating system and applications from a slow device such as the hard disk to the main memory. This loading is avoided by permanently housing the operating system in a non-volatile main memory. The system also solves the problem of corruption of operating system areas from malicious sources. The memory contains writeable and write-protected areas and a memory controller controls the access to the various regions of the memory.

Abstract: A technique for booting a stateless client includes booting a virtual machine (VM) monitor on the client. The VM monitor is stored in a non-volatile memory area of a memory subsystem (of the client) and a first portion of an operating system (which does not include any state information for the operating system) is stored in the non-volatile memory area of the client. Booting of the operating system for the client is initiated and a remote storage (that stores a second portion of the operating system that includes state information for the operating system) is accessed via a communication link. Booting of the operating system for the client is completed using the second portion of the operating system.

Abstract: Some embodiments of enhanced capabilities in provisioning on computing machines in a networked system have been presented. In one embodiment, a software vendor deploys a centralized server to an internal network of a customer. The provisioning capabilities of a centralized server are extended to support an additional type of platform by downloading a set of kickstart files associated with the additional type of platform from a software vendor. The centralized server may provision on a computing machine coupled to the centralized server within the internal network based on a type of a platform of the computing machine using one or more of the plurality of kickstart files.

Abstract: During a boot process of a data processing device having a master bootstrap processor device and multiple slave processor devices, memory associated with the master bootstrap processor is not accessible. Accordingly, the master bootstrap processor communicates configuration information to a slave processor by writing configuration information to a register associated with the slave processor. The slave processor communicates an acknowledgment to the master bootstrap processor in response to reading the configuration information.

Abstract: The present invention discloses a portable computing device (200) including a processor (202), non-volatile memory (206), and a volatile memory (208). An execute in place (XIP) kernel (210) stored in the non-volatile memory is executed immediately upon powering up the device. As the XIP kernel is executed, the processor maintain state and context information (212) in the volatile memory. The XIP kernel includes user interface and application segments, along the user to perform some functions immediately upon powering up the device. While executing the XIP kernel and full code instantiation (214) is loaded into the volatile memory. The full code instantiation includes identical code as is in the XIP kernel, in addition to other code. Once loaded, execution is switched (412) from the XIP kernel to the full code instantiation, providing full functionality of the device.

Abstract: A method and apparatus for instantly-available applications in a computer system is presented. A computer that incorporates fast non-volatile primary memory for storing the application software and/or operating system, resulting in an instant-on computer is presented. Large parts of the application code and/or operating system code are stored in non-volatile write-protectable areas of the memory that cannot be modified by malicious sources, resulting in a secure computer. It solves the problem of typical computers having to load the applications from a slow device such as the hard disk to the main memory. This loading is avoided by permanently housing the applications in a non-volatile main memory. The system also solves the problem of corruption of application software areas from malicious sources. The memory system contains writeable and write-protected areas and a memory controller that controls the access to the various regions of the memory.

Abstract: A method of encrypting a unique cryptographic entity (UCE), where a client device receives a global-key (GK-) encrypted UKD comprising a GK-encrypted UCE and a GK-encrypted unit key number (UKN). The client device verifies that the GK-encrypted UKN is the same as a pre-provisioned value and then decrypts the GK-encrypted UKD using a global key (GK). The client device then re-encrypts the decrypted UKD using a device user key (DUK) to determine a DUK-encrypted UCE and a DUK-encrypted UKN. The DUK-encrypted UKN is verified as not equal to the GK-encrypted UKN. The DUK-encrypted UKN is then appended to the DUK-encrypted UCE to form a DUK-encrypted UKD and stored in a memory.

Abstract: A profile adjustment module which enables customization of the profiles within a computer system. The profile adjustment module enables gaming or entertainment enthusiast or customers an easy-to-use interface to tune their personal computer for maximum performance for a customized application such as a gaming or entertainment application. The interface of the profile adjustment module includes designated settings depending on the system make-up. When a customer selects a usage model such as a “Game on” usage model or an “Entertainment on” usage model, the profile adjustment module initiates a predetermined sequence of events including, but not limited to tuning the audio and video settings to peek experience settings (where the settings are specifically chosen to adjust the usage model).

Abstract: The description relates to a system designed to protect data exchange involved with the use of cloud computing infrastructures by services and individuals. The system is designed so that a cloud resource and its middleware access points are protected in transferring data among themselves and end users using a system designed to spread the data and then reassemble the data.

Abstract: A storage device sends its storage-device-specific information A to a client apparatus. The client apparatus generates an encryption key P1, using client-apparatus key generation information B1 specific to the client apparatus and the received information A. The client apparatus generates information D? by encrypting its client-apparatus-specific information D, using the encryption key P1, and sends the information D? to the storage device. The storage device stores the information D?. When the storage device authenticates a client apparatus, the storage device has the client apparatus generate information D? through the process as described above and judges whether or not the information D? stored in the storage device matches the information D? generated by the client apparatus being examined.

Abstract: A secure communication path is set between virtual machines each arranged within one of a set of servers in a network. There is provided business software operated by executing one or more task programs each provided for a virtual machine, and each server is provided with, as a virtual machine, a guest operating system controlled by a host operating system. The one or more task programs are classified into task classes according to a type of a function to be realized, and there is provided task connection information indicating whether a communication path is needed or not between each pair of task classes. Then, a secure communication path between a pair of guest operating systems is set by setting virtual network connection information to a pair of host operating systems corresponding to the pair of guest operating systems, on the basis of the task connection information.

Abstract: A secure supervisory control and data acquisition (SCADA) system includes a SCADA control host system and any number of remote terminal unit (RTU) systems. Each RTU system includes an RTU transceiver, an RTU and a remote security device (RSD) coupling the RTU to the RTU transceiver. The SCADA control host system includes a SCADA control host configured to exchange SCADA information with each of the RTUs in a SCADA format, and a host security device (HSD) coupling the SCADA control host to a host transceiver. The host transceiver is configured to establish communications with each of the plurality of RTU transceivers. The HSD communicates with the RSDs to transparently encrypt the SCADA information using a cryptographic protocol that is independent of the SCADA protocol to thereby secure the communications between the HSD and each of the RSDs.

Abstract: The described embodiments relate generally to methods, systems and security devices for authorizing use of a software tool. Certain embodiments of the invention relate to a security device. The security device comprises at least one communication subsystem for enabling communication between the security device and a first external device, wherein the first external device has a software tool executable on the first external device. The security device further comprises a memory and processor coupled to the at least one communication subsystem and configured to control the at least one communication subsystem. The memory is accessible to the processor and stores a key for authorizing use of the software tool. The memory further stores program instructions which, when executed by the processor, cause the processor to execute a security application.

Abstract: This invention allows users to maximise their use of existing storage, processing power and network bandwidth resources. This is achieved through providing an enhanced level of data backup and restore that employs the initial encryption of data and storing one user's data on another user's hard drives through an anonymsing process. The efficiency of this process is enhanced when this invention is used in conjunction with self authentication which then provides the ability to log into a network anonymously from potentially anywhere.

Abstract: A device for manipulating a computer file or program includes a processor. The device includes a network interface which receives commands. The device includes a receiver which receives the commands from the network interface and provides the commands to the processor. The device includes storage having a computer file or program in a memory. Wherein the processor, based on the commands, makes changes to the computer file or program in the memory and suspends and reestablishes user intervention to the computer file or program. A device for manipulating a computer file or program.

Abstract: An exemplary display system includes a flat panel display and a host connectable to the flat panel display. The flat panel display includes a first storage unit including a first security code stored therein, a register, and a micro processing unit. The host includes a second storage unit including a second security code stored therein, and a central processing unit. The central processing unit is configured for converting the second security code to a digital signal and sending the digital signal to the register. The micro processing unit is configured to read and compare the first security code with the digital signal in the register, and output a control signal according to a result of said comparison.

Abstract: The invention facilitates remote management of a computer via a network. Remote computer management in which communication between a managed computer and a remote computer management server is initiated by the managed computer is implemented so that the presence of a proxy server at the site at which the managed computer is located can be detected, and communication from the managed computer to the remote computer management server is routed to a communication port assigned for communication with the proxy server, with instructions to then send the communication to the remote computer management server.