Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.

Abstract: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract: Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting an etching process for trench. Thus, the present invention prevents the effect of thinning tunnel oxide film while reducing a critical dimension of an active region. And, it is possible to assure a normal cell operation by the Fowler-Nordheim (FN) tunneling effect owing to preventing the thinning tunnel oxide film.

Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

Abstract: An approach where items of different temperatures are bonded to each other such that upon cooling down they contract in size resulting in zero residual stress between the bonded items at an ambient temperature. If materials of the bonded items have different thermal expansion coefficients and the items are put together at different bonding temperatures, then they may have insignificant residual stress upon cooling down to the ambient temperature (e.g., room temperature) because the different ranges of the temperature drops compensate for the different contractions.

Abstract: A method for manufacturing an SOI substrate, including the steps of implanting hydrogen ions from a main surface of a single-crystal silicon substrate having an interstitial oxygen concentration which is equal to or below 1×1018 cm?3; performing an activation treatment with respect to the main surface of at least one of a transparent insulative substrate and the silicon substrate; bonding the main surface of the transparent insulative substrate to the main surface of the silicon substrate at a room temperature; performing a heat treatment with respect to the bonded substrate at a temperature falling within the range of 350° C. to 550° C. and having a cooling rate after the heat treatment that is equal to or below 5° C./minute; and mechanically delaminating a silicon thin film from the silicon substrate to form a silicon film on the main surface of the transparent insulative substrate.

Abstract: An insulating film is formed as a pore-wall protective film (103) on pore walls in a porous layer (102) by the use of a mixed gas plasma of a noble gas and an insulating film forming gas generated by microwave excitation. As a result, the pore-wall protective film can have film properties as a protective film.

Abstract: The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and microelectronic component packages. In one particular example, a microelectronic component package includes a substrate and a microelectronic component that has a first surface with a surface area greater than that of a second surface. A cementitious material, e.g., a die attach paste, may attach the second surface of the microelectronic component to a mounting surface of the substrate, with the cementitious material extending outwardly beyond a perimeter of the second surface and covering a surface area of the mounting surface that is no greater than the surface area of the first surface. Such a microelectronic component package may be formed with a smaller footprint or, alternatively, may include a microelectronic component having larger dimensions in a microelectronic component package of the same size.

Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

Abstract: A semiconductor device manufacturing method can produce semiconductor light emitting/detecting devices that have high connective strength and high luminous energy by increasing contact areas of electrodes thereof and decreasing enclosed areas of electrodes thereof. A wafer is provided with a semiconductor substrate and a semiconductor epitaxial layer. A plurality of substrate concave portions and epitaxial layer concave portions are formed on the semiconductor substrate and the semiconductor epitaxial layer, respectively. Substrate electrodes and epitaxial layer electrodes are formed in the substrate concave portions and the epitaxial layer concave portions. A substrate surface electrode and an epitaxial layer surface electrode can be formed on the semiconductor substrate and the substrate electrodes and the semiconductor epitaxial layer and the epitaxial layer electrodes, respectively.

Abstract: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed of the stem and the cap. The method for producing this nitride semiconductor, laser light source has a cleaning step of cleaning the surface of the laser chip, the stem, or the cap. In the cleaning step, the laser chip, the stem, or the cap is exposed with ozone or an excited oxygen atom, or baked by heat. The method also has, after the cleaning step, a capping step of encapsulating the laser chip in the sealed container composed of the stem and the cap. During the capping step, the cleaned surface of the laser chip, the stem, or the cap is kept clean.

Abstract: Methods and apparatus provide for contacting respective first surfaces of a plurality of donor semiconductor wafers with a glass substrate; bonding the first surfaces of the plurality of donor semiconductor wafers to the glass substrate using electrolysis; separating the plurality of donor semiconductor wafers from the glass substrate leaving respective exfoliation layers bonded to the glass substrate; and depositing a further semiconductor layer on exposed surfaces of the exfoliation layers to augment a thickness of the exfoliation layers.

Abstract: A method of forming crystalline semiconducting layers on low melting or low softening point substrates includes the steps of providing an aqueous solution medium including a plurality of semiconductor nanoparticles dispersed therein having a median size less than 10 nm, and applying the solution medium to at least one region of a substrate to be coated. The substrate has a melting or softening point of <200° C. The solution medium is evaporated and the at least one region is laser irradiated for fusing the nanoparticles followed by annealing to obtain a continuous film having a recrystallized microstructure. An article includes a polycrystalline semiconducting layer including a plurality of crystallites predominately in the size range of 2 to 50 ?m, and a substrate having a melting or softening point of <200° C. supporting the semiconducting layer.

Abstract: A manufacturing method of a nitride substrate includes the steps of preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH3 are supplied into the reactor so that partial pressure PHCl satisfies (1.5+0.0005 p) kPa?PHCl?(4+0.0005 p) kPa and partial pressure PNH3 satisfies (15?0.0009 p) kPa?PNH3?(26?0.0017 p) kPa, whereby an AlxGayIn1-x-yN crystal (0?x<1, 0<y?1) is grown, and whereby a ridge-valley structure including a plurality of ridges and valleys parallel to one another is formed. The AlxGayIn1-x-yN crystal is grown so that the ridge-valley structure is not buried while a height of the valleys from the ground substrate is allowed to exceed 2.5 (p?s).

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.

Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

Abstract: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Abstract: A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and the first etch stopper layer, a metal line in the trench, the metal line including a second contact plug projecting from the trench, wherein the metal line and the trench are formed as a single body, and a second insulating interlayer over the substrate including the metal line and the second contact plug.

Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.

Abstract: A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of a photo mask. The remaining trench oxide film is etched using the hard mask nitride film as a mask, thus forming a trench. The etch-stop nitride film and the hard mask nitride film are etched on condition that an oxide film has a high selectivity with respect to a nitride film. Accordingly, the loss of a top surface of the trench oxide film can be minimized and a bit line can be formed to have a uniform height. In accordance with the invention, bit line resistance and capacitance variation can be reduced and the reliability of a device can be improved.

Abstract: In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating a liquid tantalum precursor containing tertiaryamylimido-tris(dimethylamido) tantalum (TAIMATA) to a temperature of at least 30° C. to form a tantalum precursor gas and exposing the substrate to a continuous flow of a carrier gas during an atomic layer deposition process. The method further provides exposing the substrate to the tantalum precursor gas by pulsing the tantalum precursor gas into the carrier gas and adsorbing the tantalum precursor gas on the substrate to form a tantalum precursor layer thereon. Subsequently, the tantalum precursor layer is exposed to at least one secondary element-containing gas by pulsing the secondary element-containing gas into the carrier gas while forming a tantalum barrier layer on the substrate.

Abstract: A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.

Abstract: A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask coverers portions of the first plurality of metal lands closest to the encapsulation area. Remaining portions of the first plurality of metal lands are exposed areas having no solder mask.

Abstract: A silicon nitride layer is formed on at least a back side of a silicon wafer substrate of a semiconductor device. An oxide layer is formed on at least the silicon nitride layer on the back side of the substrate. The oxide layer protects the silicon nitride layer during processing of the device. The oxide layer is removed prior to packaging the device. After components have been formed on a front side of the substrate opposite the back side, packaging is attached to the silicon nitride layer. The components provide a functionality of the device. The silicon nitride layer completely remains on the back side of the substrate after fabrication of the device has been completed. The silicon nitride layer is adapted to minimize and does minimize bowing of the device.

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract: A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the polymer; forming a metal layer to fill the groove which is formed with the insulation layer on the sidewall thereof; and back-grinding a backside of the wafer to expose the metal layer filled in the groove.

Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.

Abstract: A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity are insured by use of conductive rapid thermal annealing in hot wall reactors, with massive heated plates closely spaced from the substrate surfaces. Interruption is particularly facilitated by forced cooling, preferably also by conductive thermal exchange with closely spaced, massive plates.

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the film deposited during the first etching has been removed to an extent that further exposure to the etchant may remove the liner and expose underlying structures. Accordingly, the etching is stopped upon detection of distinctive reaction products and the next deposition in the deposition/etching/deposition process is begun.

Abstract: A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal silicide layer. The method comprises steps of removing a portion of the dielectric layer by using the patterned photoresist layer as a mask so as to form an opening, wherein the opening exposes a portion of the etching stop layer above the metal silicide layer. the patterned photoresist layer is removed by using an oxygen-free plasma.

Abstract: A method is provided for performing plasma immersion ion implantation with a highly uniform seasoning film on the interior of a reactor chamber having a ceiling and a cylindrical side wall and a wafer support pedestal facing the ceiling. The method includes providing a gas distribution ring with plural gas injection orifices on a periphery of a wafer support pedestal, the orifices facing radially outwardly from the wafer support pedestal. Silicon-containing gas is introduced through the gas distribution orifices of the ring to establish a radially outward flow pattern of the silicon-containing gas. The reactor includes pairs of conduit ports in the ceiling adjacent the side wall at opposing sides thereof and respective external conduits generally spanning the diameter of the chamber and coupled to respective pairs of the ports. The method further includes injecting oxygen gas through the conduit ports into the chamber to establish an axially downward flow pattern of oxygen gas in the chamber.

Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.

Abstract: Methods are provided for pulsed chemical vapor deposition (CVD) of complex nitrides, such as ternary metal nitrides. Pulses of metal halide precursors are separated from one another and nitrogen-containing precursor is provided during the metal halide precursor pulses as well as between the metal halide precursor pulses. Two different metal halide precursors can be provided in simultaneous pulses, alternatingly, or in a variety of sequences. The nitrogen-containing precursor, such as ammonia, can be provided in pulses simultaneously with the metal halide precursors and between the metal halide precursors, or continuously throughout the deposition. Temperatures can be kept between about 300° C. and about 700° C.

Abstract: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a wet oxidation process, whereby a tantalum oxide film is formed as the insulating film.

Abstract: A barrel assembly for a pneumatic paintball gun includes a barrel body and a barrel insert. The barrel body has a breech end, a muzzle end, and a barrel bore extending longitudinally through the barrel body from the breech end to the muzzle end. The barrel insert has a breech end, a distal end, and an insert bore, and is configured to be removably housed within a breech portion of the bore of the barrel body. The breech end of the barrel body is configured to attach to a breech end of the paintball gun. The barrel insert collaborates with the barrel body to provide a firing bore for the barrel assembly which guides a paintball fired from the breech end of the gun through the barrel and out the muzzle end of the barrel body. The barrel insert can be constructed having a thin, flexible wall so as to permit lateral deformation of the barrel insert.

Abstract: A wipe is provided that includes a first wiping member bonded to a backing member along valleys, whereby the wiping member includes a plurality of discrete peaks, and an adhesive is provided, in one embodiment, in the valleys and not on the peaks.

Abstract: Provided is thermosetting urea-formaldehyde (UF) resin binder formulation modified with a thickener. The formulation preferably has a viscosity in the range of from 3 to 10 cP and a surface tension of from 35 to 50 mN/m, and is preferably prepared from a binder composition exhibiting a viscosity of from 175 to 250 cP.

Abstract: The invention relates to a glass composition and a glass frit adequate for low temperature sintering agent at 1,100° C. or less, and a dielectric composition and a multilayer ceramic capacitor using the same. The glass composition comprises aLi2O-bK2O-cCaO-dBaO-eB2O3-fSiO2, in which a, b, c, d, e and f satisfy following relationships: a+b+c+d+e+f=100, 2?a?10, 2?b?10, 0?c?25, 0?d?25, 5?e?20, and 50?f?80.

Abstract: A glass composition for forming a blue colored glass is disclosed. The glass composition is made up of a base glass portion, iron oxide, and at least one first additive compound selected from Nd2O3 in an amount up to 1 weight percent and/or CuO in an amount up to 0.5 weight percent. The base glass portion has the following components: SiO2 from 66 to 75 weight percent; Na2O from 10 to 20 weight percent; CaO from 5 to 15 weight percent; MgO from 0 to 5 weight percent; Al2O3 from 0 to 5 weight percent; B2O3 from 0 to 5 weight percent; and K2O from 0 to 5 weight percent. The total iron in the glass composition ranges from 0.3 to 1.2 weight percent, and the glass composition has a redox ratio ranging from 0.15 to 0.65.

Abstract: Provided is a translucent ceramic which has a high Abbe number, is advantageous in aberration correction, and can be easily produced. The translucent ceramic contains, as a main component, a garnet type compound represented by the General Formula: Y3AlvOw, wherein the condition of 4.4?v?5.4 is satisfied and w is a positive number for maintaining electrical neutrality, in which the Al is partially or entirely substituted by Ga and the Y is optionally partly substituted by Gd. The translucent ceramic is suitably used, for example, for lenses arranged with a diaphragm interposed therebetween in a Gauss lens optical system, such as an optical system for single-lens reflex cameras.

Abstract: After synthesizing particles by liquid phase synthesis, the solution is substituted without drying these particles, and here, a solution comprising a grain boundary phase composition consisting of at least one or more types selected from a group consisting of Al2O3, yttrium oxide, silicon oxide, yttrium-silicon complex oxide, aluminum-silicon complex oxide, and a compound having a garnet structure with a lower melting point than the aforementioned particles, or a solution comprising a precipitate is introduced. Microparticles are adjusted by allowing adhesion and growth of the solution comprising a composition of grain boundary phase or the solution comprising a precipitate on the surface of the particles; these microparticles are allowed to align in 3-dimensions in solution and are formed into a molded body, and this molded body is sintered.

Abstract: The invention is concerned with a material which shows low absorption for UV radiation having a wavelength below 250 nm, low birefringence, high chemical resistance and high radiation resistance and which is therefore particularly usable for making optical components for microlithography. According to the invention the material consists of synthetically produced quartz crystallites which form a polycrystalline structure and have a mean grain size in the range between 500 nm and 30 ?m. The method according to the invention for making a blank from the material comprises providing granules consisting of synthetically produced quartz crystals having a mean grain size in the range between 500 nm and 30 ?m, and sintering the granules to obtain a blank of polycrystalline quartz.

Abstract: Provided are a catalyst which inhibits light paraffins form being produced in catalytic cracking of heavy hydrocarbons and which effectively produces olefins and a process in which the above catalyst is used to produce olefins from heavy hydrocarbons at a high yield. The catalyst is a catalytic cracking catalyst for catalytically cracking a hydrocarbon raw material, comprising (A) pentasil type zeolite modified with a rare earth element and zirconium and (B) faujasite type zeolite, and the process is a production process for olefin and a fuel oil, comprising bringing a heavy oil containing 50 mass % or more of a hydrocarbon fraction having a boiling point of 180° C. or higher into contact with the catalyst described above to crack it.