Abstract: A system for sanitizing an enclosed structure comprises a first sensor, a second sensor, a third sensor, a germicidal ultraviolet light source, a motor, and a controller. The first sensor detects the presence of humans or animals within the enclosed structure. The second sensor detects the position of at least one door of the enclosed structure. The third sensor detects tampering with the system. The ultraviolet light source provides electromagnetic radiation in the ultraviolet range. The motor moves the ultraviolet light source from an inactive position to an active position and from the active position to the inactive position. The controller receives inputs from the first sensor, the second sensor, and the third sensor, and transmits outputs to the ultraviolet light source and the motor.

Abstract: A pharmaceutical pig is used to transport a syringe containing a liquid radiopharmaceutical from a radiopharmacy to a medical facility for administration to a patient. The pharmaceutical pig includes an elongate polymer cap that is removably attached to an elongate polymer base. The elongate polymer cap includes a cap shell that completely encloses a cap shielding element and the elongate polymer base includes a base shell that completely encloses a base shielding element. Preferably the polymer utilized for the cap shell and the base shell is polycarbonate resin, e.g., LEXAN®. An inner liner is not utilized and the cap shielding element and the base shielding element, which are preferably, but not necessarily, made of lead, are completely sealed and unexposed.

Abstract: A method and apparatus wherein a substrate is provided with a preformatted structure, with structural elements arranged in a matrix, wherein the matrix extends in an X-direction and Y-direction, wherein a processing head is provided, wherein a camera is provided which is connected with the processing head and which comprises at least one series of sensors arranged along a main line, wherein the camera scans the substrate and thereby provides at least one one-dimensional camera signal, wherein, for real-time determining at least the X-position and the Y-position of the structure with respect to the camera, the said main line includes an angle with the X-direction and with the Y-direction, wherein the angle is chosen such that the camera signal contains spatially separated X-position information and Y-position information and that the X-position information and the Y-position information can be separated from the sensor signal with the aid of signal processing.

Abstract: A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate to form the nanowire extending between a pair of islands in the semiconductor layer. The method further includes depositing an electrically conductive material on the pair of islands to form the electrical contacts. A nano-pn diode includes the nanowire as a first nano-electrode, a pn-junction vertically stacked on the nanowire, and a second nano-electrode on a (110) horizontal planar end of the pn-junction. The nano-pn diode may be fabricated in an array of the diodes on the semiconductor-on-insulator substrate.

Abstract: Quantum dots are positioned within a layered composite film to produce a plurality of real-time programmable dopants within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge carriers form artificial atoms, which serve as dopants for the surrounding materials. The atomic number of each artificial atom is adjusted through precise variations in the voltage across the quantum dot that confines it. The change in atomic number alters the doping characteristics of the artificial atoms. The layered composite film is also configured as a shift register.

Abstract: A number of light-emitting layer structures for the GaN-based LEDs that can increase the lighting efficiency of the GaN-based LEDs on one hand and facilitate the growth of epitaxial layer with better quality on the other hand are provided. The light-emitting layer structure provided is located between the n-type GaN contact layer and the p-type GaN contact layer. Sequentially stacked on top of the n-type GaN contact layer is the light-emitting layer containing a lower barrier layer, at least one intermediate layer, and an upper barrier layer. That is, the light-emitting layer contains at least one intermediate layer interposed between the upper and lower barrier layers. When there are multiple intermediate layers inside the light-emitting layer, there is an intermediate barrier layer interposed between every two immediately adjacent intermediate layers.

Abstract: Group III nitride based light emitting devices and methods of fabricating Group III nitride based light emitting devices are provided. The emitting devices include an n-type Group III nitride layer, a Group III nitride based active region on the n-type Group III nitride layer and comprising at least one quantum well structure, a Group III nitride layer including indium on the active region, a p-type Group III nitride layer including aluminum on the Group III nitride layer including indium, a first contact on the n-type Group III nitride layer and a second contact on the p-type Group III nitride layer. The Group III nitride layer including indium may also include aluminum.

Abstract: The subject invention comprises the realization of P-on-N type II InAs/GaSb superlattice photodiodes. A high-quality InAsSb layer lattice-mismatched to GaSb is used as a buffer to prepare the surface of the substrate prior to superlattice growth. The InAsSb layer also serves as an effective n-contact layer. The contact layer has been optimized to improve device performance, most notably performance that is similar to traditional N-on-P structures.

Abstract: A substrate having organic thin film capable of growing two dimensionally such organic thin film as C60 and a transistor using the same are constituted with a substrate (1) having organic thin film by sequentially depositing a buffer layer (3) and organic thin film (4) on the substrate (2), and with the buffer layer orienting the organic thin film (4). A layer easily oriented with the substrate (2) and the buffer layer (3) may be inserted between the substrate (2) and the buffer layer (3). A sapphire substrate as the substrate (2), pentacene or pentacene fluoride as the buffer layer (3), and C60 or rubrene as the organic thin film (4) may be used, thereby C60 or rubrene two dimensional thin film of high quality can be obtained. By using such a substrate (1) having organic thin film, a field effect transistor of high quality can be realized.

Abstract: An organic thin film transistor that can reduce contact resistance between source and drain electrodes and an organic semiconductor layer and can be readily manufactured, a flat panel display apparatus utilizing the organic thin film transistor, and a method of manufacturing the organic thin film transistor. The organic thin film transistor includes: a substrate; a source electrode and a drain electrode disposed on the gate insulating film; a conductive polymer layer disposed to cover at least a portion of each of source and drain electrodes; a hydrophobic material layer disposed on the substrate and the source and drain electrodes except regions where the conductive polymer layer are formed; an organic semiconductor layer electrically connected to the source and drain electrodes; a gate insulating film disposed to cover the organic semiconductor layer; and a gate electrode disposed on the gate insulating film.

Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes, an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.

Abstract: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro alkyl group each having a carbon number of 1 to 20), and a field-effect transistor production method comprising forming an organic semiconductor layer using the fullerene derivative by a solution process, and subjecting the organic semiconductor layer to a heat treatment in an atmosphere containing nitrogen or argon or in vacuum to provide enhanced characteristics to the organic semiconductor layer. The present invention makes it possible to form an organic semiconductor layer by a solution process and provide an organic field-effect transistor excellent in electron mobility and on-off ratio and capable of operating even in an ambient air atmosphere.

Abstract: A display device includes an insulation substrate, a source electrode and a drain electrode disposed on the insulation substrate and distanced from each other and including a channel area interposed therebetween, a wall exposing portions of the source electrode and the drain electrode, and defining an opening area surrounding the channel area, and an organic semiconductor layer covering the channel area, and comprising a first sub layer and a second sub layer having different grain sizes.

Abstract: A colorant molecule is provided that includes at least one switch unit. The switch unit comprises ring-based tautomers, of which there may be more than one per chromophore, and may include donor and/or acceptor moieties.

Abstract: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel with each other and in perpendicular to the edge of the fuse opening.

Abstract: A top-emitting organic light emitting device having an improved pixel electrode layout for decreasing photo-leakage of a thin film transistor and enhancing an aperture ratio is provided. In the top-emitting organic light emitting device, the pixel electrode is designed to have the maximum size allowed by a layout design rule. Further, the pixel electrode is formed to overlap all the thin film transistors below.

Abstract: A display device includes a first insulating substrate having thin film transistors; a second insulating substrate of plastic having a black matrix comprising a plurality of horizontal extending portions extending in one directions and a plurality of vertical portions extending at an irregular interval in a second direction perpendicular to the first direction; and a liquid crystal layer located between the first substrate and the second substrate.

Abstract: An array substrate for a liquid crystal display device includes a gate and a data lines on a substrate intersecting each other, the data line includes a first layer formed of a transparent conductive material and a second layer under the first layer; a thin film transistor including a gate electrode connected to the gate line formed at respective intersection of the gate and data lines, an insulating layer on the gate electrode, an active layer on the insulating layer disposed within the gate electrode, an etch stopper on the active layer, an ohmic contact layer on the etch stopper, a source electrode on the ohmic contact layer and connected to the first layer, a drain electrode spaced apart from the source electrode; a pixel electrode connected to the drain electrode, wherein the source, drain and pixel electrodes are formed of the same layer and material as the first layer.

Abstract: A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.

Abstract: An active-matrix device includes a substrate; a plurality of pixel electrodes provided on a first surface of the substrate; a plurality of switching elements provided to correspond to each of the pixel electrodes, each of the switching elements including a fixed electrode connected to the each pixel electrode, a movable electrode mainly made of silicon and displaceably provided so as to contact with and separate from the fixed electrode, and a driving electrode provided to oppose the movable electrode via an electrostatic gap; a first wiring connected to the movable electrode; and a second wiring connected to the driving electrode, wherein a voltage is applied between the movable electrode and the driving electrode to generate an electrostatic attraction between the movable electrode and the driving electrode so as to displace the movable electrode such that the movable electrode contacts with the fixed electrode to electrically connect the first wiring to the pixel electrode.

Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.

Abstract: An organic light emitting display includes a substrate having a pixel driving circuit region and an opening region. A thin film transistor having source/drain electrodes is positioned on the pixel driving circuit region of the substrate. A passivation insulating layer is positioned on the source/drain electrodes to have a via hole for exposing one of the source/drain electrodes. A pixel electrode is positioned on a bottom surface of the via hole and in contact with the exposed source/drain electrode, and extends onto the passivation insulating layer. A first photosensitive organic insulating layer is positioned within the via hole in which the pixel electrode is formed to fill the via hole and to expose a portion of the pixel electrode around the via hole. An organic emission layer is positioned on the exposed pixel electrode.

Abstract: A device 100 comprising a substrate 115 having crystal-support-structures 110 thereon, and a III-V crystal 210. The III-V crystal is on a single contact region 140 of one of the crystal-support-structures. An area of the contact region is no more than about 50 percent of a surface area 320 of the III-V crystal.

Abstract: An object of the invention is to provide a lighting device which can suppress luminance nonuniformity in a light emitting region when the lighting device has large area. A layer including a light emitting material is formed between a first electrode and a second electrode, and a third electrode is formed to connect to the first electrode through an opening formed in the second electrode and the layer including a light emitting material. An effect of voltage drop due to relatively high resistivity of the first electrode can be reduced by electrically connecting the third electrode to the first electrode through the opening.

Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.

Abstract: The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while being joined to one or more edges of the upper surface. The side patterns consist of protrusions or depressions so as to scatter or diffract light to an upper portion or a lower portion of the light-emitting device.

Abstract: A semiconductor structure with active zones, such as light diodes or photodiodes, including a substrate (SUB) with at least two active zones (AZ1-AZn), each of which emits or absorbs a radiation of differing wavelength. According to the invention, a multi-wavelength diode may be achieved, in which a first (lower) active zone (AZ1) is grown on a surface of the substrate (SUB), with one or several further active zones (AZ1-Azn) epitaxially grown one on the other and the active zones (AZ1-AZn) are serially connected from the lower active zone (AZ1) to an upper active zone (AZn), by means of tunnel diodes (TD1-TDn), serving as low-impedance resistors.

Abstract: A plurality of semiconductor layers including an active layer 6 and a light extract layer 4, and a reflective metal film 11 are formed in a semiconductor light emitting device. The light extract layer 4 is formed of a plurality of layers 23, 24 having different composition ratios. An irregularity 22 is formed on the layers 23, 24 including an outermost layer to provide a main surface S as a rough-surface.

Abstract: A radiation-emitting semiconductor component with a semiconductor body, including a first principal surface (5), a second principal surface (9) and a semiconductor layer sequence (4) with an electromagnetic radiation generating active zone (7), in which the semiconductor layer sequence (4) is disposed between the first and the second principal surfaces (5, 9), a first current spreading layer (3) is disposed on the first principal surface (5) and electrically conductively connected to the semiconductor layer sequence (4), and a second current spreading layer (10) is disposed on the second principal surface (9) and electrically conductively connected to the semiconductor layer sequence (4).

Abstract: A semiconductor light-emitting device, the device includes a substrate, a semiconductor stacked layer, a lead electrode and a lead, wherein the semiconductor stacked layer at least includes a N-type layer and a P-type layer, at least one of the N-type layer and the P-type layer has an opening, the opening is just beneath the lead; or includes a conductive substrate having a main surface and a back surface, an adhesive metal layer, a reflective/ohmic metal layer, a semiconductor stacked layer, a lead electrode and a lead sequentially deposited on the main surface of the substrate, the reflective/ohmic metal layer has an opening, the opening is just beneath the lead.

Abstract: Light emitting die package is disclosed. The die package includes a leadframe, a bottom heatsink, a top heatsink, a reflector and a lens. The top and bottom heatsinks are thermally coupled but electrically insulated from the leadframe. The leadframe includes a plurality of leads and defines a mounting pad for mounting LEDS. The top heatsink defines an opening over the mounting pad. The reflector is coupled to the top heatsink at the opening. The lens is placed over the opening defining an enclosed cavity over the mounting pad. At least one light emitting device (LED) is mounted on the mounting pad within the cavity. Encapsulant optically couples the LED to its surrounding surfaces to maximize its optical performance. When energized, the LED generates light and heat. The light is reflected by the reflector and operated on by the lens. The heat is dissipated by the top and the bottom heatsinks.

Abstract: Light-emitting devices, and related components, processes, systems and methods are disclosed.

Abstract: The disclosed subject matter includes a semiconductor optical device with a stable optical characteristic, an excellent radiant efficiency, and a high mounting reliability. A casing can be configured with a concaved-shaped cavity that includes an opening and a bottom portion. Each of one end portions of first/second lead frame electrodes 3a, 3b can be exposed on the bottom portion. The first one end portion can include an optical chip mounted thereon, and the second one end portion can be connected to another electrode of the optical chip via a bonding wire. The first lead frame electrode extends from an outside surface substantially perpendicular to the bottom portion and is bent in a direction towards the opening. The second lead frame electrode extends from an outside surface of the casing that is opposite to the outside surface from which the first electrode extends. Various physical configurations of the electrodes are disclosed.

Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a Group III nitride active layer positioned between a first n-type Group III nitride cladding layer and a second n-type Group III nitride cladding layer, the respective bandgaps of the first and second n-type cladding layers being greater than the bandgap of the active layer. The semiconductor structure further includes a p-type Group III nitride layer, which is positioned in the semiconductor structure such that the second n-type cladding layer is between the p-type layer and the active layer.

Abstract: The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the plurality of voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands.

Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.

Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.

Abstract: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ?1 and a thickness L1 of the first layer, a resistivity ?2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (?1/?2)×(L1·L2/W22)<1.6.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Abstract: A field effect transistor and a method for making the same. In one embodiment, the field effect transistor comprises a source; a drain; a gate; at least one carbon nanotube on the gate; and a dielectric layer that coats the gate and a portion of the at least one carbon nanotube, wherein the at least one carbon nanotube has an exposed portion that is not coated with the dielectric layer, and wherein the exposed portion is functionalized with at least one indicator molecule. In other embodiments, the field effect transistor is a biochem-FET.

Abstract: The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel.

Abstract: The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.

Abstract: A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.