Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

Abstract: A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region.

Abstract: A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor.

Abstract: A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device.

Abstract: A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film.

Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a secon

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.

Abstract: A memory cell (300, 500), the memory cell (300, 500) comprising a substrate (301), a nanowire (302) extending along a vertical trench formed in the substrate (301), a control gate (303) surrounding the nanowire (302), and a charge storage structure (320, 501) formed between the control gate (303) and the nanowire (302).

Abstract: Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word line of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell. In another memory device, opposite polarity voltages are applied to the bit line and the word line.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

Abstract: A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices.

Abstract: In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.

Abstract: A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates surrounded by body regions of a second conductivity type encompassing source regions of the first conductivity type therein. The semiconductor power device further includes trench contact structure having a plurality of trench contacts with trenches extended into the body regions for as source-body contacts and extended into the trench gates as gate contact. The semiconductor power device further includes a termination area wherein a plurality of the trench gate contacts are electrically connected to the source-body contacts.

Abstract: There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.

Abstract: Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode.

Abstract: A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided.

Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.

Abstract: A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that provides a first dopant type. A patterned masking layer is formed on the first surface region, wherein at least one aperture in the masking layer is defined. The first surface region is etched to form at least one trench region corresponding to a position of the aperture. A dopant of a first dopant type is implanted to raise a concentration of the first dopant type in a first dopant type drift region located below the trench region. After the implanting, the trench region is filled with a dielectric fill material. A body region is then formed having a second dopant type in a portion of the first surface region. A gate dielectric is then formed over a surface of the body region and the first surface region.

Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

Abstract: A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes.

Abstract: A semiconductor device includes a gate, a source region and a drain region that are co-doped to produce a strain in the channel region of a transistor. The co-doping can include having a source and drain region having silicon that includes boron and phosphorous or arsenic and gallium. The source and drain regions can include co-dopant levels of more than 1020 atom/cm3. The source region and drain region each can be co-doped with more boron than phosphorous or can be co-doped with more phosphorous than boron. Alternatively, the source region and drain region each can be co-doped with more arsenic than gallium or can be co-doped with more gallium than arsenic. A method of manufacturing a semiconductor device includes forming a gate on top of a substrate and over a nitrogenated oxide layer, etching a portion of the substrate and nitrogenated oxide layer to form a recessed source region and a recessed drain region, filling the recessed source region and the recessed drain region with a co-doped silicon compound.

Abstract: The present invention provides a semiconductor device including thin film transistors that have different characteristics on the same substrate and that have high performance and high reliability and a production method thereof.

Abstract: A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween.

Abstract: A semiconductor device includes: an element isolation layer provided in a semiconductor layer; an element region divided by the element isolation layer; a gate interconnect which extends over the element region and the element isolation layer; a sidewall formed at a sidewall of the gate interconnect; and a contact connected to the gate interconnect located over the element isolation layer. The sidewall of the gate interconnect has a region, which is in contact with the contact, in at least an upper portion.

Abstract: To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced. The technical idea of the present invention lies in the configuration in which in a first to a third silicon nitride film to be formed by lamination, the respective film thicknesses thereof are not constant but become smaller in order from the third silicon nitride film in the upper layer to the first silicon nitride film in the lower layer while the total film thickness thereof is kept constant. Due to this it is possible to improve the embedding characteristic of the third silicon nitride film in the uppermost layer in particular, while ensuring the tensile stress of the first to third silicon nitride films, which makes effective the strained silicon technique.

Abstract: A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.

Abstract: Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer.

Abstract: A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region.

Abstract: The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning.

Abstract: A method for producing a component, especially a micromechanical, micro-electro-mechanical or micro-opto-electro-mechanical component, as well as such a component which has an active structure that is embedded in a layer structure. Strip conductor bridges are formed by etching first and second depressions having a first and second, different etching depth into a covering layer of a first layer combination that additionally encompasses a substrate and an insulation layer. The deeper depression is used for insulating the strip conductor bridge while the shallower depression provides a moving space for the active structure with the moving space being bridged by the strip conductor bridge.

Abstract: A semiconductor dynamic quantity sensor includes a sensor part and a cap connected to the sensor part. Dynamic quantity is detected based on a capacitance of a capacitor defined between a movable electrode and a fixed electrode of the sensor part. A float portion of the sensor part is separated from a support board of the sensor part to define a predetermined interval. At least one of the cap and the support board has a displacing portion displacing the float portion in a direction perpendicular to the support board so as to change the predetermined interval. The movable electrode has a displacement in accordance with the displaced float portion.

Abstract: An integrated circuit structure includes a capacitor, which further includes a first capacitor plate formed of polysilicon, and a second capacitor plate substantially encircling the first capacitor plate. The first capacitor plate has a portion configured to vibrate in response to an acoustic wave. The second capacitor plate is fixed and has slanted edges facing the first capacitor plate.

Abstract: Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization.

Abstract: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

Abstract: Sensor package 1 and a corresponding manufacturing method, wherein the sensor package 1 includes several components like a magneto resistive sensor 40 and electronic components 30, and the orientation of the elements and components is maintained by a moulding body 200 manufactured in a single moulding step.

Abstract: A thin film, hydrogenated, silicon based semiconductor alloy material is produced by a VHF energized plasma deposition process wherein a process gas is decomposed in a plasma so as to deposit the thin film material onto a substrate. The process is carried out at process gas pressures which are in the range of 0.5-2.0 torr, with substrate temperatures that do not exceed 300° C., and substrate-cathode spacings in the range of 10-50 millimeters. Deposition rates are at least 5 angstroms per second. Also disclosed are photovoltaic devices which include the semiconductor material.

Abstract: An image sensor and a method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming an interconnection and/or an interlayer dielectric over a semiconductor substrate including circuitry connected to an interconnection. A method of manufacturing an image sensor may include forming a photodiode having a first doping layer and/or a second doping layer over an interlayer dielectric, and forming a via hole through a photodiode, which may expose a portion of a surface of an interconnection. A method of manufacturing an image sensor may include forming a barrier pattern over a via hole which may cover an exposed surface of a second doping layer, and a contact plug on and/or over a via hole, which may connect an interconnection and a first doping layer. An upper portion of a contact plug may be etched. An insulating layer may be formed over a contact plug.

Abstract: A method of manufacturing an image sensor and devices thereof. A method of manufacturing an image sensor may include forming an interlayer dielectric layer, which may include a metal line, on and/or over a semiconductor substrate. A method of manufacturing an image sensor may include forming an image sensing part, including a stacked structure having a first doped layer and/or a second doped layer, on and/or over a interlayer dielectric layer. A method of manufacturing an image sensor may include forming a via hole, which may expose a metal line by perforating a image sensing part and/or a interlayer dielectric layer. A method of manufacturing an image sensor may include performing a cleaning process. An undercut may be formed on and/or over a image sensing part when a via hole is formed, and/or a native oxide layer may be substantially removed from a undercut through a cleaning process.

Abstract: A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and a light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The light permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance.

Abstract: A manufacturing method of a camera module includes steps of: forming a wafer assembly of a semiconductor wafer and a light transmissible optical wafer which are fixed to each other, wherein the semiconductor wafer has an array of plural sensor units each having a light receiving unit of a photoelectric conversion element, and wherein the light transmissible optical wafer has an array of plural lens units, the lens units being opposite to the respective sensor units while each pair of the lens unit and the sensor unit faces each other across a space, so that the semiconductor wafer and the light transmissible optical wafer are adhered at circumferences of the respective pair of the lens unit and the sensor unit with a spacer unit, cutting the wafer assembly at the spacer unit to individually divide the wafer assembly into a plurality of camera modules each comprising a sensor chip and a lens chip bonded to each other by a spacer, forming a light shieldable mask film to determine a lens aperture of each of the

Abstract: An image sensor and a method of manufacturing the same are disclosed. A passivation layer on an interlayer dielectric layer has different thicknesses for neighboring pixels. Consequently, a phase of light incident on a pixel is out of phase with light incident on an adjacent pixel before it reaches a photodiode. As a result, diffraction of the incident light results in destructive interference between the pixels. Thus, cross talk between adjacent pixels can be prevented.

Abstract: An image sensor is disclosed that includes a first substrate including an electric junction region, a transistor, and a metal line connected to the electric junction region or the transistor; and a photodiode formed on the first substrate. The first substrate is formed at an upper portion thereof with a reflective layer to reflect light back to the photodiode.

Abstract: Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a substrate, a bonding silicon, an interlayer dielectric, a first contact plug, a second contact plug, a second metal interconnection, and a color filter layer and a microlens. The substrate comprises a first metal interconnection. The bonding silicon is formed on the substrate, and comprises a plurality of impurity regions. The interlayer dielectric is formed on the bonding silicon. The first contact plug penetrates the bonding silicon and is electrically connected to the first metal interconnection. The second contact plug penetrates the interlayer dielectric and is connected to a surface of the bonding silicon. The second metal interconnection is formed on the interlayer dielectric, and is connected to the second contact plug. The color filter layer and a microlens are formed over the second metal interconnection.