Abstract: An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that data state, such matching data states are identified and writing to those bits is precluded during the write command. In one embodiment, both the incoming data to be written to a bit and the data currently present at that bit address are latched. These latched data are then compared (e.g., with an XOR gate) to determine which bits have a matching data state. The results of this comparison are used as an enable signal to the write (column) driver in the PCRAM memory array, with the effect that only data bits having different data state are written, while data bits having a matching data state are not needlessly re-written.

Abstract: A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the basis of an address signal having a voltage of the second power supply. The decoder includes a level shifter which changes a voltage of the word line to a voltage of the first power supply, and a switching circuit which receives the first power supply and applies a voltage lower than the first power supply to the level shifter in selecting the word line.

Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.

Abstract: Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.

Abstract: A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line.

Abstract: Provided is a memory device that can detect a mismatch in a bit line sense amp, wherein the memory device includes a sense amp drive unit for selectively supplying a pull-up drive voltage or a pull-down drive voltage to a bit line sense amp in response to a sensing test signal provided from outside.

Abstract: The apparatus comprises derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different from other derived addresses in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses and is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value.

Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second precharge element for precharging a fourth bit line in response to a third precharge signal.

Abstract: A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.

Abstract: A semiconductor memory device includes a voltage control circuit providing different voltages as a precharge voltage in accordance with an active state and a standby stage. The semiconductor memory device is arranged in a peripheral region, whereby the different voltages can be provided as a precharge voltage in accordance with the active state and the standby state and thus leakage current is reduced and area efficiency is enhanced.

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.

Abstract: A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.

Abstract: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Abstract: An electrical circuit contains volatile states that are lost without continued application of power to circuit elements to preserve their volatile states. A first power source in the circuit provides power to the volatile state circuit for holding and preserving their volatile states. A power selection circuit is coupled to the circuit elements and has a plurality of selectable modes. A first mode of operation of the power selection circuit is selected when the circuit elements are to be operated at a first power level via the first power source which constitutes a first mode of operation. A second mode of operation is selected when the volatile state circuit elements are to be operated under a condition where the first power source is inactivated, such as, for example, during a circuit backup or standby operation.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Abstract: Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: A semiconductor integrated circuit device including a memory circuit with both high access efficiency and high memory efficiency in a simple configuration is provided. In a memory read control circuit, burst length is changed based on whether or not a read instruction is issued at a cycle after a cycle at which a read instruction /R is issued. And, in a memory write control circuit, burst length is changed based on whether or not a write instruction is issued at a cycle before a cycle at which a write instruction /W is issued.

Abstract: The invention encompasses beam expanders and methods of using such beam expanders. A beam expander according to the present invention may advantageously be used with an interferometer. Beam expanders according to the present disclosure contain at least an input and an output lens, with the output lens having a plano-convex arrangement such that the surface of the output lens is optically flat and can be used as the reference surface in a Fizeau interferometer. The beam expander may also encompass a housing, a partially reflective coating and an anti-reflective coating.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: A method and apparatus for spread spectrum distance and for spread spectrum velocity profile measurement is provided where the short pulse of traditional ultrasonic and radar level gauges is replaced by low peak power direct sequence spread spectrum (DSSS) modulated energy. An echo sequence subtraction process is provided that increases the signal to noise ratio of each echo sequence thus increasing the dynamic range of the system. In addition to providing a higher signal to noise ratio (SNR), better precision and accuracy in ranging Doppler applications and the ability to use lower peak power transmissions, the system is more immune to interference from the environment and allows for less expensive and less bulky ultrasonic transducers.

Abstract: An apparatus and method for seismic data acquisition is provided, which, in one aspect, define a plurality of attributes relating to acquisition of seismic data by the apparatus, determine a value of each attribute when the apparatus is deployed for acquiring seismic data, generate a message for each attribute whose determined value meets a selected criterion, and transmit wirelessly each generated message to a remote unit without solicitation of such a message by the remote unit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A system for use with a boat to provide underwater sonar images includes a GPS receiver for providing GPS position data, a left side scan sonar transducer for transmitting left side scan sonar pulses and for receiving left side scan sonar return signals, and a right side scan sonar transducer for transmitting right side scan sonar pulses and for receiving right side scan sonar return signals. The system further includes signal processing circuitry for processing the left and right side scan sonar return signals to produce side scan image data and a digital processor for causing a display to display an underwater image based upon the side scan image data, wherein the digital processor associates GPS position and side scan image data.

Abstract: Acoustic ranging may involve determining a distance between a first device and at least one other device using one or more acoustic signals. In an example embodiment, a first device emits a first acoustic signal and then receives the first acoustic signal at a first time. The first device also receives a second acoustic signal at a second time, with the second acoustic signal having been emitted by a second device. The first device ascertains a first value that reflects a difference between the first time and the second time. Responsive to at least the ascertained first value, the first device determines a distance between the first device and the second device.

Abstract: A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.

Abstract: A device for indicating the passage of two or more time intervals is provided. In one embodiment, the device includes a base portion with a user interface and a light portion. The light portion includes three lights of different colors that are disposed in a vertical arrangement above the base portion. The user interface includes a display and a keypad for programming the device with one or more time durations, and for associating one or more of the lights with each time interval. A controller is in communication with the user interface and operatively coupled with the lights to illuminate and turn off each light during its associated interval. The device may include an audio section linked to the controller for further indicating the intervals or transitions therebetween by outputting one or more sounds.

Abstract: An electronic timepiece with a generator function, including a generator, a battery or the like that stores electrical energy produced by the generator, a timekeeping controller that is driven by the stored electrical energy, a time display that is controlled by the timekeeping controller and displays time, a generator output detector that detects peaks of an electrical characteristic of the power generated by the generator, a remaining operating time calculator that integrates the average values corresponding to detected peaks and calculates a remaining operating time, and a remaining operating time display that displays the remaining operating time calculated by the remaining operating time calculator.

Abstract: A recording medium, and a method and apparatus for reformatting the recording medium are disclosed. The method for reformatting a recording medium includes the steps of: (a) reading a plurality of physical access control information of the recording medium in a plurality of recording units; and (b) performing an initialization process for each recording unit upon receiving a reformatting command associated with the plurality of recording units, wherein the initialization process is differently performed according to an attribute of information recorded in each recording unit. Therefore, the PAC area contained in a high-density optical disc can be efficiently reformatted.

Abstract: Audio data which are read out from a compact disc drive are written into a hard disk drive (6) at a rate that is higher than an audio playback rate. The written audio data are read out at a rate which is higher than the audio playback rate, and than output to audio output interfaces (buffer memories). The audio output interfaces read out the audio data at the playback rate and output the data. Since the hard disk drive (6) can perform reading/writing at a rate which is sufficiently higher than the playback rate of audio data, monitoring is enabled while performing ripping.

Abstract: An information recording medium 1 at least comprises a substrate 13 having a microscopic pattern 20, which is constituted by a shape of continuous substance of approximately parallel grooves formed with a groove section G and a land section L alternately, a recording layer 12 formed on the microscopic pattern 20 and a light transmission layer 11 formed on the recording layer. The microscopic pattern 20 is formed so as to satisfy a relation of P<?<NA and a thickness of the light transmission layer 11 is within a range of 0.07 to 0.12 mm, wherein P is a pitch of the groove section G or the land section L, ? is a wavelength of reproducing light beam and NA is a numerical aperture of an objective lens. Further, there provided an information recording medium, which is improved in cross erase and recorded in high density, and a reproducing apparatus and a recording apparatus for the information recording medium.

Abstract: An information recording medium 1 at least comprises a substrate 13 having a microscopic pattern 20, which is constituted by a shape of continuous substance of approximately parallel grooves formed with a groove section G and a land section L alternately, a recording layer 12 formed on the microscopic pattern 20 and a light transmission layer 11 formed on the recording layer. The microscopic pattern 20 is formed so as to satisfy a relation of P<?<NA and a thickness of the light transmission layer 11 is within a range of 0.07 to 0.12 mm, wherein P is a pitch of the groove section G or the land section L, ? is a wavelength of reproducing light beam and NA is a numerical aperture of an objective lens. Further, there provided an information recording medium, which is improved in cross erase and recorded in high density, and a reproducing apparatus and a recording apparatus for the information recording medium.

Abstract: The objective lens driving device of the present invention for an optical pickup device is provided. The device includes first and second objective lenses, and a lens holder for supporting the first and second objective lenses. The lens holder has a first through-hole for passage of first laser beam and a second through-hole for passage of second laser beam. Where a plane defined by a central axis of the first objective lens and a central axis of the second objective lens is a central plane, a plane perpendicular to the central plane and including the central axis of the first objective lens is a first plane, and a plane perpendicular to the central plane and including the central axis of the second objective lens is a second plane; the first through-hole is asymmetrical with respect to the first plane and/or the second through-hole is asymmetrical with respect to the second plane.

Abstract: An optical disk apparatus includes a movable part having an objective lens for focusing a laser beam onto an optical disk. A lens-holding member holds the objective lens. A protecting member prevents contact of the objective lens with the optical disk. The protecting member is spaced apart from the optical disk. An elastic supporting member supports the movable part, and an actuator drives the movable part toward or away from the optical disk. The apparatus is constructed so as to maintain the protecting member spaced apart from the optical disk, even when the elastic supporting member is bent by gravity toward the optical disk.

Abstract: An apparatus for obtaining a push-pull signal is disclosed. The apparatus includes: a first amplifier coupled to a first fluctuating signal for utilizing a first gain value to amplify the first fluctuating signal and then outputting a first amplified fluctuating signal; a second amplifier coupled to a second fluctuating signal for utilizing a second gain value to amplify the second fluctuating signal and then outputting a second amplified fluctuating signal; a subtractor electrically connected to the first and second amplifiers for subtracting the second amplified fluctuating signal from the first amplified fluctuating signal to generate the push-pull signal; and a level decision unit electrically connected to the first and second amplifiers for controlling the amplitudes of signals amplified by the first and second amplifiers when the optical disc drive is switched from a first operating mode to a second operating mode.

Abstract: An optical disc drive apparatus may include an optical pickup that moves along a transportation shaft provided along a radial direction of an optical disc and picks up reflected light after emitting an optical beam via an objective lens to the optical disc; a drive section that controls the objective lens to adjust an angle of the optical beam; an angular velocity detection section that detects an angular velocity around the transportation shaft; storage means for storing coefficients from which the skew of the optical disc around a virtual axis perpendicular to the transportation shaft is calculated using the angular velocity; a skew estimation section that calculates a skew estimate value by multiplying the coefficient by the angular velocity; and a drive signal generation section that generates a drive signal based on the skew estimate value to enable the drive section to adjust the angle of the optical beam.

Abstract: A method is provided for recording visible marks on a recording medium using an input beam generated by an electromagnetic radiation source. The method comprises (a) substantially collimating the input beam to provide a substantially collimated beam, and (b) applying the substantially collimated beam to the recording medium to provide the visible mark on the recording medium.

Abstract: The present invention aims to smoothly and adequately adjust recording laser power while an increase in processing load during recording is suppressed. When a recording operation start request is received, OPC is executed with reference to a target ? value (?t) of a disc to set recording laser power Pws. Recording operation is performed based on the set recording laser power Pws. When a system is brought into an intermittent standby state, R-OPC is executed, so the recording laser power Pws is adjusted and set again. Then, its subsequent recording operation is performed based on the recording laser power Pws which is set again. When a duration of the recording operation exceeds a maximal waiting time Ts, the recording operation is suspended so that the system is set to a recording standby state. Then, the R-OPC is executed, so that the recording laser power Pws is adjusted and set again.

Abstract: Test signals are recorded on a prescribed area in an optical disc. The prescribed area is scanned by a laser beam while the power of the laser beam is changed among different DC erasing values. The different DC erasing values are assigned to the recorded test signals, respectively. The recorded test signals are reproduced from the prescribed area to obtain reproduced signals. Parameter values of the respective reproduced signals are detected. The detected parameter values correspond to the different DC erasing values, respectively. Among the detected parameter values, a detected parameter value is decided which matches a target. One corresponding to the decided parameter value is selected from the different DC erasing values. A prescribed coefficient and the selected DC erasing value are multiplied to calculate an optimum level of an erasing power of the laser beam.

Abstract: The present invention discloses read and write power control methods and system for an optical recording device that records information on an optical disk having read-only areas. The read and write power control methods respectively introduce the steps of determining a specific level of a former power control signal output based on a former power control, and then according to the specific level, setting a predetermined level of a power control signal to induce a present power control for rapidly outputting a proper power of the pick-up head. Accordingly, the level transition of the read/write power control signal can be shortened and even eliminated. An unstable read/write power output for the pick-up head can be avoided.

Abstract: A method for adjusting a tilt angle of a light beam emitted by an optical pickup unit of an optical disc drive, the method includes steps of adjusting the tilt angle of the light beam according to test parameters preinstalled in the optical disc drive; detecting focusing error signals, the focusing error signals being generated based on the light beam reflected from an optical disc; generating current parameters based on the focusing error signals; storing the current parameters; adjusting the tilt angle of the light beam according to the current parameters.

Abstract: The invention provides an optical disk device that has a laser unit including a first objective lens and a second objective lens. A numerical aperture of the first objective lens is different from a numerical aperture of the second objective lens. The optical disk device has a first focus driver that detects a first voltage value indicating the value of a driving voltage to drive the first objective lens when light beams are irradiated onto the surface of an optical disk via the first objective lens and a focus is achieved. The optical disk device has a second focus driver that detects a second voltage value indicating the value of a driving voltage to drive the second objective lens when light beams are irradiated onto the recording surface of said optical disk via the second objective lens and a focus is achieved. The optical disk device has a controller that discriminates the type of an optical disk, based on a difference between the first voltage value and the second voltage value.

Abstract: A wobble signal generating apparatus of an optical-electronic system. A first operation unit for generating a reference signal in response to a first input signal and a second input signal that are derived from a plurality of light signals reflected from an optical storage medium is provided. The plurality of reflected light signals is used for generating the reference signal even when the optical-electronic system is recording data onto the optical storage medium. A processing unit processes the reference signal to generate the wobble signal.

Abstract: A recording method for dye-based recordable DVD medium which includes recording shortest marks on a recording layer primarily containing an organic dye using a simple rectangular wave pulse; recording marks each having the second shortest or still longer mark length using one pulse of which the front and rear edges are highly energized for a given time; and controlling the optical energy for irradiating rear edge or backward of the pulse with a cooling pulse to be 0.1 mW or less for a given time, wherein when the recording power of the front and rear edges of the respective pulses is represented by P1 and the recording power of intermediate pulse between the pulse front edge and the pulse rear edge is represented by P2, P1/P2 is set to be greater when P1 is a low power, and P1/P2 is set to be smaller when P1 is a high power.

Abstract: An optical information reproducing apparatus and an optical information reproducing method using the same are provided. The optical information reproducing apparatus includes: a light source; a beam splitter which splits a beam emitted from the light source into a reference beam and a temporary beam; a temporary beam splitter which splits the temporary beam into a pair of assistant beams; an incident optical system which inputs the reference beam and the assistant beams to a recording medium in which optical information is recorded; a reproduction beam detector which detects reproduction beams reproduced in response to the reference beam, sets the position of the reproduction beam having the largest light intensity as a reference position, and sets a signal region on the basis of the reference beam; and an assistant beam detector which compares the light intensity of the assistant beams incident on the signal region with each other and sets an incident angle of the reference beam.

Abstract: An optical information processing apparatus is provided. The optical information processing apparatus includes: an optical system which irradiates a reference beam on an optical information recording medium having a plurality of recording regions adjacent to each other so that the reference beam is wider than each of the recording regions; a filter which filters readout beams reproduced from the optical information recording medium to pass a selected readout beam reproduced from a selected recording region and separates neighborhood readout beams reproduced from neighborhood of the selected recording regions; a readout beam detector which detects the selected readout beam passing through the filter; a neighborhood readout beam detector which detects the neighborhood readout beams separated by the filter; and a controller which compares the neighborhood readout beams detected by the neighborhood readout beam detector to control a reproduction condition of the selected readout beam.

Abstract: A wavefront aberration compensation element includes a wavelength selection phase plate having a plurality of phase steps having various thicknesses at various areas, a liquid crystal layer for obtaining a prescribed wavefront aberration, and a pair of first and second electrode layers having the liquid crystal layer disposed therebetween, wherein either one of the wavelength selection phase plate and the pair of first and second electrode layers having the liquid crystal layer disposed therebetween is stacked on the other.

Abstract: There is provided a diffractive element including a first member 2, which includes a first resin 2a and has a predetermined refractive index, and a second member 3, which has the same refractive index as the first member 2 having the predetermined refractive index in one wavelength of light and has a refractive index different from the first member 2 having the predetermined refractive index in the other wavelength of light. The first member 2 and the second member 3 are alternately arranged within an incidence plane of the two wavelengths of light, thereby constituting a diffraction grating. The second member 3 includes a second resin 3a to dissolve an organic matter 5 having optical absorption in a predetermined wavelength range at a molecular level, whereby the refractive index of the second member 3 is formed.

Abstract: An optical pickup which includes first to third light sources each emitting a light beam each having a first to third wavelength; an objective lens condensing each of the light beams emitted from the light sources on a signal recording face of an optical disc; a collimator lens provided between the light sources and the objective lens to convert a divergent angle of each of the light beams emitted from the light sources so as to obtain a parallel light beam; and a diffractive optical element provided between the collimator lens and the objective lens. The diffractive optical element includes first and second diffractive parts which respectively diffract the light beam having the second wavelength and the third wavelength. The second diffractive part has a diffraction structure formed by a plurality of concentric ring zones, having first to fourth optical faces, each having a different height in an optical axis direction.