Abstract: In a package mounting structure for mounting a package on a case, wherein the package internally incorporates at least one of a high-frequency transistor, MIC and MMIC used in the microwave to millimeter-wave band, and a base thereof is formed of metal and serves as ground, an electrically conductive sheet having excellent thermal conductivity and exhibiting restorability and having a size identical with that of the base of the package is laid on the case at a package-bearing location, the package and sheet are fastened together by two or more screws, and the sheet is mounted on the case while it is pressed by a pressing force of 10 N/cm2 or greater owing to fastening.

Abstract: An EMI shield for a transceiver module includes a plurality of collapsible fingers that allow the shield to be sealed at the corners when the transceiver is inserted into a receiving cage. The fingers of the shield are made with a designed interference with the cage, so that the fingers are compressed when the module is inserted into the cage. A pattern of peaks and valleys on the fingers bordering the corners of the shield allows the two adjacent fingers to mesh when the module is inserted into the cage. The meshing of the peaks-and-valleys pattern of the bordering fingers allows the shield to be sealed with a gap width under 0.015?.

Abstract: Electronic devices can be provided with at least one first circuit component coupled to a first circuit board, at least one second circuit component coupled to a second circuit board, and a mating assembly coupled to the boards for holding them in a vertical stack. The first circuit components can face the second circuit components in the stack. One or more of the first circuit components can be horizontally offset from one or more of the second circuit components in the stack to reduce the thickness of the mated circuit boards. Portions of the circuit boards and the mating assembly can shield the circuit components of the stack from electromagnetic interference.

Abstract: A harness wiring structure includes a first link that has a first fixing member, a second link that has a second fixing member, and a shaft portion that swingably connects the first link to the second link. When the first link and the second link are extended to each other, a wire harness is wired in a straight line so as to pass above the shaft portion and is fixed to the first link and the second link by the first fixing member and the second fixing member respectively.

Abstract: The present invention discloses a secondary side-driven half-bridge power supply, which has a half-bridge transformer. A MOSFET unit is connected to the primary side of the half-bridge transformer, and an output rectifier/filter circuit connected to the secondary side of the half-bridge transformer. In the present invention, a PWM controller generates a control signal and sends the signal to a separating element. The control signal is used to drive the MOSFET unit, and the MOSFET unit then drives the half-bridge transformer. The output rectifier/filter circuit processes the signal output by the half-bridge transformer to provide voltages for external loads. The present invention can increase the power efficiency, raise the working frequency, and reduce the cost.

Abstract: A power conversion circuit capable of varying an output voltage within a range from a negative voltage lower than a ground voltage to a positive voltage higher than a supply voltage, and a driving method and a drive unit are provided. A power conversion circuit includes a transformer with a 1:1 ratio between the primary winding and secondary winding, a voltage outputting capacitor, and four switches. The power conversion circuit can be operated as a DC-DC converter of a step-up type, a step-up-and-down type, a step-down type, an inverted-output step-up-and-down type, or an inverted-output step-up type by selecting two switches used for control from among the four switches and alternately turning the two switches on. By switching the operating modes of the power conversion circuit, the output voltage can be varied within a range from a negative voltage to a positive voltage higher than a supply voltage.

Abstract: In one embodiment, a power converter system includes an input terminal for an input voltage. A transformer, coupled to the input terminal, has a primary winding and a secondary winding. An output terminal is coupled to the secondary winding. Power is delivered to a load of the power converter system at the output terminal. A first control module, coupled through a relay to a tap terminal to the primary winding of the transformer, operates the power converter system if a magnitude of the input voltage is within a low voltage range. A second control module, coupled at an end terminal of the primary winding of the transformer, operates the power converter system if a magnitude of the input voltage is within a high voltage range.

Abstract: In an isolated DC-DC converter, an on-period control circuit generates an off-timing signal when the output voltage of an isolated DC-DC converter exceeds a reference voltage. A signal reception/power switch driving circuit causes a first switching device to be turned on based on a pulse signal for switching that is output from a PWM control circuit, and causes the first switching device to be turned off based on an off-timing signal transmitted by an off-timing signal transmission unit. A bootstrap circuit boosts a control voltage of the first switching device with the pulse signal for switching that is output from the PWM control circuit.

Abstract: The present invention provides a switching power supply that enables a reduction in noise without the need for an anti-noise component such as a filter circuit. A secondary current on period detecting circuit detects a first period during which a secondary current flows, the secondary current starting to flow through a secondary winding after a switching element is turned off. A secondary current on duty control circuit oscillates a clock signal set turning on the switching element so as to maintain, at a constant value, an on duty ratio of the first period to a third period made up of the first period and a second period during which the secondary current does not flow. A secondary current on duty modulating circuit applies a modulation component to the on duty ratio to periodically modulate the on duty ratio and thus the oscillation frequency of the switching element.

Abstract: In a method for controlling a rectifier and an inverter, which are connected together by a direct current circuit, a measuring direct current voltage and respectively, a measuring direct current are measured at at least one measuring point of the direct current circuit and are transmitted to a direct current control for controlling the rectifier and/or an inverter control for controlling the inverter. The direct current control controls the rectifier in such a manner that a total of a difference direct current voltage and a differential direct current is minimal and the inverter control of the inverter is controlled in such a manner that the difference between the differential direct current of the differential direct current voltage is minimal. The method is reliable and is economical. Accordingly, the desired flow of the direct current control and the desired flow of the inverter control are identical.

Abstract: The provided current source inverter includes a buck converter having an input capacitor and an output inductor, receiving a DC input voltage, and generating an output inductor current, a DC/AC converter having an output capacitor, receiving the output inductor current and generating an AC output voltage, a load coupled to the DC/AC converter, and an energy clamp circuit coupled to the buck and the DC/AC converters. The energy clamp circuit includes a first diode and a second diode, provides a discharging route while the load is disconnected with the output capacitor such that the electrical power stored at the output inductor could be discharged to the output capacitor and the input capacitor and avoids an inrush current.

Abstract: A sampling method with adjusting duty ratios is provided and includes the following steps. A first working pulse signal which has a pulse-width duty ratio D in a switching period Ts is provided. A first adjusting period comprising first N successive switching periods of the first working pulse signal is set, wherein N is a natural number larger than 1. A second working pulse signal which has second N successive switching periods with their corresponding pulse-width duty ratio D1, D2, . . . , DN to drive the switch in the converter circuit is provided and the measured signal is generated, wherein the sum of D1, D2, . . . , DN substantially equals to N·D and the second N successive switching periods constitute a second adjusting period.

Abstract: A voltage tripler circuit includes a plurality of switches and first, second, and third capacitors each having first and second terminals that are selectively interconnected via the plurality of switches. The first capacitor charges to a supply voltage during a first phase. The second capacitor charges to two times the supply voltage during a second phase that follows the first phase. The third capacitor charges to three times the supply voltage during a third phase that follows the second phase. The voltage tripler circuit draws the same peak current from a source of the supply voltage at a beginning of each of the first, second, third phases.

Abstract: At least three power converters in a power distribution and power transmission system can be controlled as rectifiers or inverters and are connected together by a direct current network. A measuring direct current voltage and a measuring direct current are measured on each power converter and respectively, transmitted to the respective rectifier control and/or inverter control, and a rectifier desired direct power and/or inverter desired direct power is determined for each power converter.

Abstract: A hold-up time extension controlling device for a power supply, that has a power factor correction circuit, a hold-up time extension circuit, a hold-up time controlling circuit, a storage capacitor and a DC to DC converter. The hold-up time extension controlling device has a switch and an auxiliary capacitor. When an AC power source is normal, the switch is controlled to turn on according to the power factor correction circuit to make the auxiliary capacitor connecting to the storage capacitor in parallel to averagely have a ripple current. When the AC power source is interrupted, the switch is controlled to turn off. At the time, the hold-up time extension circuit obtains a storage power of the auxiliary capacitor and then output to the DC to DC converter to keep the voltage of the storage capacitor at a preset voltage for a long time.

Abstract: A DC/DC power conversion device with smoothing capacitors including three column circuits share the smoothing capacitors to be connected in parallel, each column circuit have a plurality of circuits connected in series where two MOSFETs are connected in series between both ends of respective smoothing capacitors and LC serial bodies of capacitors and inductors with the same resonant cycle are disposed between the circuits at two middle terminals. Driving signals for the respective column circuits have the same driving cycle identical with the resonant cycle of the LC serial bodies, and are out of phase with each other by 2?/3(rad), and thus charge-discharge currents towards the smoothing capacitors are circulated among the column circuits and ripple currents flowing through the smoothing capacitors are reduced.

Abstract: A power converter that converts an AC power outputted from a generator into a DC power and supplies it to a battery (load). The power converter includes a thyristor (switch unit) connected between an output unit of the generator and the battery (load); and a gate control unit (control unit) for generating a triangle wave voltage having a constant peak voltage corresponding to each cycle of the AC power outputted from the generator, generating a differential voltage between the voltage supplied to the load via the switch unit and a predetermined target voltage, and controlling the conductive state of the switch unit based on the triangle wave voltage and the differential voltage.

Abstract: A power converter and power conversion method wherein operation of a switching element is controlled by the frequency of a carrier wave where the frequency is varied such that the same frequency of the carrier wave is not repeated during a single modulation period.

Abstract: A semiconductor circuit for driving a load, comprising a transformerless Alternative Current (AC) to Direct Current (DC) converter integrated circuit that includes a high voltage circuit fabricated on a substrate for converting a high voltage AC input signal to a first high voltage DC output signal. Further included is a second circuit fabricated on the same substrate for regulating a drive signal for driving a load using power from the first high voltage output signal, with the high voltage circuit and the second circuit fabricated on the substrate to form a single integrated circuit (IC) chip.

Abstract: A method for thermal protection of a frequency converter and a frequency converter includes means for controlling the output current of the frequency converter. The method includes the steps of determining predetermined data points which define a thermal current limit for a semiconductor component of the frequency converter at specific temperatures at plural switching frequencies, and determining predetermined data points which define a thermal current limit for the semiconductor component at specific temperatures at a zero converter output frequency. The method also includes determining the highest allowable thermal current as a function of a measured temperature, a determined switching frequency, and a determined output frequency based on the defined data points, and limiting the output current of the frequency converter to the determined highest allowable thermal current.

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.

Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.

Abstract: A system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via a integrated circuit buffer device) on a first signal path to the master and a second memory module simultaneously provides read data from its plurality of integrated circuit memory devices (via another integrated circuit buffer device on the second module) on a third signal path coupled to the master device.

Abstract: A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB).

Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Abstract: An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.

Abstract: A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines are kept at a supply voltage VDD to ensure that unwanted rows will not have any sub-threshold current (as Vds=0). So during read “1” operation (that is when bit line (BL) is high) load cells would not leak unnecessarily. Thus the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising includes either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation.

Abstract: A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An error correction circuit corrects any error in retained data in the memory cells sensed by the sense amplifier. A plate line control circuit controls the timing for switching a potential of the plate line to a ground potential, based on absence or presence of error correction by the error correction circuit.

Abstract: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, each having memory cells, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed the word lines to the read/write circuit. The memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.

Abstract: A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.

Abstract: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

Abstract: A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.

Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

Abstract: The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.

Abstract: A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.

Abstract: Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell.

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M?1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.

Abstract: Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.

Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.

Abstract: The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.

Abstract: A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided adjacent to the drain selecting line; and selecting a word line to program memory cells coupled to the selected word line to perform an even LSB program operation and an odd LSB program operation for the selected first word line. Each of the word lines is selected until all of the word lines have been selected, so that the even LSB program operation and the odd LSB program operation can be performed for all of the word lines. The even LSB program operation is performed to store a lower rank data bit in memory cells coupled to an even bit line assigned a selected word line.

Abstract: In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.

Abstract: A bit line select voltage generator includes a first voltage generator, a second voltage generator, and a voltage transmission unit. The first voltage generator is configured to divide a reference voltage of a reference voltage generator, generate a control voltage, and generate a first voltage in response to the control voltage. In this case, the first voltage is raised according to an increase of a temperature and output. The second voltage generator is configured to divide the reference voltage and generate a second voltage of a level lower than that of the first voltage. The voltage transmission unit is configured to transmit the first voltage or the second voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.

Abstract: Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

Abstract: Selective program acceleration of a memory device is generally described. A method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality of cells at a target threshold voltage to determine whether one or more cells of the plurality of cells have reached or surpassed the target threshold voltage, identifying slower cells of the plurality of cells, and selectively accelerating a program speed of the slower cells to reduce a programming time of a memory device.

Abstract: A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.