Abstract: Disclosed is a test device and a method for qualitatively and/or quantitatively measuring the concentration of an analyte in a biological fluid sample. The test device includes a housing defining a sample port, a test well containing a stirrer and a conjugate, and a test strip disposed within the housing. The test well is also defined by being located between the sample port and the test strip. Fluid flows from the test well onto the test strip, which has a trapping zone which binds the analyte and allows for its detection. A control zone may also be included. The test device is generally adapted to use a sandwich assay. Also disclosed is a system comprising the test device and a signal sensing device; and a method for using the test device.

Abstract: A method and apparatus for the manipulation of colloidal particles and biomolecules at the interface between an insulating electrode such as silicon oxide and an electrolyte solution. Light-controlled electrokinetic assembly of particles near surfaces relies on the combination of three functional elements: the AC electric field-induced assembly of planar aggregates; the patterning of the electrolyte/silicon oxide/silicon interface to exert spatial control over the assembly process; and the real-time control of the assembly process via external illumination. The present invention provides a set of fundamental operations enabling interactive control over the creation and placement of planar arrays of several types of particles and biomolecules and the manipulation of array shape and size. The present invention enables sample preparation and handling for diagnostic assays and biochemical analysis in an array format, and the functional integration of these operations.

Abstract: Disclosed is a diagnostic testing device that may be used to detect one or more analytes in a sample. The device comprises a receptacle and a holder for a test strip. The test strip may be, for example, a lateral flow test strip. The device and holder permit analysis of a sample, wherein the device is substantially sealed during testing and detection of results. To use, the holder containing a test strip is inserted into the receptacle containing sample to be analyzed. Capillary flow along the test strip is initiated by contact of the sample with the distal end of the test strip. The receptacle is such that results of the assay may be detected visually or using standard instrumentation such as by measuring light absorption or reflectance.

Abstract: The invention relates to liquid flow assays widely applicable to target analytes, including haptens, which employ a detection zone which is a single combined analyte detection and control zone in a test strip or sheet and two labelled reagents with detectably distinguishable labels, preferably with visually contrasting colored particle labels, whereby both negative and positive samples are distinguishable by detection of different captured label signals in the detection zone.

Abstract: A low-temperature poly-crystalline thin film transistor in which amorphous silicon is crystallized using a laser crystallization method or a metal induced lateral crystallization method shows an unstable electrical property since crystallization is accomplished at a low temperature. When an electrical stress is applied to the low-temperature poly-crystalline thin film transistor and a lower substrate for a display device including the same, an electrical feature thereof is enhanced. To apply an electrical stress to the low-temperature poly-crystalline thin film transistor, the source of a thin film transistor is grounded, and a critical voltage which is determined according to a gate voltage applied between the drain and the source of the thin film transistor, at a state where any gate voltage has been applied between the gate and the source of the thin film transistor.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

Abstract: The invention relates to a polymer optoelectronic device comprising at least a transparent conductive oxide layer, an active polymer layer, a back electrode layer and a substrate layer, wherein the transparent conductive oxide (TCO) layer has a controlled surface structure which is characterized by having an X-value in the range of from 10 nm to 500 nm, and a Y-value in the range of from 15 nm to 1000 nm, wherein the ratio between the X-value and the Y-value (X/Y) is at most 1, whereby the X-value is defined as the average value of the height of the peaks on the surface, the Y-value is defined as the average peak to peak distance on the surface, and both the X and Y values are measured by means of SEM (Scanning Electron Microscopy) or Atomic Force Microscopy (AFM).

Abstract: A method for manufacturing a light-emitting diode having a high heat-dissipating efficiency forms a thickened metal into a plurality of supports. The support has a first electrode and a second electrode thereon. The first electrode is formed with a trough. The chip that emits a visible light or an invisible light is adhered in the trough. Then, two leads are welded on the chip. One end of each of the two leads is welded to the first and second electrodes respectively. Various glues are dotted on the chip, adhesive, leads and the support. Finally, the glue is formed into a seat and lens having a packaged chip, adhesive, leads and support by means of a hot press-forming process.

Abstract: An improved method of forming a LED with a roughened surface is described. Traditional methods of roughening a LED surface utilizes strong etchants that require sealing or protecting exposed areas of the LED. The described method uses a focused laser to separate the LED from the substrate, and a second laser to roughen the LED surface thereby avoiding the use of strong etchants. A mild etchant may be used on the laser roughened LED surface to remove unwanted metals.

Abstract: A method of forming a display panel includes providing a first substrate having a transparent electrode, and a second substrate having a pixel electrode. Subsequently, an alignment material is provided and covers on the transparent electrode and/or the pixel electrode, and a photoelectric twisting layer is provided between the first substrate and the second substrate. The alignment material is first in a non-aligned state, and is radiation-polymerizable. The photoelectric twisting layer does not include any radiation-polymerizable material. Thereafter, a voltage difference is applied to drive molecules of the photoelectric twisting layer, and a radiating process is performed on the alignment material. The twisted molecules of the photoelectric twisting layer induce the surface molecules of the alignment material to arrange in an ordered state, and the alignment material is polymerized according to the ordered state as a first alignment film.

Abstract: A fabricating method of Single Electron Transistor includes processing steps as follows: first, deposit the sealing material of gas molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a reduced nano-aperture, whose opening diameter is smaller than that of said top-opening; then, keep the substrate in horizontal direction and tilt or rotate said substrate into tilt angle or rotation angle in coordination with tilt angle with the reduced nano-aperture as center respectively, and pass the deposit material of gas molecular or atom state through the reduced nano-aperture respectively. Thereby a Single Electron Transistor including island electrode, drain electrode, source electrode and gate electrode of nano-quantum dot with nano-scale is directly fabricated on the surface of said substrate.

Abstract: The present invention provides a manufacturing method of a group III nitride semiconductor light-emitting device, including a lamination step of forming a plurality of lamination films including a group III nitride semiconductor on a substrate, in which a substrate on which is formed a foundation layer including a monocrystalline group III nitride semiconductor is used as the substrate, and lamination films are formed on the foundation layer by a sputtering method, with the substrate including the foundation layer and a target made from a group III metal or an alloy including a group III metal being placed in a sputtering chamber.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Provided is a method of forming quantum dots, including: forming a buffer layer on an InP substrate so as to be lattice-matched with the InP substrate; and sequentially alternately depositing In(Ga)As layers and InAl(Ga)As or In(Ga, Al, As)P layers that are greatly lattice-mismatched with each other on the buffer layer so as to form In(Ga, Al)As or In(Ga, Al, P)As quantum dots.

Abstract: A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other.

Abstract: A process producing a single-crystalline device fabricated on a single-sided polished wafer employing processing from only the front-side and having a significant separation between the device and substrate is provided. In one embodiment, a method comprises an upper layer and a lower substrate. A device is formed in the upper layer, defined by gaps. The gaps are filled with at least one material that has etch characteristics different from those of the device and the substrate. At least a top portion of the gap material is removed from the upper layer. The gap material is etched so that a portion of the gap-material remains on the sidewalls of the surrounding upper layer. The material beneath the device is then etched, excluding an insulating layer beneath the device, releasing the device from the substrate. The insulating material beneath the device is then etched, the etch being selective to the insulating material and the gap material.

Abstract: A photoelectric conversion device comprises a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type serving as a photoelectric conversion element together with a part of the first semiconductor region; a gate electrode transferring electric carriers generated in the photoelectric conversion element to a third semiconductor region of the second conductivity type. Moreover, the photoelectric conversion device comprises an isolation region for electrically isolating the second semiconductor region from a fourth semiconductor region of the second conductivity type adjacent to the second semiconductor region. Wiring for applying voltage to the gate electrode is arranged on the isolation region. Here, a fifth semiconductor region of the second conductivity type having an impurity concentration lower than that of the fourth semiconductor region is provided between the fourth semiconductor region and the isolation region.

Abstract: A sensor comprising a semiconductor film having a plurality of mesopores and containing an oxide, and electrodes electrically connected to the semiconductor film, wherein at least part of surfaces in the mesopores is coated with an organic material.

Abstract: The present disclosure is broadly directed to a method for designing new MEMS micro-movers, particularly suited for, but not limited to, CMOS fabrication techniques, that are capable of large lateral displacement for tuning capacitors, fabricating capacitors, self-assembly of small gaps in CMOS processes, fabricating latching structures and other applications where lateral micro-positioning on the order of up to 10 ?m, or greater, is desired. Principles of self-assembly and electro-thermal actuation are used for designing micro-movers. In self-assembly, motion is induced in specific beams by designing a lateral effective residual stress gradient within the beams. The lateral residual stress gradient arises from purposefully offsetting certain layers of one material versus another material. For example, lower metal layers may be side by side with dielectric layers, both of which are positioned beneath a top metal layer of a CMOS-MEMS beam.

Abstract: A method of making a Lateral-Moving Micromachined Thermal Bimorph which provides the capability of achieving in-plane thermally-induced motion on a microchip, as opposed to the much more common out-of-plane, or vertical, motion seen in many devices. The present invention employs a novel fabrication process to allow the fabrication of a lateral bimorph in a fundamentally planar set of processes. In addition, the invention incorporates special design features that allow the bimorph to maintain material interfaces.

Abstract: Methods of preparing electrodes, as well as related devices, components, systems, and methods, are disclosed.

Abstract: A thin solar cell is provided, a decreased amount of an Al paste used for the solar cell without occurrence of a problem of ball-up which is a defect in appearance. A method of manufacturing such a solar cell as well as a manufacturing apparatus used therefor are provided. This manufacturing method is applicable with substantially no change in the conventional material and process. The solar cell has an Al paste electrode on the back surface and at least a part of an outer edge of the Al paste is thicker than any remaining part.

Abstract: A method for manufacturing a solid state image pickup device in which a semiconductor substrate includes a pixel region where a plurality of pixels are arranged, each pixel including a signal charge accumulating portion and a transistor, and a pixel well of a first conductive type shared by the respective pixels, the method comprising: (a) a first step of forming a first impurity doped region by ion-implanting an impurity of the first conductive type to a surface of the semiconductor substrate together with the pixel well at a surface density of 1×1014 cm?2 or less in total; (b) a second step of forming an interlayer film after the first step; (c) a third step of forming a hole for providing a contact electrode in the interlayer film on the first impurity doped region; (d) a fourth step of forming a contact portion by ion-implanting an impurity of the first conductive type through the hole; and (e) a fifth step of forming the contact electrode by filling the hole.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device includes a cavity housing and a sensor chip. In one embodiment, the cavity housing has an opening to the surroundings. The sensor region of the sensor chip faces said opening. The sensor chip is mechanically decoupled from the cavity housing. In one embodiment, the sensor chip is embedded into a rubber-elastic composition on all sides in the cavity of the cavity housing.

Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

Abstract: Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks for integrating color filters and microlenses to the imager pixels residing on the frontside of the wafer, enabling high performance multispectral and high sensitivity imagers, including those with extremely small pixel pitch. In addition, the methods incorporate a passivation layer for protection of devices against external contamination, and allow interface trap density reduction via thermal annealing. Backside-illuminated imagers with illumination side electrical connections are also disclosed.

Abstract: Provided is a photoelectric conversion device including: a semiconductor substrate (3) of a first conductivity type; a photoelectric conversion region (7) of a second conductivity type which is located in the semiconductor substrate (3), the second conductivity type being opposite to the first conductivity type; and a buried layer (17) of the first conductivity type which is formed in an inner portion of the semiconductor substrate (3) to cover a lower side of the photoelectric conversion region (7), the buried layer (17) including a higher impurity concentration than the semiconductor substrate (3).

Abstract: Provided are a phase change memory device that can operate at low power and improve the scale of integration by reducing a contact area between a phase change material and a bottom electrode, and a method for fabricating the same. The phase change memory comprises a current source electrode, a phase change material layer, a plurality of carbon nanotube electrodes, and an insulation layer. The current source electrode supplies external current to a target. The phase change material layer is disposed to face the current source electrode in side direction. The carbon nanotube electrodes are disposed between the current source electrode and the phase change material layer. The insulation layer is formed outside the carbon nanotube electrodes and functions to reduce the loss of heat generated at the carbon nanotube electrodes.

Abstract: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

Abstract: An organic light-emitting device including a transparent conducting oxide layer as a cathode and a method of manufacturing the organic light-emitting device. The organic light-emitting device includes an anode disposed on a substrate. An organic functional layer including at least an organic light-emitting layer is disposed on the anode. The transparent conducting oxide layer used as the cathode is disposed on the organic functional layer. The transparent conducting oxide layer cathode is formed by plasma-assisted thermal evaporation. A microcavity structure is not formed in the organic light-emitting device, thereby avoiding a luminance change and a color shift as a function of viewing angle.

Abstract: It is an object of the present invention to provide a method for manufacturing an inexpensive organic TFT which does not depend on an expensive dedicated device and does not expose an organic semiconductor to atmospheric air. Moreover, it is another object of the present invention to provide a method for manufacturing an organic TFT at low temperature so as not to cause a problem of pyrolyzing a material. In view of the foregoing problems, one feature of the present invention is that a film-like protector which serves as a protective film is provided over an organic semiconductor film. The film-like protector can be formed by being fixed to a film-like support body with an adhesive agent or the like.

Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Abstract: A method for making a semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.

Abstract: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also electrically connects the integrated circuit to a plurality of exposed conductors.

Abstract: A method is disclosed for inhibiting oxygen and moisture penetration of a device comprising the steps of depositing a tin phosphate low liquidus temperature (LLT) inorganic material on at least a portion of the device to create a deposited tin phosphate LLT material, and heat treating the deposited LLT material in a substantially oxygen and moisture free environment to form a hermetic seal; wherein the step of depositing the LLT material comprises the use of a resistive heating element comprising tungsten. An organic electronic device is also disclosed comprising a substrate plate, at least one electronic or optoelectronic layer, and a tin phosphate LLT barrier layer, wherein the electronic or optoelectronic layer is hermetically sealed between the tin phosphate LLT barrier layer and the substrate plate. An apparatus is also disclosed having at least a portion thereof sealed with a tin phosphate LLT barrier layer.

Abstract: A heat dissipating structure includes: a heat spreader; and a plurality of compliant beams attached to the heat spreader. The beams are formed of a high-conductive material such that a maximum stress of each beam is less than a fatigue stress of the high-conductive material; said beams are placed at an angle relative to a chip surface such that the beams are able to exert bending compliance in response to x, y, and z forces exerted upon them. The structure also includes a thermal material interface for bonding said structure to the chip surface. Both the heat spreader and the compliant beams can be machined from a copper block. An alternative heat dissipating structure includes compliant beams soldered to the chip surface.

Abstract: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.

Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes positioning a substrate containing a metal nitride barrier layer within a process chamber and exposing the substrate to a reagent gas containing diborane to form a reagent layer on the metal nitride barrier layer. The method further provides exposing the substrate sequentially to a tungsten precursor and a reductant to form a nucleation layer during an atomic layer deposition (ALD) process and subsequently depositing a bulk layer over the nucleation layer. The bulk layer may contain copper, but generally contains tungsten deposited by a chemical vapor deposition (CVD) process. In some examples, the bulk layer may be used to fill apertures within the substrate.

Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.

Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Stripe shape or rectangular shape unevenness or opening is formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave oscillation laser light may also be used.

Abstract: It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.

Abstract: Disclosed is a manufacturing method of a thin film transistor, which enables the formation of a thin film transistor by using only one photomask. The method includes: over a substrate sequentially forming a first insulating film, a first conductive film, a second insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a resist mask thereover using a first photomask; performing a first etching to allow the side surface of the layers including an upper portion of the first insulating film, the first conductive film, the second insulating film, the semiconductor film, the impurity semiconductor film, and the second conductive film to be coplanar to a side surface of the resist mask; and performing a second etching to selectively etch the first conductive film to allow the side surface of the first conductive film is located inside the side surface of the layers.

Abstract: A method of fabricating a pixel structure includes first forming a first, a second, and a third dielectric layers over an active device and a substrate. Etching rates of the first and the third dielectric layers are lower than an etching rate of the second dielectric layer. A contact opening exposing a portion of the active device is formed in the third, the second, and the first dielectric layers. The third and the second dielectric layers are patterned to form a number of stacked structures. An electrode material layer is formed and fills the contact opening. The electrode material layer located on the stacked structures and the electrode material layer located on the first dielectric layer are separated. The stacked structures and the electrode material layer thereon are simultaneously removed to define a pixel electrode and to form at least an alignment slit in the pixel electrode.

Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.